230 lines
7.9 KiB
C
230 lines
7.9 KiB
C
/*
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* ARM Versatile Express emulation.
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*
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* Copyright (c) 2010 - 2011 B Labs Ltd.
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* Copyright (c) 2011 Linaro Limited
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* Written by Bahadir Balban, Amit Mahajan, Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "primecell.h"
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#include "devices.h"
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#include "net.h"
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#include "sysemu.h"
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#include "boards.h"
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#define SMP_BOOT_ADDR 0xe0000000
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#define VEXPRESS_BOARD_ID 0x8e0
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static struct arm_boot_info vexpress_binfo = {
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.smp_loader_start = SMP_BOOT_ADDR,
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};
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static void vexpress_a9_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env = NULL;
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ram_addr_t ram_offset, vram_offset, sram_offset;
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DeviceState *dev, *sysctl, *pl041;
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SysBusDevice *busdev;
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qemu_irq *irqp;
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qemu_irq pic[64];
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int n;
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qemu_irq cpu_irq[4];
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uint32_t proc_id;
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uint32_t sys_id;
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ram_addr_t low_ram_size, vram_size, sram_size;
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if (!cpu_model) {
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cpu_model = "cortex-a9";
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}
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for (n = 0; n < smp_cpus; n++) {
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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irqp = arm_pic_init_cpu(env);
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cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
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}
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if (ram_size > 0x40000000) {
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/* 1GB is the maximum the address space permits */
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fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
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exit(1);
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}
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ram_offset = qemu_ram_alloc(NULL, "vexpress.highmem", ram_size);
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low_ram_size = ram_size;
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if (low_ram_size > 0x4000000) {
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low_ram_size = 0x4000000;
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}
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/* RAM is from 0x60000000 upwards. The bottom 64MB of the
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* address space should in theory be remappable to various
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* things including ROM or RAM; we always map the RAM there.
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*/
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cpu_register_physical_memory(0x0, low_ram_size, ram_offset | IO_MEM_RAM);
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cpu_register_physical_memory(0x60000000, ram_size,
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ram_offset | IO_MEM_RAM);
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/* 0x1e000000 A9MPCore (SCU) private memory region */
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dev = qdev_create(NULL, "a9mpcore_priv");
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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vexpress_binfo.smp_priv_base = 0x1e000000;
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sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
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for (n = 0; n < smp_cpus; n++) {
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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}
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/* Interrupts [42:0] are from the motherboard;
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* [47:43] are reserved; [63:48] are daughterboard
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* peripherals. Note that some documentation numbers
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* external interrupts starting from 32 (because the
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* A9MP has internal interrupts 0..31).
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*/
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for (n = 0; n < 64; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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/* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
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sys_id = 0x1190f500;
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proc_id = 0x0c000191;
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/* 0x10000000 System registers */
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sysctl = qdev_create(NULL, "realview_sysctl");
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qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
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qdev_init_nofail(sysctl);
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qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
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sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
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/* 0x10001000 SP810 system control */
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/* 0x10002000 serial bus PCI */
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/* 0x10004000 PL041 audio */
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pl041 = qdev_create(NULL, "pl041");
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qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
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qdev_init_nofail(pl041);
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sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
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sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]);
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dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
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/* Wire up MMC card detect and read-only signals */
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qdev_connect_gpio_out(dev, 0,
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qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
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qdev_connect_gpio_out(dev, 1,
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qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
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sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
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sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
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sysbus_create_simple("pl011", 0x10009000, pic[5]);
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sysbus_create_simple("pl011", 0x1000a000, pic[6]);
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sysbus_create_simple("pl011", 0x1000b000, pic[7]);
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sysbus_create_simple("pl011", 0x1000c000, pic[8]);
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/* 0x1000f000 SP805 WDT */
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sysbus_create_simple("sp804", 0x10011000, pic[2]);
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sysbus_create_simple("sp804", 0x10012000, pic[3]);
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/* 0x10016000 Serial Bus DVI */
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sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
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/* 0x1001a000 Compact Flash */
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/* 0x1001f000 PL111 CLCD (motherboard) */
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/* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
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/* 0x10020000 PL111 CLCD (daughterboard) */
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sysbus_create_simple("pl111", 0x10020000, pic[44]);
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/* 0x10060000 AXI RAM */
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/* 0x100e0000 PL341 Dynamic Memory Controller */
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/* 0x100e1000 PL354 Static Memory Controller */
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/* 0x100e2000 System Configuration Controller */
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sysbus_create_simple("sp804", 0x100e4000, pic[48]);
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/* 0x100e5000 SP805 Watchdog module */
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/* 0x100e6000 BP147 TrustZone Protection Controller */
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/* 0x100e9000 PL301 'Fast' AXI matrix */
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/* 0x100ea000 PL301 'Slow' AXI matrix */
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/* 0x100ec000 TrustZone Address Space Controller */
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/* 0x10200000 CoreSight debug APB */
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/* 0x1e00a000 PL310 L2 Cache Controller */
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/* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */
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/* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */
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/* CS2: SRAM : 0x48000000 .. 0x4a000000 */
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sram_size = 0x2000000;
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sram_offset = qemu_ram_alloc(NULL, "vexpress.sram", sram_size);
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cpu_register_physical_memory(0x48000000, sram_size,
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sram_offset | IO_MEM_RAM);
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/* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
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/* 0x4c000000 Video RAM */
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vram_size = 0x800000;
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vram_offset = qemu_ram_alloc(NULL, "vexpress.vram", vram_size);
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cpu_register_physical_memory(0x4c000000, vram_size,
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vram_offset | IO_MEM_RAM);
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/* 0x4e000000 LAN9118 Ethernet */
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if (nd_table[0].vlan) {
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lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
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}
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/* 0x4f000000 ISP1761 USB */
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/* ??? Hack to map an additional page of ram for the secondary CPU
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startup code. I guess this works on real hardware because the
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BootROM happens to be in ROM/flash or in memory that isn't clobbered
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until after Linux boots the secondary CPUs. */
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ram_offset = qemu_ram_alloc(NULL, "vexpress.hack", 0x1000);
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cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
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ram_offset | IO_MEM_RAM);
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vexpress_binfo.ram_size = ram_size;
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vexpress_binfo.kernel_filename = kernel_filename;
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vexpress_binfo.kernel_cmdline = kernel_cmdline;
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vexpress_binfo.initrd_filename = initrd_filename;
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vexpress_binfo.nb_cpus = smp_cpus;
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vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
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vexpress_binfo.loader_start = 0x60000000;
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arm_load_kernel(first_cpu, &vexpress_binfo);
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}
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static QEMUMachine vexpress_a9_machine = {
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.name = "vexpress-a9",
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.desc = "ARM Versatile Express for Cortex-A9",
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.init = vexpress_a9_init,
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.use_scsi = 1,
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.max_cpus = 4,
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};
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static void vexpress_machine_init(void)
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{
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qemu_register_machine(&vexpress_a9_machine);
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}
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machine_init(vexpress_machine_init);
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