255 lines
7.9 KiB
C
255 lines
7.9 KiB
C
/*
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* QEMU PowerPC Booke hardware System Emulator
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*
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* Copyright (c) 2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "ppc.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "nvram.h"
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#include "qemu-log.h"
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#include "loader.h"
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/* Timer Control Register */
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#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
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#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT)
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#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
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#define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT)
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#define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */
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#define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */
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#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
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#define TCR_FP_MASK (0x3 << TCR_FP_SHIFT)
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#define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
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#define TCR_ARE (1 << 22) /* Auto-Reload Enable */
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/* Timer Control Register (e500 specific fields) */
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#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
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#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
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#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
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#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
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/* Timer Status Register */
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#define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */
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#define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */
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#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
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#define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT)
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#define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */
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#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */
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typedef struct booke_timer_t booke_timer_t;
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struct booke_timer_t {
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uint64_t fit_next;
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struct QEMUTimer *fit_timer;
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uint64_t wdt_next;
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struct QEMUTimer *wdt_timer;
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uint32_t flags;
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};
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static void booke_update_irq(CPUState *env)
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{
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ppc_set_irq(env, PPC_INTERRUPT_DECR,
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(env->spr[SPR_BOOKE_TSR] & TSR_DIS
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&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
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ppc_set_irq(env, PPC_INTERRUPT_WDT,
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(env->spr[SPR_BOOKE_TSR] & TSR_WIS
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&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
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ppc_set_irq(env, PPC_INTERRUPT_FIT,
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(env->spr[SPR_BOOKE_TSR] & TSR_FIS
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&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
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}
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/* Return the location of the bit of time base at which the FIT will raise an
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interrupt */
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static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
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{
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uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
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if (tb_env->flags & PPC_TIMER_E500) {
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/* e500 Fixed-interval timer period extension */
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uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
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>> TCR_E500_FPEXT_SHIFT;
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fp = 63 - (fp | fpext << 2);
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} else {
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fp = env->fit_period[fp];
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}
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return fp;
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}
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/* Return the location of the bit of time base at which the WDT will raise an
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interrupt */
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static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
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{
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uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
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if (tb_env->flags & PPC_TIMER_E500) {
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/* e500 Watchdog timer period extension */
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uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
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>> TCR_E500_WPEXT_SHIFT;
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wp = 63 - (wp | wpext << 2);
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} else {
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wp = env->wdt_period[wp];
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}
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return wp;
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}
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static void booke_update_fixed_timer(CPUState *env,
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uint8_t target_bit,
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uint64_t *next,
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struct QEMUTimer *timer)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t lapse;
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uint64_t tb;
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uint64_t period = 1 << (target_bit + 1);
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uint64_t now;
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now = qemu_get_clock_ns(vm_clock);
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tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
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lapse = period - ((tb - (1 << target_bit)) & (period - 1));
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*next = now + muldiv64(lapse, get_ticks_per_sec(), tb_env->tb_freq);
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/* XXX: If expire time is now. We can't run the callback because we don't
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* have access to it. So we just set the timer one nanosecond later.
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*/
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if (*next == now) {
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(*next)++;
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}
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qemu_mod_timer(timer, *next);
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}
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static void booke_decr_cb(void *opaque)
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{
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CPUState *env = opaque;
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env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
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booke_update_irq(env);
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if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
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/* Auto Reload */
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cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
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}
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}
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static void booke_fit_cb(void *opaque)
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{
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CPUState *env;
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ppc_tb_t *tb_env;
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booke_timer_t *booke_timer;
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env = opaque;
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tb_env = env->tb_env;
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booke_timer = tb_env->opaque;
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env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
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booke_update_irq(env);
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booke_update_fixed_timer(env,
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booke_get_fit_target(env, tb_env),
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&booke_timer->fit_next,
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booke_timer->fit_timer);
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}
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static void booke_wdt_cb(void *opaque)
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{
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CPUState *env;
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ppc_tb_t *tb_env;
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booke_timer_t *booke_timer;
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env = opaque;
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tb_env = env->tb_env;
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booke_timer = tb_env->opaque;
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/* TODO: There's lots of complicated stuff to do here */
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booke_update_irq(env);
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booke_update_fixed_timer(env,
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booke_get_wdt_target(env, tb_env),
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&booke_timer->wdt_next,
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booke_timer->wdt_timer);
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}
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void store_booke_tsr(CPUState *env, target_ulong val)
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{
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env->spr[SPR_BOOKE_TSR] &= ~val;
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booke_update_irq(env);
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}
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void store_booke_tcr(CPUState *env, target_ulong val)
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{
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ppc_tb_t *tb_env = env->tb_env;
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booke_timer_t *booke_timer = tb_env->opaque;
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tb_env = env->tb_env;
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env->spr[SPR_BOOKE_TCR] = val;
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booke_update_irq(env);
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booke_update_fixed_timer(env,
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booke_get_fit_target(env, tb_env),
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&booke_timer->fit_next,
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booke_timer->fit_timer);
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booke_update_fixed_timer(env,
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booke_get_wdt_target(env, tb_env),
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&booke_timer->wdt_next,
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booke_timer->wdt_timer);
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}
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void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags)
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{
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ppc_tb_t *tb_env;
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booke_timer_t *booke_timer;
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tb_env = g_malloc0(sizeof(ppc_tb_t));
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booke_timer = g_malloc0(sizeof(booke_timer_t));
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env->tb_env = tb_env;
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tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
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tb_env->tb_freq = freq;
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tb_env->decr_freq = freq;
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tb_env->opaque = booke_timer;
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tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, env);
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booke_timer->fit_timer =
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qemu_new_timer_ns(vm_clock, &booke_fit_cb, env);
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booke_timer->wdt_timer =
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qemu_new_timer_ns(vm_clock, &booke_wdt_cb, env);
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}
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