83 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * QEMU Emulated HPET support
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|  *
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|  * Copyright IBM, Corp. 2008
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|  *
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|  * Authors:
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|  *  Beth Kon   <bkon@us.ibm.com>
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|  *
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|  * This work is licensed under the terms of the GNU GPL, version 2.  See
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|  * the COPYING file in the top-level directory.
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|  *
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|  */
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| #ifndef QEMU_HPET_EMUL_H
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| #define QEMU_HPET_EMUL_H
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| 
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| #define HPET_BASE               0xfed00000
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| #define HPET_CLK_PERIOD         10000000ULL /* 10000000 femtoseconds == 10ns*/
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| 
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| #define FS_PER_NS 1000000
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| #define HPET_NUM_TIMERS 3
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| #define HPET_TIMER_TYPE_LEVEL 0x002
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| 
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| #define HPET_CFG_ENABLE 0x001
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| #define HPET_CFG_LEGACY 0x002
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| 
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| #define HPET_ID         0x000
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| #define HPET_PERIOD     0x004
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| #define HPET_CFG        0x010
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| #define HPET_STATUS     0x020
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| #define HPET_COUNTER    0x0f0
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| #define HPET_TN_CFG     0x000
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| #define HPET_TN_CMP     0x008
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| #define HPET_TN_ROUTE   0x010
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| #define HPET_CFG_WRITE_MASK  0x3
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| 
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| 
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| #define HPET_TN_ENABLE           0x004
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| #define HPET_TN_PERIODIC         0x008
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| #define HPET_TN_PERIODIC_CAP     0x010
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| #define HPET_TN_SIZE_CAP         0x020
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| #define HPET_TN_SETVAL           0x040
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| #define HPET_TN_32BIT            0x100
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| #define HPET_TN_INT_ROUTE_MASK  0x3e00
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| #define HPET_TN_CFG_WRITE_MASK  0x3f4e
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| #define HPET_TN_INT_ROUTE_SHIFT      9
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| #define HPET_TN_INT_ROUTE_CAP_SHIFT 32
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| #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
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| 
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| struct HPETState;
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| typedef struct HPETTimer {  /* timers */
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|     uint8_t tn;             /*timer number*/
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|     QEMUTimer *qemu_timer;
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|     struct HPETState *state;
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|     /* Memory-mapped, software visible timer registers */
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|     uint64_t config;        /* configuration/cap */
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|     uint64_t cmp;           /* comparator */
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|     uint64_t fsb;           /* FSB route, not supported now */
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|     /* Hidden register state */
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|     uint64_t period;        /* Last value written to comparator */
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|     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
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|                              * mode. Next pop will be actual timer expiration.
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|                              */
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| } HPETTimer;
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| 
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| typedef struct HPETState {
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|     uint64_t hpet_offset;
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|     qemu_irq *irqs;
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|     HPETTimer timer[HPET_NUM_TIMERS];
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| 
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|     /* Memory-mapped, software visible registers */
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|     uint64_t capability;        /* capabilities */
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|     uint64_t config;            /* configuration */
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|     uint64_t isr;               /* interrupt status reg */
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|     uint64_t hpet_counter;      /* main counter */
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| } HPETState;
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| 
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| #if defined TARGET_I386
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| extern uint32_t hpet_in_legacy_mode(void);
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| extern void hpet_init(qemu_irq *irq);
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| #endif
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| 
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| #endif
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