226 lines
6.3 KiB
C
226 lines
6.3 KiB
C
/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "sysemu/watchdog.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#define WDT_STATUS (0x00 / 4)
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#define WDT_RELOAD_VALUE (0x04 / 4)
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#define WDT_RESTART (0x08 / 4)
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#define WDT_CTRL (0x0C / 4)
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#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
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#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
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#define WDT_CTRL_1MHZ_CLK BIT(4)
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#define WDT_CTRL_WDT_EXT BIT(3)
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#define WDT_CTRL_WDT_INTR BIT(2)
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#define WDT_CTRL_RESET_SYSTEM BIT(1)
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#define WDT_CTRL_ENABLE BIT(0)
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#define WDT_TIMEOUT_STATUS (0x10 / 4)
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#define WDT_TIMEOUT_CLEAR (0x14 / 4)
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#define WDT_RESET_WDITH (0x18 / 4)
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#define WDT_RESTART_MAGIC 0x4755
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static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
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{
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return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
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}
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static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedWDTState *s = ASPEED_WDT(opaque);
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offset >>= 2;
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switch (offset) {
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case WDT_STATUS:
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return s->regs[WDT_STATUS];
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case WDT_RELOAD_VALUE:
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return s->regs[WDT_RELOAD_VALUE];
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case WDT_RESTART:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: read from write-only reg at offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);
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return 0;
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case WDT_CTRL:
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return s->regs[WDT_CTRL];
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case WDT_TIMEOUT_STATUS:
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case WDT_TIMEOUT_CLEAR:
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case WDT_RESET_WDITH:
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qemu_log_mask(LOG_UNIMP,
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"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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}
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static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
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{
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uint32_t reload;
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if (pclk) {
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reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
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s->pclk_freq);
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} else {
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reload = s->regs[WDT_RELOAD_VALUE] * 1000;
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}
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if (aspeed_wdt_is_enabled(s)) {
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timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
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}
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}
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static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedWDTState *s = ASPEED_WDT(opaque);
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bool enable = data & WDT_CTRL_ENABLE;
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offset >>= 2;
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switch (offset) {
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case WDT_STATUS:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to read-only reg at offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);
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break;
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case WDT_RELOAD_VALUE:
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s->regs[WDT_RELOAD_VALUE] = data;
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break;
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case WDT_RESTART:
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if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
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s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
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aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
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}
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break;
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case WDT_CTRL:
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if (enable && !aspeed_wdt_is_enabled(s)) {
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s->regs[WDT_CTRL] = data;
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aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
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} else if (!enable && aspeed_wdt_is_enabled(s)) {
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s->regs[WDT_CTRL] = data;
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timer_del(s->timer);
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}
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break;
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case WDT_TIMEOUT_STATUS:
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case WDT_TIMEOUT_CLEAR:
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case WDT_RESET_WDITH:
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qemu_log_mask(LOG_UNIMP,
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"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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return;
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}
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static WatchdogTimerModel model = {
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.wdt_name = TYPE_ASPEED_WDT,
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.wdt_description = "Aspeed watchdog device",
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};
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static const VMStateDescription vmstate_aspeed_wdt = {
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.name = "vmstate_aspeed_wdt",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER_PTR(timer, AspeedWDTState),
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VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static const MemoryRegionOps aspeed_wdt_ops = {
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.read = aspeed_wdt_read,
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.write = aspeed_wdt_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void aspeed_wdt_reset(DeviceState *dev)
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{
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AspeedWDTState *s = ASPEED_WDT(dev);
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s->regs[WDT_STATUS] = 0x3EF1480;
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s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
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s->regs[WDT_RESTART] = 0;
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s->regs[WDT_CTRL] = 0;
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timer_del(s->timer);
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}
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static void aspeed_wdt_timer_expired(void *dev)
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{
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AspeedWDTState *s = ASPEED_WDT(dev);
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qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
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watchdog_perform_action();
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timer_del(s->timer);
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}
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#define PCLK_HZ 24000000
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static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedWDTState *s = ASPEED_WDT(dev);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
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/* FIXME: This setting should be derived from the SCU hw strapping
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* register SCU70
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*/
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s->pclk_freq = PCLK_HZ;
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
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TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_wdt_realize;
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dc->reset = aspeed_wdt_reset;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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dc->vmsd = &vmstate_aspeed_wdt;
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}
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static const TypeInfo aspeed_wdt_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.name = TYPE_ASPEED_WDT,
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.instance_size = sizeof(AspeedWDTState),
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.class_init = aspeed_wdt_class_init,
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};
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static void wdt_aspeed_register_types(void)
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{
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watchdog_add_model(&model);
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type_register_static(&aspeed_wdt_info);
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}
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type_init(wdt_aspeed_register_types)
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