68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
#ifndef __QEMU_BARRIER_H
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#define __QEMU_BARRIER_H 1
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/* Compiler barrier */
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#define barrier() asm volatile("" ::: "memory")
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#if defined(__i386__)
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#include "compiler.h" /* QEMU_GNUC_PREREQ */
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/*
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* Because of the strongly ordered x86 storage model, wmb() and rmb() are nops
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* on x86(well, a compiler barrier only). Well, at least as long as
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* qemu doesn't do accesses to write-combining memory or non-temporal
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* load/stores from C code.
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*/
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#define smp_wmb() barrier()
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#define smp_rmb() barrier()
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/*
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* We use GCC builtin if it's available, as that can use
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* mfence on 32 bit as well, e.g. if built with -march=pentium-m.
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* However, on i386, there seem to be known bugs as recently as 4.3.
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* */
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#if QEMU_GNUC_PREREQ(4, 4)
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#define smp_mb() __sync_synchronize()
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#else
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#define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
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#endif
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#elif defined(__x86_64__)
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#define smp_wmb() barrier()
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#define smp_rmb() barrier()
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#define smp_mb() asm volatile("mfence" ::: "memory")
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#elif defined(_ARCH_PPC)
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/*
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* We use an eieio() for wmb() on powerpc. This assumes we don't
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* need to order cacheable and non-cacheable stores with respect to
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* each other
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*/
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#define smp_wmb() asm volatile("eieio" ::: "memory")
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#if defined(__powerpc64__)
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#define smp_rmb() asm volatile("lwsync" ::: "memory")
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#else
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#define smp_rmb() asm volatile("sync" ::: "memory")
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#endif
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#define smp_mb() asm volatile("sync" ::: "memory")
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#else
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/*
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* For (host) platforms we don't have explicit barrier definitions
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* for, we use the gcc __sync_synchronize() primitive to generate a
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* full barrier. This should be safe on all platforms, though it may
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* be overkill for wmb() and rmb().
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*/
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#define smp_wmb() __sync_synchronize()
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#define smp_mb() __sync_synchronize()
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#define smp_rmb() __sync_synchronize()
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#endif
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#endif
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