366 lines
12 KiB
C
366 lines
12 KiB
C
/*
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* QEMU Sun4u System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "pc.h"
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#include "nvram.h"
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#include "fdc.h"
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#include "net.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "firmware_abi.h"
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define INITRD_LOAD_ADDR 0x00300000
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#define PROM_SIZE_MAX (512 * 1024)
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#define PROM_ADDR 0x1fff0000000ULL
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#define PROM_VADDR 0x000ffd00000ULL
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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#define APB_MEM_BASE 0x1ff00000000ULL
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#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
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#define PROM_FILENAME "openbios-sparc64"
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#define NVRAM_SIZE 0x2000
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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return qemu_get_clock(vm_clock);
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}
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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}
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extern int nographic;
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static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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const unsigned char *arch,
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uint32_t RAM_size, const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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unsigned int i;
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uint32_t start, end;
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image));
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// Try to match PPC NVRAM
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strcpy(header->struct_ident, "QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */
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header->nvram_size = cpu_to_be16(NVRAM_size);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
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strcpy(header->arch, arch);
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
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strcpy(header->boot_devices, boot_devices);
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
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if (cmdline) {
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strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
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}
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header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
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header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
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header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
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header->width = cpu_to_be16(width);
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header->height = cpu_to_be16(height);
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header->depth = cpu_to_be16(depth);
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg);
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM;
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strcpy(part_header->name, "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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for (i = 0; i < nb_prom_envs; i++)
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end = OpenBIOS_set_var(image, end, prom_envs[i]);
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15);
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OpenBIOS_finish_partition(part_header, end - start);
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// free partition
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start = end;
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE;
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strcpy(part_header->name, "free");
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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return 0;
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}
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void pic_info()
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{
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}
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void irq_info()
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{
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}
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void qemu_system_powerdown(void)
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{
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->tick, 0);
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ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->stick, 0);
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ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->hstick, 0);
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}
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void tick_irq(void *opaque)
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{
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CPUState *env = opaque;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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void stick_irq(void *opaque)
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{
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CPUState *env = opaque;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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void hstick_irq(void *opaque)
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{
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CPUState *env = opaque;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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static void dummy_cpu_set_irq(void *opaque, int irq, int level)
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{
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}
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
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static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
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static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
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static fdctrl_t *floppy_controller;
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/* Sun4u hardware initialisation */
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static void sun4u_init(int ram_size, int vga_ram_size,
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const char *boot_devices, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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char buf[1024];
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m48t59_t *nvram;
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int ret, linux_boot;
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unsigned int i;
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long prom_offset, initrd_size, kernel_size;
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PCIBus *pci_bus;
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QEMUBH *bh;
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qemu_irq *irq;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (cpu_model == NULL)
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cpu_model = "TI UltraSparc II";
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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bh = qemu_bh_new(tick_irq, env);
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env->tick = ptimer_init(bh);
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ptimer_set_period(env->tick, 1ULL);
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bh = qemu_bh_new(stick_irq, env);
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env->stick = ptimer_init(bh);
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ptimer_set_period(env->stick, 1ULL);
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bh = qemu_bh_new(hstick_irq, env);
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env->hstick = ptimer_init(bh);
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ptimer_set_period(env->hstick, 1ULL);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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main_cpu_reset(env);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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prom_offset = ram_size + vga_ram_size;
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cpu_register_physical_memory(PROM_ADDR,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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kernel_size = 0;
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initrd_size = 0;
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if (linux_boot) {
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/* XXX: put correct offset */
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kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (kernel_size < 0)
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kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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== 0x48647253) { // HdrS
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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}
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}
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}
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}
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pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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isa_mem_base = VGA_BASE;
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pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
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}
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}
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for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
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if (parallel_hds[i]) {
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parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
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}
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}
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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nd_table[i].model = "ne2k_pci";
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pci_nic_init(pci_bus, &nd_table[i], -1);
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}
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irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
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// XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
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pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
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/* FIXME: wire up interrupts. */
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i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
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floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
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nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
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sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
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KERNEL_LOAD_ADDR, kernel_size,
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kernel_cmdline,
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INITRD_LOAD_ADDR, initrd_size,
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/* XXX: need an option to load a NVRAM image */
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0,
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graphic_width, graphic_height, graphic_depth);
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}
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QEMUMachine sun4u_machine = {
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"sun4u",
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"Sun4u platform",
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sun4u_init,
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};
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