qemu-irix/hw/arm
Andrew Jeffery 87e79af074 palmetto-bmc: Configure the SCU's hardware strapping register
The magic constant configures the following options:

* 28:27: Configure DRAM size as 256MB
* 26:24: DDR3 SDRAM with CL = 6, CWL = 5
* 23: Configure 24/48MHz CLKIN
* 22: Disable GPIOE pass-through mode
* 21: Disable GPIOD pass-through mode
* 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses
* 19: Disable ACPI
* 18: Configure 48MHz CLKIN
* 17: Disable BMC 2nd boot watchdog timer
* 16: Decode SuperIO address 0x2E
* 15: VGA Class Code
* 14: Enable LPC dedicated reset pin
* 13:12: Enable SPI Master and SPI Slave to AHB Bridge
* 11:10: Select CPU:AHB ratio = 2:1
* 9:8: Select 384MHz H-PLL
* 7: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1466744305-23163-4-git-send-email-andrew@aj.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-27 15:37:33 +01:00
..
Makefile.objs
allwinner-a10.c
armv7m.c
ast2400.c
bcm2835_peripherals.c
bcm2836.c
boot.c
collie.c
cubieboard.c
digic.c
digic_boards.c
exynos4_boards.c
exynos4210.c
fsl-imx6.c
fsl-imx25.c
fsl-imx31.c
gumstix.c
highbank.c
imx25_pdk.c
integratorcp.c
kzm.c
mainstone.c
musicpal.c
netduino2.c
nseries.c
omap1.c
omap2.c
omap_sx1.c
palm.c
palmetto-bmc.c palmetto-bmc: Configure the SCU's hardware strapping register 2016-06-27 15:37:33 +01:00
pxa2xx.c
pxa2xx_gpio.c
pxa2xx_pic.c
raspi.c
realview.c
sabrelite.c
spitz.c
stellaris.c
stm32f205_soc.c
strongarm.c
strongarm.h
sysbus-fdt.c
tosa.c
trace-events
versatilepb.c
vexpress.c
virt-acpi-build.c
virt.c
xilinx_zynq.c
xlnx-ep108.c
xlnx-zynqmp.c
z2.c