552 lines
14 KiB
C
552 lines
14 KiB
C
/*
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* QEMU model of the Milkymist minimac2 block.
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*
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* Copyright (c) 2011 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* not available yet
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*
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*/
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "trace.h"
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#include "net/net.h"
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#include "qemu/error-report.h"
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#include <zlib.h>
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enum {
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R_SETUP = 0,
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R_MDIO,
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R_STATE0,
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R_COUNT0,
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R_STATE1,
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R_COUNT1,
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R_TXCOUNT,
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R_MAX
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};
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enum {
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SETUP_PHY_RST = (1<<0),
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};
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enum {
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MDIO_DO = (1<<0),
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MDIO_DI = (1<<1),
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MDIO_OE = (1<<2),
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MDIO_CLK = (1<<3),
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};
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enum {
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STATE_EMPTY = 0,
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STATE_LOADED = 1,
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STATE_PENDING = 2,
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};
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enum {
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MDIO_OP_WRITE = 1,
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MDIO_OP_READ = 2,
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};
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enum mdio_state {
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MDIO_STATE_IDLE,
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MDIO_STATE_READING,
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MDIO_STATE_WRITING,
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};
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enum {
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R_PHY_ID1 = 2,
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R_PHY_ID2 = 3,
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R_PHY_MAX = 32
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};
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#define MINIMAC2_MTU 1530
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#define MINIMAC2_BUFFER_SIZE 2048
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struct MilkymistMinimac2MdioState {
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int last_clk;
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int count;
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uint32_t data;
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uint16_t data_out;
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int state;
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uint8_t phy_addr;
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uint8_t reg_addr;
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};
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typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
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#define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
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#define MILKYMIST_MINIMAC2(obj) \
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OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
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struct MilkymistMinimac2State {
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SysBusDevice parent_obj;
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NICState *nic;
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NICConf conf;
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char *phy_model;
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MemoryRegion buffers;
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MemoryRegion regs_region;
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qemu_irq rx_irq;
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qemu_irq tx_irq;
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uint32_t regs[R_MAX];
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MilkymistMinimac2MdioState mdio;
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uint16_t phy_regs[R_PHY_MAX];
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uint8_t *rx0_buf;
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uint8_t *rx1_buf;
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uint8_t *tx_buf;
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};
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typedef struct MilkymistMinimac2State MilkymistMinimac2State;
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static const uint8_t preamble_sfd[] = {
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0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
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};
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static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
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uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
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{
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trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
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/* nop */
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}
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static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
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uint8_t phy_addr, uint8_t reg_addr)
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{
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uint16_t r = s->phy_regs[reg_addr];
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trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
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return r;
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}
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static void minimac2_update_mdio(MilkymistMinimac2State *s)
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{
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MilkymistMinimac2MdioState *m = &s->mdio;
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/* detect rising clk edge */
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if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
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/* shift data in */
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int bit = ((s->regs[R_MDIO] & MDIO_DO)
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&& (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
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m->data = (m->data << 1) | bit;
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/* check for sync */
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if (m->data == 0xffffffff) {
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m->count = 32;
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}
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if (m->count == 16) {
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uint8_t start = (m->data >> 14) & 0x3;
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uint8_t op = (m->data >> 12) & 0x3;
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uint8_t ta = (m->data) & 0x3;
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if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
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m->state = MDIO_STATE_WRITING;
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} else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
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m->state = MDIO_STATE_READING;
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} else {
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m->state = MDIO_STATE_IDLE;
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}
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if (m->state != MDIO_STATE_IDLE) {
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m->phy_addr = (m->data >> 7) & 0x1f;
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m->reg_addr = (m->data >> 2) & 0x1f;
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}
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if (m->state == MDIO_STATE_READING) {
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m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
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m->reg_addr);
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}
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}
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if (m->count < 16 && m->state == MDIO_STATE_READING) {
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int bit = (m->data_out & 0x8000) ? 1 : 0;
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m->data_out <<= 1;
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if (bit) {
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s->regs[R_MDIO] |= MDIO_DI;
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} else {
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s->regs[R_MDIO] &= ~MDIO_DI;
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}
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}
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if (m->count == 0 && m->state) {
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if (m->state == MDIO_STATE_WRITING) {
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uint16_t data = m->data & 0xffff;
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minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
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}
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m->state = MDIO_STATE_IDLE;
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}
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m->count--;
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}
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m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
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}
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static size_t assemble_frame(uint8_t *buf, size_t size,
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const uint8_t *payload, size_t payload_size)
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{
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uint32_t crc;
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if (size < payload_size + 12) {
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error_report("milkymist_minimac2: received too big ethernet frame");
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return 0;
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}
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/* prepend preamble and sfd */
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memcpy(buf, preamble_sfd, 8);
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/* now copy the payload */
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memcpy(buf + 8, payload, payload_size);
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/* pad frame if needed */
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if (payload_size < 60) {
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memset(buf + payload_size + 8, 0, 60 - payload_size);
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payload_size = 60;
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}
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/* append fcs */
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crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
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memcpy(buf + payload_size + 8, &crc, 4);
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return payload_size + 12;
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}
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static void minimac2_tx(MilkymistMinimac2State *s)
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{
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uint32_t txcount = s->regs[R_TXCOUNT];
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uint8_t *buf = s->tx_buf;
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if (txcount < 64) {
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error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
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txcount, 64);
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goto err;
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}
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if (txcount > MINIMAC2_MTU) {
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error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
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txcount, MINIMAC2_MTU);
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goto err;
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}
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if (memcmp(buf, preamble_sfd, 8) != 0) {
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error_report("milkymist_minimac2: frame doesn't contain the preamble "
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"and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
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goto err;
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}
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trace_milkymist_minimac2_tx_frame(txcount - 12);
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/* send packet, skipping preamble and sfd */
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qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
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s->regs[R_TXCOUNT] = 0;
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err:
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trace_milkymist_minimac2_pulse_irq_tx();
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qemu_irq_pulse(s->tx_irq);
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}
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static void update_rx_interrupt(MilkymistMinimac2State *s)
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{
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if (s->regs[R_STATE0] == STATE_PENDING
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|| s->regs[R_STATE1] == STATE_PENDING) {
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trace_milkymist_minimac2_raise_irq_rx();
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qemu_irq_raise(s->rx_irq);
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} else {
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trace_milkymist_minimac2_lower_irq_rx();
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qemu_irq_lower(s->rx_irq);
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}
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}
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static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
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uint32_t r_count;
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uint32_t r_state;
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uint8_t *rx_buf;
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size_t frame_size;
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trace_milkymist_minimac2_rx_frame(buf, size);
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/* choose appropriate slot */
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if (s->regs[R_STATE0] == STATE_LOADED) {
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r_count = R_COUNT0;
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r_state = R_STATE0;
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rx_buf = s->rx0_buf;
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} else if (s->regs[R_STATE1] == STATE_LOADED) {
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r_count = R_COUNT1;
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r_state = R_STATE1;
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rx_buf = s->rx1_buf;
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} else {
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trace_milkymist_minimac2_drop_rx_frame(buf);
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return size;
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}
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/* assemble frame */
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frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
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if (frame_size == 0) {
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return size;
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}
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trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
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/* update slot */
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s->regs[r_count] = frame_size;
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s->regs[r_state] = STATE_PENDING;
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update_rx_interrupt(s);
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return size;
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}
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static uint64_t
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minimac2_read(void *opaque, hwaddr addr, unsigned size)
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{
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MilkymistMinimac2State *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_SETUP:
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case R_MDIO:
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case R_STATE0:
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case R_COUNT0:
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case R_STATE1:
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case R_COUNT1:
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case R_TXCOUNT:
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_minimac2: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_minimac2_memory_read(addr << 2, r);
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return r;
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}
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static void
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minimac2_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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MilkymistMinimac2State *s = opaque;
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trace_milkymist_minimac2_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_MDIO:
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{
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/* MDIO_DI is read only */
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int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
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s->regs[R_MDIO] = value;
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if (mdio_di) {
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s->regs[R_MDIO] |= mdio_di;
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} else {
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s->regs[R_MDIO] &= ~mdio_di;
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}
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minimac2_update_mdio(s);
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} break;
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case R_TXCOUNT:
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s->regs[addr] = value;
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if (value > 0) {
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minimac2_tx(s);
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}
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break;
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case R_STATE0:
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case R_STATE1:
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s->regs[addr] = value;
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update_rx_interrupt(s);
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break;
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case R_SETUP:
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case R_COUNT0:
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case R_COUNT1:
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s->regs[addr] = value;
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break;
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default:
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error_report("milkymist_minimac2: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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}
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static const MemoryRegionOps minimac2_ops = {
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.read = minimac2_read,
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.write = minimac2_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int minimac2_can_rx(NetClientState *nc)
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{
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MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
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if (s->regs[R_STATE0] == STATE_LOADED) {
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return 1;
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}
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if (s->regs[R_STATE1] == STATE_LOADED) {
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return 1;
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}
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return 0;
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}
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static void minimac2_cleanup(NetClientState *nc)
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{
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MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
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s->nic = NULL;
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}
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static void milkymist_minimac2_reset(DeviceState *d)
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{
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MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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for (i = 0; i < R_PHY_MAX; i++) {
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s->phy_regs[i] = 0;
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}
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/* defaults */
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s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
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s->phy_regs[R_PHY_ID2] = 0x161a;
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}
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static NetClientInfo net_milkymist_minimac2_info = {
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.type = NET_CLIENT_OPTIONS_KIND_NIC,
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.size = sizeof(NICState),
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.can_receive = minimac2_can_rx,
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.receive = minimac2_rx,
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.cleanup = minimac2_cleanup,
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};
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static int milkymist_minimac2_init(SysBusDevice *sbd)
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{
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DeviceState *dev = DEVICE(sbd);
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MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
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size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
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sysbus_init_irq(sbd, &s->rx_irq);
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sysbus_init_irq(sbd, &s->tx_irq);
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memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
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"milkymist-minimac2", R_MAX * 4);
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sysbus_init_mmio(sbd, &s->regs_region);
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/* register buffers memory */
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memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
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buffers_size);
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vmstate_register_ram_global(&s->buffers);
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s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
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s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
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s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
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sysbus_init_mmio(sbd, &s->buffers);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
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object_get_typename(OBJECT(dev)), dev->id, s);
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qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
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return 0;
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}
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static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
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.name = "milkymist-minimac2-mdio",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
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VMSTATE_INT32(count, MilkymistMinimac2MdioState),
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VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
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VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
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VMSTATE_INT32(state, MilkymistMinimac2MdioState),
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VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
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VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_milkymist_minimac2 = {
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.name = "milkymist-minimac2",
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.version_id = 1,
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.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
|
|
VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
|
|
VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
|
|
vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property milkymist_minimac2_properties[] = {
|
|
DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
|
|
DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = milkymist_minimac2_init;
|
|
dc->reset = milkymist_minimac2_reset;
|
|
dc->vmsd = &vmstate_milkymist_minimac2;
|
|
dc->props = milkymist_minimac2_properties;
|
|
}
|
|
|
|
static const TypeInfo milkymist_minimac2_info = {
|
|
.name = TYPE_MILKYMIST_MINIMAC2,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MilkymistMinimac2State),
|
|
.class_init = milkymist_minimac2_class_init,
|
|
};
|
|
|
|
static void milkymist_minimac2_register_types(void)
|
|
{
|
|
type_register_static(&milkymist_minimac2_info);
|
|
}
|
|
|
|
type_init(milkymist_minimac2_register_types)
|