461 lines
12 KiB
C
461 lines
12 KiB
C
/*
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* SH7750 device
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <assert.h>
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#include "vl.h"
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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#define NB_DEVICES 4
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typedef struct SH7750State {
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/* CPU */
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CPUSH4State *cpu;
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/* Peripheral frequency in Hz */
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uint32_t periph_freq;
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/* SDRAM controller */
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uint16_t rfcr;
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/* IO ports */
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uint16_t gpioic;
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uint32_t pctra;
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uint32_t pctrb;
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uint16_t portdira; /* Cached */
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uint16_t portpullupa; /* Cached */
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uint16_t portdirb; /* Cached */
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uint16_t portpullupb; /* Cached */
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uint16_t pdtra;
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uint16_t pdtrb;
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uint16_t periph_pdtra; /* Imposed by the peripherals */
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uint16_t periph_portdira; /* Direction seen from the peripherals */
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uint16_t periph_pdtrb; /* Imposed by the peripherals */
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uint16_t periph_portdirb; /* Direction seen from the peripherals */
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sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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uint16_t icr;
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uint16_t ipra;
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uint16_t iprb;
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uint16_t iprc;
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uint16_t iprd;
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uint32_t intpri00;
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uint32_t intmsk00;
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/* Cache */
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uint32_t ccr;
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} SH7750State;
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/**********************************************************************
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I/O ports
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**********************************************************************/
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int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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{
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int i;
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for (i = 0; i < NB_DEVICES; i++) {
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if (s->devices[i] == NULL) {
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s->devices[i] = device;
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return 0;
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}
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}
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return -1;
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}
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static uint16_t portdir(uint32_t v)
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{
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#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
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return
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EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
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EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
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EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
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EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
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EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
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EVENPORTMASK(0);
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}
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static uint16_t portpullup(uint32_t v)
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{
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#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
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return
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ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
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ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
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ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
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ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
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ODDPORTMASK(1) | ODDPORTMASK(0);
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}
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static uint16_t porta_lines(SH7750State * s)
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{
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return (s->portdira & s->pdtra) | /* CPU */
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(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
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}
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static uint16_t portb_lines(SH7750State * s)
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{
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return (s->portdirb & s->pdtrb) | /* CPU */
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(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
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(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
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}
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static void gen_port_interrupts(SH7750State * s)
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{
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/* XXXXX interrupts not generated */
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}
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static void porta_changed(SH7750State * s, uint16_t prev)
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{
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uint16_t currenta, changes;
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int i, r = 0;
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#if 0
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fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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prev, porta_lines(s));
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fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
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#endif
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currenta = porta_lines(s);
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if (currenta == prev)
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return;
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changes = currenta ^ prev;
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for (i = 0; i < NB_DEVICES; i++) {
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if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
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r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
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&s->periph_pdtra,
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&s->periph_portdira,
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&s->periph_pdtrb,
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&s->periph_portdirb);
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}
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}
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if (r)
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gen_port_interrupts(s);
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}
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static void portb_changed(SH7750State * s, uint16_t prev)
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{
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uint16_t currentb, changes;
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int i, r = 0;
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currentb = portb_lines(s);
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if (currentb == prev)
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return;
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changes = currentb ^ prev;
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for (i = 0; i < NB_DEVICES; i++) {
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if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
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r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
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&s->periph_pdtra,
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&s->periph_portdira,
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&s->periph_pdtrb,
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&s->periph_portdirb);
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}
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}
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if (r)
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gen_port_interrupts(s);
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}
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/**********************************************************************
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Memory
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**********************************************************************/
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static void error_access(const char *kind, target_phys_addr_t addr)
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{
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fprintf(stderr, "%s to %s (0x%08x) not supported\n",
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kind, regname(addr), addr);
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}
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static void ignore_access(const char *kind, target_phys_addr_t addr)
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{
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fprintf(stderr, "%s to %s (0x%08x) ignored\n",
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kind, regname(addr), addr);
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}
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static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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switch (addr) {
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default:
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error_access("byte read", addr);
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assert(0);
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}
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}
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static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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SH7750State *s = opaque;
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switch (addr) {
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case SH7750_FRQCR_A7:
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return 0;
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case SH7750_RFCR_A7:
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fprintf(stderr,
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"Read access to refresh count register, incrementing\n");
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return s->rfcr++;
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case SH7750_PDTRA_A7:
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return porta_lines(s);
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case SH7750_PDTRB_A7:
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return portb_lines(s);
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case 0x1fd00000:
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return s->icr;
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case 0x1fd00004:
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return s->ipra;
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case 0x1fd00008:
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return s->iprb;
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case 0x1fd0000c:
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return s->iprc;
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case 0x1fd00010:
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return s->iprd;
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default:
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error_access("word read", addr);
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assert(0);
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}
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}
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static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SH7750State *s = opaque;
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switch (addr) {
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case SH7750_MMUCR_A7:
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return s->cpu->mmucr;
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case SH7750_PTEH_A7:
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return s->cpu->pteh;
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case SH7750_PTEL_A7:
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return s->cpu->ptel;
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case SH7750_TTB_A7:
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return s->cpu->ttb;
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case SH7750_TEA_A7:
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return s->cpu->tea;
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case SH7750_TRA_A7:
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return s->cpu->tra;
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case SH7750_EXPEVT_A7:
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return s->cpu->expevt;
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case SH7750_INTEVT_A7:
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return s->cpu->intevt;
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case SH7750_CCR_A7:
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return s->ccr;
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case 0x1f000030: /* Processor version PVR */
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return 0x00050000; /* SH7750R */
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case 0x1f000040: /* Processor version CVR */
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return 0x00110000; /* Minimum caches */
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case 0x1f000044: /* Processor version PRR */
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return 0x00000100; /* SH7750R */
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case 0x1e080000:
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return s->intpri00;
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case 0x1e080020:
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return 0;
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case 0x1e080040:
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return s->intmsk00;
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case 0x1e080060:
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return 0;
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default:
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error_access("long read", addr);
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assert(0);
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}
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}
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static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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switch (addr) {
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/* PRECHARGE ? XXXXX */
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case SH7750_PRECHARGE0_A7:
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case SH7750_PRECHARGE1_A7:
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ignore_access("byte write", addr);
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return;
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default:
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error_access("byte write", addr);
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assert(0);
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}
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}
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static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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SH7750State *s = opaque;
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uint16_t temp;
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switch (addr) {
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/* SDRAM controller */
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case SH7750_BCR2_A7:
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case SH7750_BCR3_A7:
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case SH7750_RTCOR_A7:
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case SH7750_RTCNT_A7:
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case SH7750_RTCSR_A7:
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ignore_access("word write", addr);
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return;
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/* IO ports */
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case SH7750_PDTRA_A7:
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temp = porta_lines(s);
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s->pdtra = mem_value;
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porta_changed(s, temp);
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return;
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case SH7750_PDTRB_A7:
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temp = portb_lines(s);
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s->pdtrb = mem_value;
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portb_changed(s, temp);
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return;
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case SH7750_RFCR_A7:
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fprintf(stderr, "Write access to refresh count register\n");
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s->rfcr = mem_value;
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return;
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case SH7750_GPIOIC_A7:
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s->gpioic = mem_value;
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if (mem_value != 0) {
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fprintf(stderr, "I/O interrupts not implemented\n");
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assert(0);
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}
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return;
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case 0x1fd00000:
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s->icr = mem_value;
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return;
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case 0x1fd00004:
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s->ipra = mem_value;
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return;
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case 0x1fd00008:
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s->iprb = mem_value;
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return;
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case 0x1fd0000c:
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s->iprc = mem_value;
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return;
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case 0x1fd00010:
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s->iprd = mem_value;
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return;
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default:
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error_access("word write", addr);
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assert(0);
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}
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}
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static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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SH7750State *s = opaque;
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uint16_t temp;
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switch (addr) {
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/* SDRAM controller */
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case SH7750_BCR1_A7:
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case SH7750_BCR4_A7:
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case SH7750_WCR1_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR3_A7:
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case SH7750_MCR_A7:
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ignore_access("long write", addr);
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return;
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/* IO ports */
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case SH7750_PCTRA_A7:
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temp = porta_lines(s);
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s->pctra = mem_value;
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s->portdira = portdir(mem_value);
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s->portpullupa = portpullup(mem_value);
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porta_changed(s, temp);
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return;
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case SH7750_PCTRB_A7:
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temp = portb_lines(s);
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s->pctrb = mem_value;
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s->portdirb = portdir(mem_value);
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s->portpullupb = portpullup(mem_value);
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portb_changed(s, temp);
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return;
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case SH7750_MMUCR_A7:
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s->cpu->mmucr = mem_value;
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return;
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case SH7750_PTEH_A7:
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s->cpu->pteh = mem_value;
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return;
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case SH7750_PTEL_A7:
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s->cpu->ptel = mem_value;
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return;
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case SH7750_TTB_A7:
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s->cpu->ttb = mem_value;
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return;
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case SH7750_TEA_A7:
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s->cpu->tea = mem_value;
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return;
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case SH7750_TRA_A7:
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s->cpu->tra = mem_value & 0x000007ff;
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return;
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case SH7750_EXPEVT_A7:
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s->cpu->expevt = mem_value & 0x000007ff;
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return;
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case SH7750_INTEVT_A7:
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s->cpu->intevt = mem_value & 0x000007ff;
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return;
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case SH7750_CCR_A7:
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s->ccr = mem_value;
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return;
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case 0x1e080000:
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s->intpri00 = mem_value;
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return;
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case 0x1e080020:
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return;
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case 0x1e080040:
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s->intmsk00 = mem_value;
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return;
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case 0x1e080060:
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return;
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default:
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error_access("long write", addr);
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assert(0);
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}
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}
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static CPUReadMemoryFunc *sh7750_mem_read[] = {
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sh7750_mem_readb,
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sh7750_mem_readw,
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sh7750_mem_readl
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};
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static CPUWriteMemoryFunc *sh7750_mem_write[] = {
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sh7750_mem_writeb,
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sh7750_mem_writew,
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sh7750_mem_writel
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};
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SH7750State *sh7750_init(CPUSH4State * cpu)
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{
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SH7750State *s;
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int sh7750_io_memory;
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s = qemu_mallocz(sizeof(SH7750State));
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s->cpu = cpu;
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s->periph_freq = 60000000; /* 60MHz */
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sh7750_io_memory = cpu_register_io_memory(0,
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sh7750_mem_read,
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sh7750_mem_write, s);
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cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
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sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]);
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sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hds[1]);
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tmu012_init(0x1fd80000,
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TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
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s->periph_freq);
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tmu012_init(0x1e100000, 0, s->periph_freq);
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return s;
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}
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