140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/*
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* AArch64 translation
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "tcg-op.h"
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#include "qemu/log.h"
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#include "translate.h"
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#include "qemu/host-utils.h"
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#include "helper.h"
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#define GEN_HELPER 1
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#include "helper.h"
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static TCGv_i64 cpu_X[32];
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static TCGv_i64 cpu_pc;
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static TCGv_i32 pstate;
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static const char *regnames[] = {
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
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};
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/* initialize TCG globals. */
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void a64_translate_init(void)
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{
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int i;
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cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, pc),
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"pc");
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for (i = 0; i < 32; i++) {
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cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUARMState, xregs[i]),
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regnames[i]);
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}
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pstate = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUARMState, pstate),
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"pstate");
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}
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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int i;
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cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
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env->pc, env->xregs[31]);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
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if ((i % 4) == 3) {
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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}
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}
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cpu_fprintf(f, "PSTATE=%c%c%c%c\n",
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env->pstate & PSTATE_N ? 'n' : '.',
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env->pstate & PSTATE_Z ? 'z' : '.',
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env->pstate & PSTATE_C ? 'c' : '.',
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env->pstate & PSTATE_V ? 'v' : '.');
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cpu_fprintf(f, "\n");
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}
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void gen_a64_set_pc_im(uint64_t val)
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{
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tcg_gen_movi_i64(cpu_pc, val);
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}
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static void gen_exception(int excp)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, excp);
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gen_helper_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void gen_exception_insn(DisasContext *s, int offset, int excp)
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{
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gen_a64_set_pc_im(s->pc - offset);
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gen_exception(excp);
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s->is_jmp = DISAS_JUMP;
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}
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static void real_unallocated_encoding(DisasContext *s)
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{
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fprintf(stderr, "Unknown instruction: %#x\n", s->insn);
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gen_exception_insn(s, 4, EXCP_UDEF);
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}
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#define unallocated_encoding(s) do { \
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fprintf(stderr, "unallocated encoding at line: %d\n", __LINE__); \
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real_unallocated_encoding(s); \
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} while (0)
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void disas_a64_insn(CPUARMState *env, DisasContext *s)
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{
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uint32_t insn;
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insn = arm_ldl_code(env, s->pc, s->bswap_code);
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s->insn = insn;
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s->pc += 4;
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switch ((insn >> 24) & 0x1f) {
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default:
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unallocated_encoding(s);
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break;
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}
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if (unlikely(s->singlestep_enabled) && (s->is_jmp == DISAS_TB_JUMP)) {
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/* go through the main loop for single step */
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s->is_jmp = DISAS_JUMP;
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}
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}
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