203 lines
6.6 KiB
C
203 lines
6.6 KiB
C
/*
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* Simple interface for atomic operations.
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*
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* Copyright (C) 2013 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef __QEMU_ATOMIC_H
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#define __QEMU_ATOMIC_H 1
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#include "qemu/compiler.h"
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/* For C11 atomic ops */
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/* Compiler barrier */
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#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
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#ifndef __ATOMIC_RELAXED
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/*
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* We use GCC builtin if it's available, as that can use mfence on
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* 32-bit as well, e.g. if built with -march=pentium-m. However, on
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* i386 the spec is buggy, and the implementation followed it until
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* 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#if !QEMU_GNUC_PREREQ(4, 4)
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#if defined __x86_64__
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#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
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#else
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#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
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#endif
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#endif
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#endif
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#ifdef __alpha__
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#endif
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)
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/*
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* Because of the strongly ordered storage model, wmb() and rmb() are nops
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* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
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* qemu memory or non-temporal load/stores from C code.
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*/
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#define smp_wmb() barrier()
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#define smp_rmb() barrier()
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/*
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* __sync_lock_test_and_set() is documented to be an acquire barrier only,
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* but it is a full barrier at the hardware level. Add a compiler barrier
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* to make it a full barrier also at the compiler level.
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*/
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#define atomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i))
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/*
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* Load/store with Java volatile semantics.
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*/
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#define atomic_mb_set(ptr, i) ((void)atomic_xchg(ptr, i))
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#elif defined(_ARCH_PPC)
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/*
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* We use an eieio() for wmb() on powerpc. This assumes we don't
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* need to order cacheable and non-cacheable stores with respect to
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* each other.
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*
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* smp_mb has the same problem as on x86 for not-very-new GCC
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* (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
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*/
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#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
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#if defined(__powerpc64__)
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#define smp_rmb() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
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#else
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#define smp_rmb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif
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#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif /* _ARCH_PPC */
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#endif /* C11 atomics */
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/*
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* For (host) platforms we don't have explicit barrier definitions
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* for, we use the gcc __sync_synchronize() primitive to generate a
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* full barrier. This should be safe on all platforms, though it may
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* be overkill for smp_wmb() and smp_rmb().
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*/
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#ifndef smp_mb
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#define smp_mb() __sync_synchronize()
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#endif
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#ifndef smp_wmb
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#ifdef __ATOMIC_RELEASE
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#define smp_wmb() __atomic_thread_fence(__ATOMIC_RELEASE)
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#else
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#define smp_wmb() __sync_synchronize()
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#endif
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#endif
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#ifndef smp_rmb
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#ifdef __ATOMIC_ACQUIRE
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#define smp_rmb() __atomic_thread_fence(__ATOMIC_ACQUIRE)
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#else
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#define smp_rmb() __sync_synchronize()
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#endif
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#endif
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#ifndef smp_read_barrier_depends
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#ifdef __ATOMIC_CONSUME
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#define smp_read_barrier_depends() __atomic_thread_fence(__ATOMIC_CONSUME)
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#else
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#define smp_read_barrier_depends() barrier()
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#endif
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#endif
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#ifndef atomic_read
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#define atomic_read(ptr) (*(__typeof__(*ptr) volatile*) (ptr))
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#endif
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#ifndef atomic_set
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#define atomic_set(ptr, i) ((*(__typeof__(*ptr) volatile*) (ptr)) = (i))
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#endif
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/* These have the same semantics as Java volatile variables.
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* See http://gee.cs.oswego.edu/dl/jmm/cookbook.html:
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* "1. Issue a StoreStore barrier (wmb) before each volatile store."
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* 2. Issue a StoreLoad barrier after each volatile store.
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* Note that you could instead issue one before each volatile load, but
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* this would be slower for typical programs using volatiles in which
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* reads greatly outnumber writes. Alternatively, if available, you
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* can implement volatile store as an atomic instruction (for example
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* XCHG on x86) and omit the barrier. This may be more efficient if
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* atomic instructions are cheaper than StoreLoad barriers.
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* 3. Issue LoadLoad and LoadStore barriers after each volatile load."
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*
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* If you prefer to think in terms of "pairing" of memory barriers,
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* an atomic_mb_read pairs with an atomic_mb_set.
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*
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* And for the few ia64 lovers that exist, an atomic_mb_read is a ld.acq,
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* while an atomic_mb_set is a st.rel followed by a memory barrier.
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*
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* These are a bit weaker than __atomic_load/store with __ATOMIC_SEQ_CST
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* (see docs/atomics.txt), and I'm not sure that __ATOMIC_ACQ_REL is enough.
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* Just always use the barriers manually by the rules above.
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*/
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#ifndef atomic_mb_read
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#define atomic_mb_read(ptr) ({ \
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typeof(*ptr) _val = atomic_read(ptr); \
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smp_rmb(); \
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_val; \
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})
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#endif
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#ifndef atomic_mb_set
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#define atomic_mb_set(ptr, i) do { \
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smp_wmb(); \
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atomic_set(ptr, i); \
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smp_mb(); \
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} while (0)
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#endif
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#ifndef atomic_xchg
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#if defined(__clang__)
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#define atomic_xchg(ptr, i) __sync_swap(ptr, i)
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#elif defined(__ATOMIC_SEQ_CST)
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#define atomic_xchg(ptr, i) ({ \
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typeof(*ptr) _new = (i), _old; \
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__atomic_exchange(ptr, &_new, &_old, __ATOMIC_SEQ_CST); \
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_old; \
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})
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#else
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/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */
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#define atomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i))
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#endif
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#endif
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/* Provide shorter names for GCC atomic builtins. */
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#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
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#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
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#define atomic_fetch_add __sync_fetch_and_add
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#define atomic_fetch_sub __sync_fetch_and_sub
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#define atomic_fetch_and __sync_fetch_and_and
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#define atomic_fetch_or __sync_fetch_and_or
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#define atomic_cmpxchg __sync_val_compare_and_swap
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/* And even shorter names that return void. */
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#define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1))
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#define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1))
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#define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n))
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#define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n))
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#define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n))
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#define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n))
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#endif
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