qemu-irix/target/arm
Jan Kiszka 8d04fb55de tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.

We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.

Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:

20338 jan       20   0  331m  75m 6904 R   99  0.9   0:50.95 qemu-system-arm
20337 jan       20   0  331m  75m 6904 S   20  0.9   0:26.50 qemu-system-arm

The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond

32206 jan       20   0  330m  73m 7036 R   82  0.9   1:06.00 qemu-system-arm
32204 jan       20   0  330m  73m 7036 S   21  0.9   0:17.03 qemu-system-arm

We don't benefit significantly, though, when the guest is not fully
loading a host CPU.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-24 10:32:45 +00:00
..
Makefile.objs
arch_dump.c
arm-powerctl.c
arm-powerctl.h
arm-semi.c
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2017-02-07 18:29:59 +00:00
cpu-qom.h
cpu.c target-arm: Enable vPMU support under TCG mode 2017-02-10 17:40:28 +00:00
cpu.h target-arm: Add support for PMU register PMINTENSET_EL1 2017-02-10 17:40:28 +00:00
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2017-01-20 11:15:10 +00:00
crypto_helper.c
gdbstub.c
gdbstub64.c
helper-a64.c target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper-a64.h target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper.c tcg: drop global lock during TCG code execution 2017-02-24 10:32:45 +00:00
helper.h target-arm: Use clz opcode 2017-01-10 08:06:11 -08:00
internals.h arm: Correctly handle watchpoints for BE32 CPUs 2017-02-07 18:29:59 +00:00
iwmmxt_helper.c
kvm-consts.h arm: add trailing ; after MISMATCH_CHECK 2017-02-01 03:37:18 +02:00
kvm-stub.c
kvm.c
kvm32.c
kvm64.c
kvm_arm.h
machine.c armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR 2017-01-27 15:29:08 +00:00
monitor.c
neon_helper.c
op_addsub.h
op_helper.c tcg: drop global lock during TCG code execution 2017-02-24 10:32:45 +00:00
psci.c target/arm/psci.c: If EL2 implemented, start CPUs in EL2 2017-01-20 11:15:10 +00:00
trace-events
translate-a64.c target/arm: A32, T32: Create Instruction Syndromes for Data Aborts 2017-02-07 18:30:00 +00:00
translate.c target/arm: A32, T32: Create Instruction Syndromes for Data Aborts 2017-02-07 18:30:00 +00:00
translate.h target/arm: A32, T32: Create Instruction Syndromes for Data Aborts 2017-02-07 18:30:00 +00:00