543 lines
14 KiB
C
543 lines
14 KiB
C
/*
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* Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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#include "hw.h"
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#include "mcf.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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/* General purpose timer module. */
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typedef struct {
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uint16_t tmr;
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uint16_t trr;
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uint16_t tcr;
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uint16_t ter;
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ptimer_state *timer;
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qemu_irq irq;
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int irq_state;
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} m5206_timer_state;
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#define TMR_RST 0x01
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#define TMR_CLK 0x06
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#define TMR_FRR 0x08
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#define TMR_ORI 0x10
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#define TMR_OM 0x20
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#define TMR_CE 0xc0
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#define TER_CAP 0x01
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#define TER_REF 0x02
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static void m5206_timer_update(m5206_timer_state *s)
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{
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if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF))
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qemu_irq_raise(s->irq);
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else
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qemu_irq_lower(s->irq);
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}
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static void m5206_timer_reset(m5206_timer_state *s)
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{
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s->tmr = 0;
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s->trr = 0;
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}
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static void m5206_timer_recalibrate(m5206_timer_state *s)
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{
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int prescale;
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int mode;
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ptimer_stop(s->timer);
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if ((s->tmr & TMR_RST) == 0)
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return;
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prescale = (s->tmr >> 8) + 1;
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mode = (s->tmr >> 1) & 3;
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if (mode == 2)
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prescale *= 16;
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if (mode == 3 || mode == 0)
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cpu_abort(cpu_single_env,
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"m5206_timer: mode %d not implemented\n", mode);
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if ((s->tmr & TMR_FRR) == 0)
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cpu_abort(cpu_single_env,
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"m5206_timer: free running mode not implemented\n");
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/* Assume 66MHz system clock. */
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ptimer_set_freq(s->timer, 66000000 / prescale);
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ptimer_set_limit(s->timer, s->trr, 0);
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ptimer_run(s->timer, 0);
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}
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static void m5206_timer_trigger(void *opaque)
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{
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m5206_timer_state *s = (m5206_timer_state *)opaque;
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s->ter |= TER_REF;
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m5206_timer_update(s);
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}
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static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
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{
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switch (addr) {
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case 0:
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return s->tmr;
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case 4:
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return s->trr;
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case 8:
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return s->tcr;
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case 0xc:
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return s->trr - ptimer_get_count(s->timer);
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case 0x11:
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return s->ter;
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default:
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return 0;
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}
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}
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static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
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{
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switch (addr) {
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case 0:
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if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) {
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m5206_timer_reset(s);
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}
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s->tmr = val;
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m5206_timer_recalibrate(s);
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break;
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case 4:
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s->trr = val;
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m5206_timer_recalibrate(s);
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break;
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case 8:
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s->tcr = val;
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break;
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case 0xc:
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ptimer_set_count(s->timer, val);
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break;
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case 0x11:
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s->ter &= ~val;
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break;
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default:
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break;
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}
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m5206_timer_update(s);
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}
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static m5206_timer_state *m5206_timer_init(qemu_irq irq)
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{
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m5206_timer_state *s;
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QEMUBH *bh;
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s = (m5206_timer_state *)qemu_mallocz(sizeof(m5206_timer_state));
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bh = qemu_bh_new(m5206_timer_trigger, s);
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s->timer = ptimer_init(bh);
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s->irq = irq;
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m5206_timer_reset(s);
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return s;
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}
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/* System Integration Module. */
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typedef struct {
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CPUState *env;
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m5206_timer_state *timer[2];
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void *uart[2];
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uint8_t scr;
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uint8_t icr[14];
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uint16_t imr; /* 1 == interrupt is masked. */
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uint16_t ipr;
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uint8_t rsr;
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uint8_t swivr;
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uint8_t par;
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/* Include the UART vector registers here. */
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uint8_t uivr[2];
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} m5206_mbar_state;
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/* Interrupt controller. */
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static int m5206_find_pending_irq(m5206_mbar_state *s)
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{
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int level;
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int vector;
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uint16_t active;
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int i;
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level = 0;
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vector = 0;
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active = s->ipr & ~s->imr;
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if (!active)
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return 0;
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for (i = 1; i < 14; i++) {
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if (active & (1 << i)) {
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if ((s->icr[i] & 0x1f) > level) {
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level = s->icr[i] & 0x1f;
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vector = i;
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}
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}
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}
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if (level < 4)
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vector = 0;
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return vector;
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}
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static void m5206_mbar_update(m5206_mbar_state *s)
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{
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int irq;
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int vector;
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int level;
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irq = m5206_find_pending_irq(s);
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if (irq) {
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int tmp;
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tmp = s->icr[irq];
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level = (tmp >> 2) & 7;
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if (tmp & 0x80) {
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/* Autovector. */
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vector = 24 + level;
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} else {
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switch (irq) {
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case 8: /* SWT */
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vector = s->swivr;
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break;
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case 12: /* UART1 */
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vector = s->uivr[0];
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break;
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case 13: /* UART2 */
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vector = s->uivr[1];
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break;
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default:
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/* Unknown vector. */
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fprintf(stderr, "Unhandled vector for IRQ %d\n", irq);
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vector = 0xf;
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break;
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}
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}
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} else {
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level = 0;
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vector = 0;
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}
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m68k_set_irq_level(s->env, level, vector);
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}
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static void m5206_mbar_set_irq(void *opaque, int irq, int level)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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if (level) {
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s->ipr |= 1 << irq;
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} else {
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s->ipr &= ~(1 << irq);
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}
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m5206_mbar_update(s);
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}
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/* System Integration Module. */
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static void m5206_mbar_reset(m5206_mbar_state *s)
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{
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s->scr = 0xc0;
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s->icr[1] = 0x04;
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s->icr[2] = 0x08;
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s->icr[3] = 0x0c;
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s->icr[4] = 0x10;
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s->icr[5] = 0x14;
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s->icr[6] = 0x18;
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s->icr[7] = 0x1c;
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s->icr[8] = 0x1c;
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s->icr[9] = 0x80;
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s->icr[10] = 0x80;
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s->icr[11] = 0x80;
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s->icr[12] = 0x00;
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s->icr[13] = 0x00;
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s->imr = 0x3ffe;
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s->rsr = 0x80;
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s->swivr = 0x0f;
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s->par = 0;
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}
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static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
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{
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if (offset >= 0x100 && offset < 0x120) {
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return m5206_timer_read(s->timer[0], offset - 0x100);
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} else if (offset >= 0x120 && offset < 0x140) {
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return m5206_timer_read(s->timer[1], offset - 0x120);
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} else if (offset >= 0x140 && offset < 0x160) {
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return mcf_uart_read(s->uart[0], offset - 0x140);
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} else if (offset >= 0x180 && offset < 0x1a0) {
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return mcf_uart_read(s->uart[1], offset - 0x180);
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}
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switch (offset) {
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case 0x03: return s->scr;
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case 0x14 ... 0x20: return s->icr[offset - 0x13];
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case 0x36: return s->imr;
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case 0x3a: return s->ipr;
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case 0x40: return s->rsr;
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case 0x41: return 0;
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case 0x42: return s->swivr;
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case 0x50:
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/* DRAM mask register. */
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/* FIXME: currently hardcoded to 128Mb. */
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{
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uint32_t mask = ~0;
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while (mask > ram_size)
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mask >>= 1;
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return mask & 0x0ffe0000;
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}
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case 0x5c: return 1; /* DRAM bank 1 empty. */
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case 0xcb: return s->par;
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case 0x170: return s->uivr[0];
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case 0x1b0: return s->uivr[1];
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}
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cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
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return 0;
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}
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static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
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uint32_t value)
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{
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if (offset >= 0x100 && offset < 0x120) {
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m5206_timer_write(s->timer[0], offset - 0x100, value);
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return;
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} else if (offset >= 0x120 && offset < 0x140) {
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m5206_timer_write(s->timer[1], offset - 0x120, value);
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return;
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} else if (offset >= 0x140 && offset < 0x160) {
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mcf_uart_write(s->uart[0], offset - 0x140, value);
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return;
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} else if (offset >= 0x180 && offset < 0x1a0) {
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mcf_uart_write(s->uart[1], offset - 0x180, value);
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return;
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}
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switch (offset) {
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case 0x03:
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s->scr = value;
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break;
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case 0x14 ... 0x20:
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s->icr[offset - 0x13] = value;
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m5206_mbar_update(s);
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break;
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case 0x36:
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s->imr = value;
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m5206_mbar_update(s);
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break;
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case 0x40:
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s->rsr &= ~value;
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break;
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case 0x41:
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/* TODO: implement watchdog. */
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break;
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case 0x42:
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s->swivr = value;
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break;
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case 0xcb:
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s->par = value;
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break;
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case 0x170:
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s->uivr[0] = value;
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break;
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case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
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/* Not implemented: UART Output port bits. */
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break;
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case 0x1b0:
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s->uivr[1] = value;
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break;
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default:
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cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
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break;
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}
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}
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/* Internal peripherals use a variety of register widths.
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This lookup table allows a single routine to handle all of them. */
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static const int m5206_mbar_width[] =
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{
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/* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
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/* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
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/* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
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/* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
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/* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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/* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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};
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static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
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static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
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static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
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}
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if (m5206_mbar_width[offset >> 2] > 1) {
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uint16_t val;
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val = m5206_mbar_readw(opaque, offset & ~1);
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if ((offset & 1) == 0) {
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val >>= 8;
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}
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return val & 0xff;
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}
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return m5206_mbar_read(s, offset);
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}
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static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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int width;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
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}
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width = m5206_mbar_width[offset >> 2];
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if (width > 2) {
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uint32_t val;
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val = m5206_mbar_readl(opaque, offset & ~3);
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if ((offset & 3) == 0)
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val >>= 16;
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return val & 0xffff;
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} else if (width < 2) {
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uint16_t val;
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val = m5206_mbar_readb(opaque, offset) << 8;
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val |= m5206_mbar_readb(opaque, offset + 1);
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return val;
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}
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return m5206_mbar_read(s, offset);
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}
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static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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int width;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
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}
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width = m5206_mbar_width[offset >> 2];
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if (width < 4) {
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uint32_t val;
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val = m5206_mbar_readw(opaque, offset) << 16;
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val |= m5206_mbar_readw(opaque, offset + 2);
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return val;
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}
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return m5206_mbar_read(s, offset);
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}
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static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
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uint32_t value);
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static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
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uint32_t value);
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static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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int width;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
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}
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width = m5206_mbar_width[offset >> 2];
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if (width > 1) {
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uint32_t tmp;
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tmp = m5206_mbar_readw(opaque, offset & ~1);
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if (offset & 1) {
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tmp = (tmp & 0xff00) | value;
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} else {
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tmp = (tmp & 0x00ff) | (value << 8);
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}
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m5206_mbar_writew(opaque, offset & ~1, tmp);
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return;
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}
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m5206_mbar_write(s, offset, value);
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}
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static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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int width;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
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}
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width = m5206_mbar_width[offset >> 2];
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if (width > 2) {
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uint32_t tmp;
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tmp = m5206_mbar_readl(opaque, offset & ~3);
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if (offset & 3) {
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tmp = (tmp & 0xffff0000) | value;
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} else {
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tmp = (tmp & 0x0000ffff) | (value << 16);
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}
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m5206_mbar_writel(opaque, offset & ~3, tmp);
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return;
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} else if (width < 2) {
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m5206_mbar_writeb(opaque, offset, value >> 8);
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m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
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return;
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}
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m5206_mbar_write(s, offset, value);
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}
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static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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m5206_mbar_state *s = (m5206_mbar_state *)opaque;
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int width;
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offset &= 0x3ff;
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if (offset > 0x200) {
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cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
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}
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width = m5206_mbar_width[offset >> 2];
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if (width < 4) {
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m5206_mbar_writew(opaque, offset, value >> 16);
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m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
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return;
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}
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m5206_mbar_write(s, offset, value);
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}
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static CPUReadMemoryFunc *m5206_mbar_readfn[] = {
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m5206_mbar_readb,
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m5206_mbar_readw,
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m5206_mbar_readl
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};
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static CPUWriteMemoryFunc *m5206_mbar_writefn[] = {
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m5206_mbar_writeb,
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m5206_mbar_writew,
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m5206_mbar_writel
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};
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qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
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{
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m5206_mbar_state *s;
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qemu_irq *pic;
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int iomemtype;
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s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
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iomemtype = cpu_register_io_memory(0, m5206_mbar_readfn,
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m5206_mbar_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
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s->timer[0] = m5206_timer_init(pic[9]);
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s->timer[1] = m5206_timer_init(pic[10]);
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s->uart[0] = mcf_uart_init(pic[12], serial_hds[0]);
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s->uart[1] = mcf_uart_init(pic[13], serial_hds[1]);
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s->env = env;
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m5206_mbar_reset(s);
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return pic;
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}
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