134 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			134 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * QEMU emulation of an Intel IOMMU (VT-d)
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|  *   (DMA Remapping device)
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|  *
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|  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
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|  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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| 
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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| 
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|  * You should have received a copy of the GNU General Public License along
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|  * with this program; if not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef INTEL_IOMMU_H
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| #define INTEL_IOMMU_H
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| #include "hw/qdev.h"
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| #include "sysemu/dma.h"
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| 
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| #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
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| #define INTEL_IOMMU_DEVICE(obj) \
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|      OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
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| 
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| /* DMAR Hardware Unit Definition address (IOMMU unit) */
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| #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
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| 
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| #define VTD_PCI_BUS_MAX             256
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| #define VTD_PCI_SLOT_MAX            32
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| #define VTD_PCI_FUNC_MAX            8
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| #define VTD_PCI_DEVFN_MAX           256
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| #define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
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| #define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
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| #define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
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| #define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)
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| 
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| #define DMAR_REG_SIZE               0x230
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| #define VTD_HOST_ADDRESS_WIDTH      39
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| #define VTD_HAW_MASK                ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
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| 
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| typedef struct VTDContextEntry VTDContextEntry;
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| typedef struct VTDContextCacheEntry VTDContextCacheEntry;
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| typedef struct IntelIOMMUState IntelIOMMUState;
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| typedef struct VTDAddressSpace VTDAddressSpace;
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| typedef struct VTDIOTLBEntry VTDIOTLBEntry;
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| typedef struct VTDBus VTDBus;
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| 
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| /* Context-Entry */
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| struct VTDContextEntry {
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|     uint64_t lo;
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|     uint64_t hi;
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| };
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| 
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| struct VTDContextCacheEntry {
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|     /* The cache entry is obsolete if
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|      * context_cache_gen!=IntelIOMMUState.context_cache_gen
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|      */
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|     uint32_t context_cache_gen;
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|     struct VTDContextEntry context_entry;
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| };
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| 
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| struct VTDAddressSpace {
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|     PCIBus *bus;
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|     uint8_t devfn;
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|     AddressSpace as;
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|     MemoryRegion iommu;
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|     IntelIOMMUState *iommu_state;
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|     VTDContextCacheEntry context_cache_entry;
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| };
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| 
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| struct VTDBus {
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|     PCIBus* bus;		/* A reference to the bus to provide translation for */
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|     VTDAddressSpace *dev_as[0];	/* A table of VTDAddressSpace objects indexed by devfn */
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| };
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| 
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| struct VTDIOTLBEntry {
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|     uint64_t gfn;
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|     uint16_t domain_id;
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|     uint64_t slpte;
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|     uint64_t mask;
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|     bool read_flags;
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|     bool write_flags;
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| };
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| 
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| /* The iommu (DMAR) device state struct */
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| struct IntelIOMMUState {
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|     SysBusDevice busdev;
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|     MemoryRegion csrmem;
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|     uint8_t csr[DMAR_REG_SIZE];     /* register values */
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|     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
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|     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
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|     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
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|     uint32_t version;
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| 
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|     dma_addr_t root;                /* Current root table pointer */
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|     bool root_extended;             /* Type of root table (extended or not) */
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|     bool dmar_enabled;              /* Set if DMA remapping is enabled */
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| 
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|     uint16_t iq_head;               /* Current invalidation queue head */
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|     uint16_t iq_tail;               /* Current invalidation queue tail */
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|     dma_addr_t iq;                  /* Current invalidation queue pointer */
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|     uint16_t iq_size;               /* IQ Size in number of entries */
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|     bool qi_enabled;                /* Set if the QI is enabled */
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|     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
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| 
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|     /* The index of the Fault Recording Register to be used next.
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|      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
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|      */
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|     uint16_t next_frcd_reg;
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| 
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|     uint64_t cap;                   /* The value of capability reg */
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|     uint64_t ecap;                  /* The value of extended capability reg */
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| 
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|     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
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|     GHashTable *iotlb;              /* IOTLB */
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| 
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|     MemoryRegionIOMMUOps iommu_ops;
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|     GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
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|     VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
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| };
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| 
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| /* Find the VTD Address space associated with the given bus pointer,
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|  * create a new one if none exists
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|  */
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| VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
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| 
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| #endif
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