* Implement priority handling properly via GICC_APR
* Enable TZ extensions on the GIC if we're using them
* Minor preparatory patches for EL3 support
* cadence_gem: Correct Marvell PHY SPCFC reset value
* Support AHCI in ZynqMP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJV7xFhAAoJEDwlJe0UNgzeobsP/iNDaNaLy/KDS2sErdPlHN6W
1woHq4dP9Kv6DC55KE2lINDd/Y7XeFSz5A2hqVhOqLQMXysfW7gbT1KEWr7nw4Da
c2fQgPPCsYd1XSB3PXHXJSYP0BgFNjRncvBgM4V/w4cPmETHPqaYBs2gQCm81Sg5
FnjIKUJlr1DTE4jyJu4wu7lbJIeIS2bZnFqORd6uadoslyu+5yB0NKsEjqB88U+4
+aRDFo3aSpUBqIy0KGIB73pxCwcHu6bqgmRXiORHt96OIzhMpgPLtwk/wjY3gvi8
bD04ImGV5aQZpK+feIqj9AjJzL+Lq8hUQXrHT0q9tcBpXMrRjTcHZrdAy4/fJHEL
sbO13KyVHAINSJAzNHWF+702iEvhc95EEV1mdftZ1EkNkSRnVpSS5mmjxriCLHB/
t6b5d60Mqbou71LL1DCcbj2eMxRNwjhwfkGfqXxo7DVSORonV2DSRSDqIy+X24gV
pEfphi3UGL7hDRJwx42nFtW3ezPB5tz0WgDT1eS32H5O2JSr0NRLS49mT6Jqbd4J
2JWeEzgcRYcRymJMlZANNhL+7CORT7ZzjXRitTheq91pkkcf9SBkl55OI0MXH/JG
vgqwwLKJiKZLxi1BJUJxvN828udH4EpIB6wc5RV9LAsTVoEftYdpc5O3Us4ae03+
Dca5VcsBowY00cOIeYe5
=hLY2
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150908' into staging
target-arm queue:
* Implement priority handling properly via GICC_APR
* Enable TZ extensions on the GIC if we're using them
* Minor preparatory patches for EL3 support
* cadence_gem: Correct Marvell PHY SPCFC reset value
* Support AHCI in ZynqMP
# gpg: Signature made Tue 08 Sep 2015 17:48:33 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20150908:
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort
ahci.c: Don't assume AHCIState's parent is AHCIPCIState
ahci: Separate the AHCI state structure into the header
cadence_gem: Correct Marvell PHY SPCFC reset value
target-arm: Add AArch64 access to PAR_EL1
target-arm: Correct opc1 for AT_S12Exx
target-arm: Log the target EL when taking exceptions
target-arm: Fix default_exception_el() function for the case when EL3 is not supported
hw/arm/virt: Enable TZ extensions on the GIC if we are using them
hw/arm/virt: Default to not providing TrustZone support
hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs
hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot
hw/arm: new interface for devices which need to behave differently for kernel boot
qom: Add recursive version of object_child_for_each
hw/intc/arm_gic: Actually set the active bits for active interrupts
hw/intc/arm_gic: Drop running_irq and last_active arrays
hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers
hw/intc/arm_gic: Running priority is group priority, not full priority
armv7m_nvic: Implement ICSR without using internal GIC state
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
fc04a730b7