mirror of https://github.com/zeldaret/tp.git
142 lines
4.0 KiB
ArmAsm
142 lines
4.0 KiB
ArmAsm
.include "macros.inc"
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.section .text, "ax" # 80339cc0
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.global PPCMfmsr
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PPCMfmsr:
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/* 80339CC0 00336C00 7C 60 00 A6 */ mfmsr r3
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/* 80339CC4 00336C04 4E 80 00 20 */ blr
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.global PPCMtmsr
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PPCMtmsr:
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/* 80339CC8 00336C08 7C 60 01 24 */ mtmsr r3
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/* 80339CCC 00336C0C 4E 80 00 20 */ blr
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.global PPCMfhid0
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PPCMfhid0:
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/* 80339CD0 00336C10 7C 70 FA A6 */ mfspr r3, 0x3f0
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/* 80339CD4 00336C14 4E 80 00 20 */ blr
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.global PPCMthid0
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PPCMthid0:
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/* 80339CD8 00336C18 7C 70 FB A6 */ mtspr 0x3f0, r3
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/* 80339CDC 00336C1C 4E 80 00 20 */ blr
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.global PPCMfl2cr
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PPCMfl2cr:
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/* 80339CE0 00336C20 7C 79 FA A6 */ mfspr r3, 0x3f9
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/* 80339CE4 00336C24 4E 80 00 20 */ blr
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.global PPCMtl2cr
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PPCMtl2cr:
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/* 80339CE8 00336C28 7C 79 FB A6 */ mtspr 0x3f9, r3
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/* 80339CEC 00336C2C 4E 80 00 20 */ blr
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.global PPCMtdec
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PPCMtdec:
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/* 80339CF0 00336C30 7C 76 03 A6 */ mtspr 0x16, r3
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/* 80339CF4 00336C34 4E 80 00 20 */ blr
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.global PPCSync
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PPCSync:
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/* 80339CF8 00336C38 44 00 00 02 */ sc
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/* 80339CFC 00336C3C 4E 80 00 20 */ blr
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.global PPCHalt
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PPCHalt:
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/* 80339D00 00336C40 7C 00 04 AC */ sync 0
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lbl_80339D04:
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/* 80339D04 00336C44 60 00 00 00 */ nop
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/* 80339D08 00336C48 38 60 00 00 */ li r3, 0
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/* 80339D0C 00336C4C 60 00 00 00 */ nop
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/* 80339D10 00336C50 4B FF FF F4 */ b lbl_80339D04
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.global PPCMtmmcr0
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PPCMtmmcr0:
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/* 80339D14 00336C54 7C 78 EB A6 */ mtspr 0x3b8, r3
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/* 80339D18 00336C58 4E 80 00 20 */ blr
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.global PPCMtmmcr1
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PPCMtmmcr1:
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/* 80339D1C 00336C5C 7C 7C EB A6 */ mtspr 0x3bc, r3
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/* 80339D20 00336C60 4E 80 00 20 */ blr
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.global PPCMtpmc1
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PPCMtpmc1:
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/* 80339D24 00336C64 7C 79 EB A6 */ mtspr 0x3b9, r3
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/* 80339D28 00336C68 4E 80 00 20 */ blr
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.global PPCMtpmc2
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PPCMtpmc2:
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/* 80339D2C 00336C6C 7C 7A EB A6 */ mtspr 0x3ba, r3
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/* 80339D30 00336C70 4E 80 00 20 */ blr
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.global PPCMtpmc3
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PPCMtpmc3:
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/* 80339D34 00336C74 7C 7D EB A6 */ mtspr 0x3bd, r3
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/* 80339D38 00336C78 4E 80 00 20 */ blr
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.global PPCMtpmc4
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PPCMtpmc4:
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/* 80339D3C 00336C7C 7C 7E EB A6 */ mtspr 0x3be, r3
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/* 80339D40 00336C80 4E 80 00 20 */ blr
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.global PPCMffpscr
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PPCMffpscr:
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/* 80339D44 00336C84 94 21 FF E8 */ stwu r1, -0x18(r1)
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/* 80339D48 00336C88 DB E1 00 10 */ stfd f31, 0x10(r1)
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/* 80339D4C 00336C8C FF E0 04 8E */ mffs f31
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/* 80339D50 00336C90 DB E1 00 08 */ stfd f31, 8(r1)
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/* 80339D54 00336C94 80 61 00 0C */ lwz r3, 0xc(r1)
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/* 80339D58 00336C98 CB E1 00 10 */ lfd f31, 0x10(r1)
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/* 80339D5C 00336C9C 38 21 00 18 */ addi r1, r1, 0x18
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/* 80339D60 00336CA0 4E 80 00 20 */ blr
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.global PPCMtfpscr
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PPCMtfpscr:
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/* 80339D64 00336CA4 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80339D68 00336CA8 DB E1 00 18 */ stfd f31, 0x18(r1)
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/* 80339D6C 00336CAC 38 80 00 00 */ li r4, 0
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/* 80339D70 00336CB0 90 81 00 10 */ stw r4, 0x10(r1)
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/* 80339D74 00336CB4 90 61 00 14 */ stw r3, 0x14(r1)
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/* 80339D78 00336CB8 CB E1 00 10 */ lfd f31, 0x10(r1)
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/* 80339D7C 00336CBC FD FE FD 8E */ mtfsf 0xff, f31
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/* 80339D80 00336CC0 CB E1 00 18 */ lfd f31, 0x18(r1)
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/* 80339D84 00336CC4 38 21 00 20 */ addi r1, r1, 0x20
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/* 80339D88 00336CC8 4E 80 00 20 */ blr
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.global PPCMfhid2
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PPCMfhid2:
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/* 80339D8C 00336CCC 7C 78 E2 A6 */ mfspr r3, 0x398
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/* 80339D90 00336CD0 4E 80 00 20 */ blr
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.global PPCMthid2
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PPCMthid2:
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/* 80339D94 00336CD4 7C 78 E3 A6 */ mtspr 0x398, r3
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/* 80339D98 00336CD8 4E 80 00 20 */ blr
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.global PPCMtwpar
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PPCMtwpar:
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/* 80339D9C 00336CDC 7C 79 E3 A6 */ mtspr 0x399, r3
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/* 80339DA0 00336CE0 4E 80 00 20 */ blr
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.global PPCDisableSpeculation
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PPCDisableSpeculation:
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/* 80339DA4 00336CE4 7C 08 02 A6 */ mflr r0
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/* 80339DA8 00336CE8 90 01 00 04 */ stw r0, 4(r1)
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/* 80339DAC 00336CEC 94 21 FF F8 */ stwu r1, -8(r1)
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/* 80339DB0 00336CF0 4B FF FF 21 */ bl PPCMfhid0
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/* 80339DB4 00336CF4 60 63 02 00 */ ori r3, r3, 0x200
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/* 80339DB8 00336CF8 4B FF FF 21 */ bl PPCMthid0
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/* 80339DBC 00336CFC 80 01 00 0C */ lwz r0, 0xc(r1)
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/* 80339DC0 00336D00 38 21 00 08 */ addi r1, r1, 8
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/* 80339DC4 00336D04 7C 08 03 A6 */ mtlr r0
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/* 80339DC8 00336D08 4E 80 00 20 */ blr
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.global PPCSetFpNonIEEEMode
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PPCSetFpNonIEEEMode:
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/* 80339DCC 00336D0C FF A0 00 4C */ mtfsb1 0x1d
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/* 80339DD0 00336D10 4E 80 00 20 */ blr
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