mirror of https://github.com/zeldaret/tp.git
88 lines
3.5 KiB
ArmAsm
88 lines
3.5 KiB
ArmAsm
.include "macros.inc"
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.section .text, "ax" # 80266440
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.global cTr_SingleCut
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cTr_SingleCut:
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/* 80266440 00263380 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80266444 00263384 7C 08 02 A6 */ mflr r0
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/* 80266448 00263388 90 01 00 14 */ stw r0, 0x14(r1)
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/* 8026644C 0026338C 4B FF FA 2D */ bl cLs_SingleCut
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/* 80266450 00263390 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80266454 00263394 7C 08 03 A6 */ mtlr r0
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/* 80266458 00263398 38 21 00 10 */ addi r1, r1, 0x10
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/* 8026645C 0026339C 4E 80 00 20 */ blr
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.global cTr_Addition
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cTr_Addition:
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/* 80266460 002633A0 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80266464 002633A4 7C 08 02 A6 */ mflr r0
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/* 80266468 002633A8 90 01 00 14 */ stw r0, 0x14(r1)
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/* 8026646C 002633AC 80 03 00 04 */ lwz r0, 4(r3)
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/* 80266470 002633B0 7C 04 00 00 */ cmpw r4, r0
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/* 80266474 002633B4 41 80 00 0C */ blt lbl_80266480
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/* 80266478 002633B8 38 60 00 00 */ li r3, 0
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/* 8026647C 002633BC 48 00 00 18 */ b lbl_80266494
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lbl_80266480:
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/* 80266480 002633C0 80 63 00 00 */ lwz r3, 0(r3)
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/* 80266484 002633C4 1C 04 00 0C */ mulli r0, r4, 0xc
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/* 80266488 002633C8 7C 63 02 14 */ add r3, r3, r0
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/* 8026648C 002633CC 7C A4 2B 78 */ mr r4, r5
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/* 80266490 002633D0 4B FF FA 6D */ bl cLs_Addition
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lbl_80266494:
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/* 80266494 002633D4 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80266498 002633D8 7C 08 03 A6 */ mtlr r0
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/* 8026649C 002633DC 38 21 00 10 */ addi r1, r1, 0x10
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/* 802664A0 002633E0 4E 80 00 20 */ blr
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.global cTr_Insert
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cTr_Insert:
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/* 802664A4 002633E4 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 802664A8 002633E8 7C 08 02 A6 */ mflr r0
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/* 802664AC 002633EC 90 01 00 14 */ stw r0, 0x14(r1)
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/* 802664B0 002633F0 80 03 00 04 */ lwz r0, 4(r3)
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/* 802664B4 002633F4 7C 04 00 00 */ cmpw r4, r0
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/* 802664B8 002633F8 41 80 00 0C */ blt lbl_802664C4
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/* 802664BC 002633FC 38 60 00 00 */ li r3, 0
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/* 802664C0 00263400 48 00 00 18 */ b lbl_802664D8
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lbl_802664C4:
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/* 802664C4 00263404 80 63 00 00 */ lwz r3, 0(r3)
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/* 802664C8 00263408 1C 04 00 0C */ mulli r0, r4, 0xc
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/* 802664CC 0026340C 7C 63 02 14 */ add r3, r3, r0
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/* 802664D0 00263410 7C C4 33 78 */ mr r4, r6
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/* 802664D4 00263414 4B FF FA 9D */ bl cLs_Insert
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lbl_802664D8:
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/* 802664D8 00263418 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 802664DC 0026341C 7C 08 03 A6 */ mtlr r0
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/* 802664E0 00263420 38 21 00 10 */ addi r1, r1, 0x10
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/* 802664E4 00263424 4E 80 00 20 */ blr
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.global cTr_Create
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cTr_Create:
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/* 802664E8 00263428 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 802664EC 0026342C 7C 08 02 A6 */ mflr r0
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/* 802664F0 00263430 90 01 00 14 */ stw r0, 0x14(r1)
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/* 802664F4 00263434 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 802664F8 00263438 93 C1 00 08 */ stw r30, 8(r1)
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/* 802664FC 0026343C 7C 9E 23 78 */ mr r30, r4
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/* 80266500 00263440 7C BF 2B 78 */ mr r31, r5
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/* 80266504 00263444 93 C3 00 00 */ stw r30, 0(r3)
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/* 80266508 00263448 93 E3 00 04 */ stw r31, 4(r3)
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/* 8026650C 0026344C 48 00 00 10 */ b lbl_8026651C
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lbl_80266510:
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/* 80266510 00263450 7F C3 F3 78 */ mr r3, r30
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/* 80266514 00263454 3B DE 00 0C */ addi r30, r30, 0xc
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/* 80266518 00263458 4B FF FB 29 */ bl cLs_Create
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lbl_8026651C:
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/* 8026651C 0026345C 2C 1F 00 00 */ cmpwi r31, 0
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/* 80266520 00263460 3B FF FF FF */ addi r31, r31, -1
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/* 80266524 00263464 41 81 FF EC */ bgt lbl_80266510
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/* 80266528 00263468 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 8026652C 0026346C 83 C1 00 08 */ lwz r30, 8(r1)
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/* 80266530 00263470 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80266534 00263474 7C 08 03 A6 */ mtlr r0
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/* 80266538 00263478 38 21 00 10 */ addi r1, r1, 0x10
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/* 8026653C 0026347C 4E 80 00 20 */ blr
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