tp/asm/f/pc/f_pc_load.s

82 lines
3.1 KiB
ArmAsm

.include "macros.inc"
.section .text, "ax" # 80021fb8
.global fpcLd_Use
fpcLd_Use:
/* 80021FB8 0001EEF8 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 80021FBC 0001EEFC 7C 08 02 A6 */ mflr r0
/* 80021FC0 0001EF00 90 01 00 14 */ stw r0, 0x14(r1)
/* 80021FC4 0001EF04 93 E1 00 0C */ stw r31, 0xc(r1)
/* 80021FC8 0001EF08 7C 7F 1B 78 */ mr r31, r3
/* 80021FCC 0001EF0C 48 00 00 3D */ bl fpcLd_IsLoaded
/* 80021FD0 0001EF10 2C 03 00 01 */ cmpwi r3, 1
/* 80021FD4 0001EF14 40 82 00 1C */ bne lbl_80021FF0
/* 80021FD8 0001EF18 7F E3 FB 78 */ mr r3, r31
/* 80021FDC 0001EF1C 48 00 00 75 */ bl fpcLd_Load
/* 80021FE0 0001EF20 2C 03 00 04 */ cmpwi r3, 4
/* 80021FE4 0001EF24 40 82 00 0C */ bne lbl_80021FF0
/* 80021FE8 0001EF28 38 60 00 01 */ li r3, 1
/* 80021FEC 0001EF2C 48 00 00 08 */ b lbl_80021FF4
lbl_80021FF0:
/* 80021FF0 0001EF30 38 60 00 00 */ li r3, 0
lbl_80021FF4:
/* 80021FF4 0001EF34 83 E1 00 0C */ lwz r31, 0xc(r1)
/* 80021FF8 0001EF38 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80021FFC 0001EF3C 7C 08 03 A6 */ mtlr r0
/* 80022000 0001EF40 38 21 00 10 */ addi r1, r1, 0x10
/* 80022004 0001EF44 4E 80 00 20 */ blr
.global fpcLd_IsLoaded
fpcLd_IsLoaded:
/* 80022008 0001EF48 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 8002200C 0001EF4C 7C 08 02 A6 */ mflr r0
/* 80022010 0001EF50 90 01 00 14 */ stw r0, 0x14(r1)
/* 80022014 0001EF54 7C 63 07 34 */ extsh r3, r3
/* 80022018 0001EF58 4B FF 65 2D */ bl cDyl_IsLinked
/* 8002201C 0001EF5C 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80022020 0001EF60 7C 08 03 A6 */ mtlr r0
/* 80022024 0001EF64 38 21 00 10 */ addi r1, r1, 0x10
/* 80022028 0001EF68 4E 80 00 20 */ blr
.global fpcLd_Free
fpcLd_Free:
/* 8002202C 0001EF6C 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 80022030 0001EF70 7C 08 02 A6 */ mflr r0
/* 80022034 0001EF74 90 01 00 14 */ stw r0, 0x14(r1)
/* 80022038 0001EF78 7C 63 07 34 */ extsh r3, r3
/* 8002203C 0001EF7C 4B FF 65 41 */ bl cDyl_Unlink
/* 80022040 0001EF80 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80022044 0001EF84 7C 08 03 A6 */ mtlr r0
/* 80022048 0001EF88 38 21 00 10 */ addi r1, r1, 0x10
/* 8002204C 0001EF8C 4E 80 00 20 */ blr
.global fpcLd_Load
fpcLd_Load:
/* 80022050 0001EF90 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 80022054 0001EF94 7C 08 02 A6 */ mflr r0
/* 80022058 0001EF98 90 01 00 14 */ stw r0, 0x14(r1)
/* 8002205C 0001EF9C 7C 63 07 34 */ extsh r3, r3
/* 80022060 0001EFA0 4B FF 65 61 */ bl cDyl_LinkASync
/* 80022064 0001EFA4 2C 03 00 04 */ cmpwi r3, 4
/* 80022068 0001EFA8 41 82 00 14 */ beq lbl_8002207C
/* 8002206C 0001EFAC 40 80 00 20 */ bge lbl_8002208C
/* 80022070 0001EFB0 2C 03 00 00 */ cmpwi r3, 0
/* 80022074 0001EFB4 41 82 00 10 */ beq lbl_80022084
/* 80022078 0001EFB8 48 00 00 14 */ b lbl_8002208C
lbl_8002207C:
/* 8002207C 0001EFBC 38 60 00 04 */ li r3, 4
/* 80022080 0001EFC0 48 00 00 10 */ b lbl_80022090
lbl_80022084:
/* 80022084 0001EFC4 38 60 00 00 */ li r3, 0
/* 80022088 0001EFC8 48 00 00 08 */ b lbl_80022090
lbl_8002208C:
/* 8002208C 0001EFCC 38 60 00 05 */ li r3, 5
lbl_80022090:
/* 80022090 0001EFD0 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80022094 0001EFD4 7C 08 03 A6 */ mtlr r0
/* 80022098 0001EFD8 38 21 00 10 */ addi r1, r1, 0x10
/* 8002209C 0001EFDC 4E 80 00 20 */ blr