mirror of https://github.com/zeldaret/tp.git
51 lines
2.1 KiB
ArmAsm
51 lines
2.1 KiB
ArmAsm
lbl_80370134:
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/* 80370134 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80370138 7C 08 02 A6 */ mflr r0
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/* 8037013C 3C 60 80 45 */ lis r3, gTRKState@ha /* 0x8044F294@ha */
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/* 80370140 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80370144 38 63 F2 94 */ addi r3, r3, gTRKState@l /* 0x8044F294@l */
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/* 80370148 80 03 00 9C */ lwz r0, 0x9c(r3)
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/* 8037014C 2C 00 00 00 */ cmpwi r0, 0
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/* 80370150 41 82 00 10 */ beq lbl_80370160
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/* 80370154 38 00 00 00 */ li r0, 0
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/* 80370158 90 03 00 9C */ stw r0, 0x9c(r3)
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/* 8037015C 48 00 00 74 */ b lbl_803701D0
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lbl_80370160:
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/* 80370160 3C 60 80 45 */ lis r3, gTRKCPUState@ha /* 0x8044F338@ha */
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/* 80370164 38 63 F3 38 */ addi r3, r3, gTRKCPUState@l /* 0x8044F338@l */
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/* 80370168 80 03 02 F8 */ lwz r0, 0x2f8(r3)
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/* 8037016C 54 00 04 3E */ clrlwi r0, r0, 0x10
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/* 80370170 2C 00 0D 00 */ cmpwi r0, 0xd00
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/* 80370174 41 82 00 14 */ beq lbl_80370188
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/* 80370178 40 80 00 44 */ bge lbl_803701BC
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/* 8037017C 2C 00 07 00 */ cmpwi r0, 0x700
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/* 80370180 41 82 00 08 */ beq lbl_80370188
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/* 80370184 48 00 00 38 */ b lbl_803701BC
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lbl_80370188:
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/* 80370188 3C 80 80 45 */ lis r4, gTRKCPUState@ha /* 0x8044F338@ha */
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/* 8037018C 38 61 00 08 */ addi r3, r1, 8
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/* 80370190 38 84 F3 38 */ addi r4, r4, gTRKCPUState@l /* 0x8044F338@l */
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/* 80370194 80 84 00 80 */ lwz r4, 0x80(r4)
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/* 80370198 48 00 0B F1 */ bl TRKTargetReadInstruction
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/* 8037019C 80 61 00 08 */ lwz r3, 8(r1)
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/* 803701A0 3C 03 F0 20 */ addis r0, r3, 0xf020
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/* 803701A4 28 00 00 00 */ cmplwi r0, 0
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/* 803701A8 40 82 00 0C */ bne lbl_803701B4
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/* 803701AC 38 80 00 05 */ li r4, 5
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/* 803701B0 48 00 00 10 */ b lbl_803701C0
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lbl_803701B4:
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/* 803701B4 38 80 00 03 */ li r4, 3
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/* 803701B8 48 00 00 08 */ b lbl_803701C0
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lbl_803701BC:
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/* 803701BC 38 80 00 04 */ li r4, 4
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lbl_803701C0:
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/* 803701C0 38 61 00 0C */ addi r3, r1, 0xc
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/* 803701C4 4B FF CA 79 */ bl TRKConstructEvent
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/* 803701C8 38 61 00 0C */ addi r3, r1, 0xc
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/* 803701CC 4B FF CA 89 */ bl TRKPostEvent
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lbl_803701D0:
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/* 803701D0 80 01 00 24 */ lwz r0, 0x24(r1)
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/* 803701D4 7C 08 03 A6 */ mtlr r0
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/* 803701D8 38 21 00 20 */ addi r1, r1, 0x20
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/* 803701DC 4E 80 00 20 */ blr
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