mirror of https://github.com/zeldaret/tp.git
51 lines
2.1 KiB
ArmAsm
51 lines
2.1 KiB
ArmAsm
lbl_80149300:
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/* 80149300 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80149304 7C 08 02 A6 */ mflr r0
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/* 80149308 90 01 00 24 */ stw r0, 0x24(r1)
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/* 8014930C 93 E1 00 1C */ stw r31, 0x1c(r1)
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/* 80149310 7C 7F 1B 78 */ mr r31, r3
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/* 80149314 38 7F 0B 74 */ addi r3, r31, 0xb74
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/* 80149318 A0 9F 0E 1E */ lhz r4, 0xe1e(r31)
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/* 8014931C 38 A1 00 0C */ addi r5, r1, 0xc
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/* 80149320 38 C1 00 08 */ addi r6, r1, 8
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/* 80149324 4B FF C5 9D */ bl play__22daNpcT_MotionSeqMngr_cFUsPiPf
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/* 80149328 2C 03 00 00 */ cmpwi r3, 0
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/* 8014932C 41 82 00 78 */ beq lbl_801493A4
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/* 80149330 38 A0 00 00 */ li r5, 0
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/* 80149334 C0 21 00 08 */ lfs f1, 8(r1)
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/* 80149338 C0 02 99 E8 */ lfs f0, lit_4148(r2)
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/* 8014933C FC 01 00 40 */ fcmpo cr0, f1, f0
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/* 80149340 40 80 00 08 */ bge lbl_80149348
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/* 80149344 38 A0 00 01 */ li r5, 1
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lbl_80149348:
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/* 80149348 7F E3 FB 78 */ mr r3, r31
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/* 8014934C 80 81 00 0C */ lwz r4, 0xc(r1)
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/* 80149350 C0 02 99 D8 */ lfs f0, lit_4116(r2)
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/* 80149354 FC 01 00 40 */ fcmpo cr0, f1, f0
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/* 80149358 40 80 00 08 */ bge lbl_80149360
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/* 8014935C C0 3F 0A 84 */ lfs f1, 0xa84(r31)
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lbl_80149360:
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/* 80149360 81 83 0E 3C */ lwz r12, 0xe3c(r3)
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/* 80149364 81 8C 00 C0 */ lwz r12, 0xc0(r12)
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/* 80149368 7D 89 03 A6 */ mtctr r12
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/* 8014936C 4E 80 04 21 */ bctrl
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/* 80149370 C0 22 99 D8 */ lfs f1, lit_4116(r2)
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/* 80149374 D0 3F 0D FC */ stfs f1, 0xdfc(r31)
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/* 80149378 88 1F 0A 88 */ lbz r0, 0xa88(r31)
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/* 8014937C 28 00 00 00 */ cmplwi r0, 0
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/* 80149380 41 82 00 24 */ beq lbl_801493A4
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/* 80149384 80 7F 05 78 */ lwz r3, 0x578(r31)
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/* 80149388 4B EC 67 F5 */ bl setMorf__13mDoExt_morf_cFf
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/* 8014938C C0 22 99 D8 */ lfs f1, lit_4116(r2)
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/* 80149390 D0 3F 0D FC */ stfs f1, 0xdfc(r31)
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/* 80149394 80 7F 05 7C */ lwz r3, 0x57c(r31)
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/* 80149398 28 03 00 00 */ cmplwi r3, 0
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/* 8014939C 41 82 00 08 */ beq lbl_801493A4
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/* 801493A0 4B EC 67 DD */ bl setMorf__13mDoExt_morf_cFf
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lbl_801493A4:
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/* 801493A4 83 E1 00 1C */ lwz r31, 0x1c(r1)
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/* 801493A8 80 01 00 24 */ lwz r0, 0x24(r1)
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/* 801493AC 7C 08 03 A6 */ mtlr r0
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/* 801493B0 38 21 00 20 */ addi r1, r1, 0x20
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/* 801493B4 4E 80 00 20 */ blr
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