mirror of https://github.com/zeldaret/tp.git
144 lines
5.8 KiB
ArmAsm
144 lines
5.8 KiB
ArmAsm
lbl_80270990:
|
|
/* 80270990 94 21 FF A0 */ stwu r1, -0x60(r1)
|
|
/* 80270994 7C 08 02 A6 */ mflr r0
|
|
/* 80270998 90 01 00 64 */ stw r0, 0x64(r1)
|
|
/* 8027099C DB E1 00 50 */ stfd f31, 0x50(r1)
|
|
/* 802709A0 F3 E1 00 58 */ psq_st f31, 88(r1), 0, 0 /* qr0 */
|
|
/* 802709A4 93 E1 00 4C */ stw r31, 0x4c(r1)
|
|
/* 802709A8 93 C1 00 48 */ stw r30, 0x48(r1)
|
|
/* 802709AC 7C 7E 1B 78 */ mr r30, r3
|
|
/* 802709B0 7C 9F 23 78 */ mr r31, r4
|
|
/* 802709B4 FF E0 08 90 */ fmr f31, f1
|
|
/* 802709B8 38 61 00 24 */ addi r3, r1, 0x24
|
|
/* 802709BC 7F C4 F3 78 */ mr r4, r30
|
|
/* 802709C0 7F E5 FB 78 */ mr r5, r31
|
|
/* 802709C4 4B FF 61 71 */ bl __mi__4cXyzCFRC3Vec
|
|
/* 802709C8 C0 41 00 24 */ lfs f2, 0x24(r1)
|
|
/* 802709CC D0 41 00 30 */ stfs f2, 0x30(r1)
|
|
/* 802709D0 C0 01 00 28 */ lfs f0, 0x28(r1)
|
|
/* 802709D4 D0 01 00 34 */ stfs f0, 0x34(r1)
|
|
/* 802709D8 C0 21 00 2C */ lfs f1, 0x2c(r1)
|
|
/* 802709DC D0 21 00 38 */ stfs f1, 0x38(r1)
|
|
/* 802709E0 C0 02 B7 E0 */ lfs f0, lit_2262(r2)
|
|
/* 802709E4 D0 01 00 34 */ stfs f0, 0x34(r1)
|
|
/* 802709E8 D0 41 00 0C */ stfs f2, 0xc(r1)
|
|
/* 802709EC D0 01 00 10 */ stfs f0, 0x10(r1)
|
|
/* 802709F0 D0 21 00 14 */ stfs f1, 0x14(r1)
|
|
/* 802709F4 38 61 00 0C */ addi r3, r1, 0xc
|
|
/* 802709F8 48 0D 67 41 */ bl PSVECSquareMag
|
|
/* 802709FC C0 02 B7 E0 */ lfs f0, lit_2262(r2)
|
|
/* 80270A00 FC 01 00 40 */ fcmpo cr0, f1, f0
|
|
/* 80270A04 40 81 00 58 */ ble lbl_80270A5C
|
|
/* 80270A08 FC 00 08 34 */ frsqrte f0, f1
|
|
/* 80270A0C C8 82 B7 E8 */ lfd f4, lit_2379(r2)
|
|
/* 80270A10 FC 44 00 32 */ fmul f2, f4, f0
|
|
/* 80270A14 C8 62 B7 F0 */ lfd f3, lit_2380(r2)
|
|
/* 80270A18 FC 00 00 32 */ fmul f0, f0, f0
|
|
/* 80270A1C FC 01 00 32 */ fmul f0, f1, f0
|
|
/* 80270A20 FC 03 00 28 */ fsub f0, f3, f0
|
|
/* 80270A24 FC 02 00 32 */ fmul f0, f2, f0
|
|
/* 80270A28 FC 44 00 32 */ fmul f2, f4, f0
|
|
/* 80270A2C FC 00 00 32 */ fmul f0, f0, f0
|
|
/* 80270A30 FC 01 00 32 */ fmul f0, f1, f0
|
|
/* 80270A34 FC 03 00 28 */ fsub f0, f3, f0
|
|
/* 80270A38 FC 02 00 32 */ fmul f0, f2, f0
|
|
/* 80270A3C FC 44 00 32 */ fmul f2, f4, f0
|
|
/* 80270A40 FC 00 00 32 */ fmul f0, f0, f0
|
|
/* 80270A44 FC 01 00 32 */ fmul f0, f1, f0
|
|
/* 80270A48 FC 03 00 28 */ fsub f0, f3, f0
|
|
/* 80270A4C FC 02 00 32 */ fmul f0, f2, f0
|
|
/* 80270A50 FC 21 00 32 */ fmul f1, f1, f0
|
|
/* 80270A54 FC 20 08 18 */ frsp f1, f1
|
|
/* 80270A58 48 00 00 88 */ b lbl_80270AE0
|
|
lbl_80270A5C:
|
|
/* 80270A5C C8 02 B7 F8 */ lfd f0, lit_2381(r2)
|
|
/* 80270A60 FC 01 00 40 */ fcmpo cr0, f1, f0
|
|
/* 80270A64 40 80 00 10 */ bge lbl_80270A74
|
|
/* 80270A68 3C 60 80 45 */ lis r3, __float_nan@ha /* 0x80450AE0@ha */
|
|
/* 80270A6C C0 23 0A E0 */ lfs f1, __float_nan@l(r3) /* 0x80450AE0@l */
|
|
/* 80270A70 48 00 00 70 */ b lbl_80270AE0
|
|
lbl_80270A74:
|
|
/* 80270A74 D0 21 00 08 */ stfs f1, 8(r1)
|
|
/* 80270A78 80 81 00 08 */ lwz r4, 8(r1)
|
|
/* 80270A7C 54 83 00 50 */ rlwinm r3, r4, 0, 1, 8
|
|
/* 80270A80 3C 00 7F 80 */ lis r0, 0x7f80
|
|
/* 80270A84 7C 03 00 00 */ cmpw r3, r0
|
|
/* 80270A88 41 82 00 14 */ beq lbl_80270A9C
|
|
/* 80270A8C 40 80 00 40 */ bge lbl_80270ACC
|
|
/* 80270A90 2C 03 00 00 */ cmpwi r3, 0
|
|
/* 80270A94 41 82 00 20 */ beq lbl_80270AB4
|
|
/* 80270A98 48 00 00 34 */ b lbl_80270ACC
|
|
lbl_80270A9C:
|
|
/* 80270A9C 54 80 02 7F */ clrlwi. r0, r4, 9
|
|
/* 80270AA0 41 82 00 0C */ beq lbl_80270AAC
|
|
/* 80270AA4 38 00 00 01 */ li r0, 1
|
|
/* 80270AA8 48 00 00 28 */ b lbl_80270AD0
|
|
lbl_80270AAC:
|
|
/* 80270AAC 38 00 00 02 */ li r0, 2
|
|
/* 80270AB0 48 00 00 20 */ b lbl_80270AD0
|
|
lbl_80270AB4:
|
|
/* 80270AB4 54 80 02 7F */ clrlwi. r0, r4, 9
|
|
/* 80270AB8 41 82 00 0C */ beq lbl_80270AC4
|
|
/* 80270ABC 38 00 00 05 */ li r0, 5
|
|
/* 80270AC0 48 00 00 10 */ b lbl_80270AD0
|
|
lbl_80270AC4:
|
|
/* 80270AC4 38 00 00 03 */ li r0, 3
|
|
/* 80270AC8 48 00 00 08 */ b lbl_80270AD0
|
|
lbl_80270ACC:
|
|
/* 80270ACC 38 00 00 04 */ li r0, 4
|
|
lbl_80270AD0:
|
|
/* 80270AD0 2C 00 00 01 */ cmpwi r0, 1
|
|
/* 80270AD4 40 82 00 0C */ bne lbl_80270AE0
|
|
/* 80270AD8 3C 60 80 45 */ lis r3, __float_nan@ha /* 0x80450AE0@ha */
|
|
/* 80270ADC C0 23 0A E0 */ lfs f1, __float_nan@l(r3) /* 0x80450AE0@l */
|
|
lbl_80270AE0:
|
|
/* 80270AE0 C0 02 B7 E0 */ lfs f0, lit_2262(r2)
|
|
/* 80270AE4 FC 1F 00 00 */ fcmpu cr0, f31, f0
|
|
/* 80270AE8 41 82 00 68 */ beq lbl_80270B50
|
|
/* 80270AEC FC 00 0A 10 */ fabs f0, f1
|
|
/* 80270AF0 FC 40 00 18 */ frsp f2, f0
|
|
/* 80270AF4 C0 02 B8 00 */ lfs f0, lit_2382(r2)
|
|
/* 80270AF8 FC 02 00 40 */ fcmpo cr0, f2, f0
|
|
/* 80270AFC 41 80 00 10 */ blt lbl_80270B0C
|
|
/* 80270B00 FC 01 F8 40 */ fcmpo cr0, f1, f31
|
|
/* 80270B04 4C 40 13 82 */ cror 2, 0, 2
|
|
/* 80270B08 40 82 00 24 */ bne lbl_80270B2C
|
|
lbl_80270B0C:
|
|
/* 80270B0C C0 1F 00 00 */ lfs f0, 0(r31)
|
|
/* 80270B10 D0 1E 00 00 */ stfs f0, 0(r30)
|
|
/* 80270B14 C0 1F 00 04 */ lfs f0, 4(r31)
|
|
/* 80270B18 D0 1E 00 04 */ stfs f0, 4(r30)
|
|
/* 80270B1C C0 1F 00 08 */ lfs f0, 8(r31)
|
|
/* 80270B20 D0 1E 00 08 */ stfs f0, 8(r30)
|
|
/* 80270B24 38 60 00 01 */ li r3, 1
|
|
/* 80270B28 48 00 00 48 */ b lbl_80270B70
|
|
lbl_80270B2C:
|
|
/* 80270B2C 38 61 00 18 */ addi r3, r1, 0x18
|
|
/* 80270B30 38 81 00 30 */ addi r4, r1, 0x30
|
|
/* 80270B34 EC 3F 08 24 */ fdivs f1, f31, f1
|
|
/* 80270B38 4B FF 60 4D */ bl __ml__4cXyzCFf
|
|
/* 80270B3C 7F C3 F3 78 */ mr r3, r30
|
|
/* 80270B40 38 81 00 18 */ addi r4, r1, 0x18
|
|
/* 80270B44 7F C5 F3 78 */ mr r5, r30
|
|
/* 80270B48 48 0D 65 6D */ bl PSVECSubtract
|
|
/* 80270B4C 48 00 00 20 */ b lbl_80270B6C
|
|
lbl_80270B50:
|
|
/* 80270B50 FC 00 0A 10 */ fabs f0, f1
|
|
/* 80270B54 FC 20 00 18 */ frsp f1, f0
|
|
/* 80270B58 C0 02 B8 00 */ lfs f0, lit_2382(r2)
|
|
/* 80270B5C FC 01 00 40 */ fcmpo cr0, f1, f0
|
|
/* 80270B60 40 80 00 0C */ bge lbl_80270B6C
|
|
/* 80270B64 38 60 00 01 */ li r3, 1
|
|
/* 80270B68 48 00 00 08 */ b lbl_80270B70
|
|
lbl_80270B6C:
|
|
/* 80270B6C 38 60 00 00 */ li r3, 0
|
|
lbl_80270B70:
|
|
/* 80270B70 E3 E1 00 58 */ psq_l f31, 88(r1), 0, 0 /* qr0 */
|
|
/* 80270B74 CB E1 00 50 */ lfd f31, 0x50(r1)
|
|
/* 80270B78 83 E1 00 4C */ lwz r31, 0x4c(r1)
|
|
/* 80270B7C 83 C1 00 48 */ lwz r30, 0x48(r1)
|
|
/* 80270B80 80 01 00 64 */ lwz r0, 0x64(r1)
|
|
/* 80270B84 7C 08 03 A6 */ mtlr r0
|
|
/* 80270B88 38 21 00 60 */ addi r1, r1, 0x60
|
|
/* 80270B8C 4E 80 00 20 */ blr
|