tp/asm/d/d_simple_model/dSmplMdl_modelUpdateDL__FP8...

26 lines
999 B
ArmAsm

lbl_80048C54:
/* 80048C54 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 80048C58 7C 08 02 A6 */ mflr r0
/* 80048C5C 90 01 00 14 */ stw r0, 0x14(r1)
/* 80048C60 93 E1 00 0C */ stw r31, 0xc(r1)
/* 80048C64 7C 7F 1B 78 */ mr r31, r3
/* 80048C68 81 83 00 00 */ lwz r12, 0(r3)
/* 80048C6C 81 8C 00 10 */ lwz r12, 0x10(r12)
/* 80048C70 7D 89 03 A6 */ mtctr r12
/* 80048C74 4E 80 04 21 */ bctrl
/* 80048C78 7F E3 FB 78 */ mr r3, r31
/* 80048C7C 81 9F 00 00 */ lwz r12, 0(r31)
/* 80048C80 81 8C 00 0C */ lwz r12, 0xc(r12)
/* 80048C84 7D 89 03 A6 */ mtctr r12
/* 80048C88 4E 80 04 21 */ bctrl
/* 80048C8C 7F E3 FB 78 */ mr r3, r31
/* 80048C90 81 9F 00 00 */ lwz r12, 0(r31)
/* 80048C94 81 8C 00 1C */ lwz r12, 0x1c(r12)
/* 80048C98 7D 89 03 A6 */ mtctr r12
/* 80048C9C 4E 80 04 21 */ bctrl
/* 80048CA0 83 E1 00 0C */ lwz r31, 0xc(r1)
/* 80048CA4 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80048CA8 7C 08 03 A6 */ mtlr r0
/* 80048CAC 38 21 00 10 */ addi r1, r1, 0x10
/* 80048CB0 4E 80 00 20 */ blr