mirror of https://github.com/zeldaret/tp.git
392 lines
16 KiB
ArmAsm
392 lines
16 KiB
ArmAsm
lbl_80356364:
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/* 80356364 7C 08 02 A6 */ mflr r0
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/* 80356368 90 01 00 04 */ stw r0, 4(r1)
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/* 8035636C 94 21 FF A8 */ stwu r1, -0x58(r1)
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/* 80356370 BF 21 00 3C */ stmw r25, 0x3c(r1)
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/* 80356374 7C 9A 23 79 */ or. r26, r4, r4
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/* 80356378 3B 23 00 00 */ addi r25, r3, 0
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/* 8035637C 3B 65 00 00 */ addi r27, r5, 0
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/* 80356380 3B C0 00 00 */ li r30, 0
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/* 80356384 3B A0 00 00 */ li r29, 0
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/* 80356388 3B 80 00 00 */ li r28, 0
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/* 8035638C 41 82 00 0C */ beq lbl_80356398
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/* 80356390 38 00 00 00 */ li r0, 0
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/* 80356394 90 1A 00 00 */ stw r0, 0(r26)
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lbl_80356398:
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/* 80356398 38 79 00 00 */ addi r3, r25, 0
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/* 8035639C 38 81 00 30 */ addi r4, r1, 0x30
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/* 803563A0 4B FF D8 15 */ bl __CARDGetControlBlock
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/* 803563A4 2C 03 00 00 */ cmpwi r3, 0
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/* 803563A8 40 80 00 08 */ bge lbl_803563B0
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/* 803563AC 48 00 05 34 */ b lbl_803568E0
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lbl_803563B0:
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/* 803563B0 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803563B4 4B FF F7 DD */ bl VerifyID
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/* 803563B8 7C 64 1B 79 */ or. r4, r3, r3
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/* 803563BC 40 80 00 10 */ bge lbl_803563CC
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/* 803563C0 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803563C4 4B FF D8 A9 */ bl __CARDPutControlBlock
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/* 803563C8 48 00 05 18 */ b lbl_803568E0
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lbl_803563CC:
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/* 803563CC 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803563D0 38 81 00 18 */ addi r4, r1, 0x18
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/* 803563D4 4B FF FA 41 */ bl VerifyDir
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/* 803563D8 7C 7F 1B 78 */ mr r31, r3
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/* 803563DC 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803563E0 38 81 00 1C */ addi r4, r1, 0x1c
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/* 803563E4 4B FF FC 71 */ bl VerifyFAT
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/* 803563E8 7C BF 1A 14 */ add r5, r31, r3
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/* 803563EC 2C 05 00 01 */ cmpwi r5, 1
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/* 803563F0 40 81 00 14 */ ble lbl_80356404
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/* 803563F4 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803563F8 38 80 FF FA */ li r4, -6
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/* 803563FC 4B FF D8 71 */ bl __CARDPutControlBlock
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/* 80356400 48 00 04 E0 */ b lbl_803568E0
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lbl_80356404:
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/* 80356404 80 C1 00 30 */ lwz r6, 0x30(r1)
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/* 80356408 80 86 00 80 */ lwz r4, 0x80(r6)
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/* 8035640C 38 64 20 00 */ addi r3, r4, 0x2000
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/* 80356410 38 04 60 00 */ addi r0, r4, 0x6000
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/* 80356414 90 61 00 28 */ stw r3, 0x28(r1)
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/* 80356418 3C 64 00 01 */ addis r3, r4, 1
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/* 8035641C 38 84 40 00 */ addi r4, r4, 0x4000
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/* 80356420 90 01 00 20 */ stw r0, 0x20(r1)
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/* 80356424 38 03 80 00 */ addi r0, r3, -32768
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/* 80356428 90 81 00 2C */ stw r4, 0x2c(r1)
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/* 8035642C 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80356430 41 82 00 0C */ beq lbl_8035643C
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/* 80356434 40 80 00 8C */ bge lbl_803564C0
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/* 80356438 48 00 00 88 */ b lbl_803564C0
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lbl_8035643C:
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/* 8035643C 38 66 00 84 */ addi r3, r6, 0x84
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/* 80356440 80 06 00 84 */ lwz r0, 0x84(r6)
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/* 80356444 28 00 00 00 */ cmplwi r0, 0
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/* 80356448 40 82 00 40 */ bne lbl_80356488
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/* 8035644C 80 01 00 18 */ lwz r0, 0x18(r1)
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/* 80356450 38 81 00 28 */ addi r4, r1, 0x28
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/* 80356454 38 A0 20 00 */ li r5, 0x2000
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/* 80356458 54 00 10 3A */ slwi r0, r0, 2
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/* 8035645C 7C 04 00 2E */ lwzx r0, r4, r0
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/* 80356460 90 03 00 00 */ stw r0, 0(r3)
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/* 80356464 80 61 00 18 */ lwz r3, 0x18(r1)
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/* 80356468 68 60 00 01 */ xori r0, r3, 1
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/* 8035646C 54 63 10 3A */ slwi r3, r3, 2
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/* 80356470 54 00 10 3A */ slwi r0, r0, 2
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/* 80356474 7C 64 18 2E */ lwzx r3, r4, r3
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/* 80356478 7C 84 00 2E */ lwzx r4, r4, r0
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/* 8035647C 4B CA D0 C5 */ bl memcpy
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/* 80356480 3B A0 00 01 */ li r29, 1
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/* 80356484 48 00 00 3C */ b lbl_803564C0
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lbl_80356488:
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/* 80356488 80 01 00 1C */ lwz r0, 0x1c(r1)
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/* 8035648C 38 81 00 20 */ addi r4, r1, 0x20
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/* 80356490 38 A0 20 00 */ li r5, 0x2000
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/* 80356494 54 00 10 3A */ slwi r0, r0, 2
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/* 80356498 7C 04 00 2E */ lwzx r0, r4, r0
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/* 8035649C 90 06 00 88 */ stw r0, 0x88(r6)
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/* 803564A0 80 61 00 1C */ lwz r3, 0x1c(r1)
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/* 803564A4 68 60 00 01 */ xori r0, r3, 1
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/* 803564A8 54 63 10 3A */ slwi r3, r3, 2
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/* 803564AC 54 00 10 3A */ slwi r0, r0, 2
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/* 803564B0 7C 64 18 2E */ lwzx r3, r4, r3
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/* 803564B4 7C 84 00 2E */ lwzx r4, r4, r0
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/* 803564B8 4B CA D0 89 */ bl memcpy
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/* 803564BC 3B C0 00 01 */ li r30, 1
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lbl_803564C0:
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/* 803564C0 80 01 00 1C */ lwz r0, 0x1c(r1)
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/* 803564C4 38 61 00 20 */ addi r3, r1, 0x20
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/* 803564C8 38 80 00 00 */ li r4, 0
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/* 803564CC 68 00 00 01 */ xori r0, r0, 1
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/* 803564D0 54 00 10 3A */ slwi r0, r0, 2
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/* 803564D4 7F E3 00 2E */ lwzx r31, r3, r0
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/* 803564D8 38 A0 20 00 */ li r5, 0x2000
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/* 803564DC 38 7F 00 00 */ addi r3, r31, 0
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/* 803564E0 4B CA CF 79 */ bl memset
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/* 803564E4 38 00 00 7F */ li r0, 0x7f
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/* 803564E8 80 A1 00 30 */ lwz r5, 0x30(r1)
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/* 803564EC 7C 09 03 A6 */ mtctr r0
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/* 803564F0 38 C0 00 00 */ li r6, 0
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lbl_803564F4:
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/* 803564F4 80 05 00 84 */ lwz r0, 0x84(r5)
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/* 803564F8 7C E0 32 14 */ add r7, r0, r6
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/* 803564FC 88 07 00 00 */ lbz r0, 0(r7)
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/* 80356500 28 00 00 FF */ cmplwi r0, 0xff
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/* 80356504 41 82 00 A8 */ beq lbl_803565AC
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/* 80356508 A0 87 00 36 */ lhz r4, 0x36(r7)
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/* 8035650C 39 00 00 00 */ li r8, 0
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/* 80356510 48 00 00 54 */ b lbl_80356564
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lbl_80356514:
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/* 80356514 54 83 04 3E */ clrlwi r3, r4, 0x10
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/* 80356518 28 03 00 05 */ cmplwi r3, 5
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/* 8035651C 41 80 00 2C */ blt lbl_80356548
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/* 80356520 A0 05 00 10 */ lhz r0, 0x10(r5)
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/* 80356524 7C 03 00 40 */ cmplw r3, r0
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/* 80356528 40 80 00 20 */ bge lbl_80356548
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/* 8035652C 54 64 08 3C */ slwi r4, r3, 1
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/* 80356530 7C 7F 22 2E */ lhzx r3, r31, r4
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/* 80356534 38 63 00 01 */ addi r3, r3, 1
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/* 80356538 54 60 04 3E */ clrlwi r0, r3, 0x10
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/* 8035653C 7C 7F 23 2E */ sthx r3, r31, r4
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/* 80356540 28 00 00 01 */ cmplwi r0, 1
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/* 80356544 40 81 00 14 */ ble lbl_80356558
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lbl_80356548:
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/* 80356548 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 8035654C 38 80 FF FA */ li r4, -6
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/* 80356550 4B FF D7 1D */ bl __CARDPutControlBlock
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/* 80356554 48 00 03 8C */ b lbl_803568E0
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lbl_80356558:
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/* 80356558 80 65 00 88 */ lwz r3, 0x88(r5)
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/* 8035655C 39 08 00 01 */ addi r8, r8, 1
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/* 80356560 7C 83 22 2E */ lhzx r4, r3, r4
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lbl_80356564:
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/* 80356564 54 80 04 3E */ clrlwi r0, r4, 0x10
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/* 80356568 28 00 FF FF */ cmplwi r0, 0xffff
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/* 8035656C 41 82 00 14 */ beq lbl_80356580
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/* 80356570 A0 07 00 38 */ lhz r0, 0x38(r7)
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/* 80356574 55 03 04 3E */ clrlwi r3, r8, 0x10
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/* 80356578 7C 03 00 40 */ cmplw r3, r0
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/* 8035657C 41 80 FF 98 */ blt lbl_80356514
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lbl_80356580:
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/* 80356580 A0 07 00 38 */ lhz r0, 0x38(r7)
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/* 80356584 55 03 04 3E */ clrlwi r3, r8, 0x10
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/* 80356588 7C 03 00 40 */ cmplw r3, r0
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/* 8035658C 40 82 00 10 */ bne lbl_8035659C
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/* 80356590 54 80 04 3E */ clrlwi r0, r4, 0x10
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/* 80356594 28 00 FF FF */ cmplwi r0, 0xffff
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/* 80356598 41 82 00 14 */ beq lbl_803565AC
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lbl_8035659C:
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/* 8035659C 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803565A0 38 80 FF FA */ li r4, -6
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/* 803565A4 4B FF D6 C9 */ bl __CARDPutControlBlock
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/* 803565A8 48 00 03 38 */ b lbl_803568E0
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lbl_803565AC:
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/* 803565AC 38 C6 00 40 */ addi r6, r6, 0x40
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/* 803565B0 42 00 FF 44 */ bdnz lbl_803564F4
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/* 803565B4 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 803565B8 38 DF 00 0A */ addi r6, r31, 0xa
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/* 803565BC 39 20 00 00 */ li r9, 0
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/* 803565C0 39 00 00 05 */ li r8, 5
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/* 803565C4 38 A0 00 0A */ li r5, 0xa
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/* 803565C8 48 00 00 68 */ b lbl_80356630
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lbl_803565CC:
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/* 803565CC 80 83 00 88 */ lwz r4, 0x88(r3)
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/* 803565D0 A0 06 00 00 */ lhz r0, 0(r6)
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/* 803565D4 7C 84 2A 14 */ add r4, r4, r5
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/* 803565D8 28 00 00 00 */ cmplwi r0, 0
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/* 803565DC A0 04 00 00 */ lhz r0, 0(r4)
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/* 803565E0 40 82 00 20 */ bne lbl_80356600
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/* 803565E4 28 00 00 00 */ cmplwi r0, 0
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/* 803565E8 41 82 00 10 */ beq lbl_803565F8
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/* 803565EC 38 00 00 00 */ li r0, 0
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/* 803565F0 B0 04 00 00 */ sth r0, 0(r4)
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/* 803565F4 3B 80 00 01 */ li r28, 1
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lbl_803565F8:
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/* 803565F8 39 29 00 01 */ addi r9, r9, 1
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/* 803565FC 48 00 00 28 */ b lbl_80356624
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lbl_80356600:
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/* 80356600 28 00 00 05 */ cmplwi r0, 5
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/* 80356604 41 80 00 0C */ blt lbl_80356610
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/* 80356608 7C 00 38 40 */ cmplw r0, r7
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/* 8035660C 41 80 00 18 */ blt lbl_80356624
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lbl_80356610:
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/* 80356610 28 00 FF FF */ cmplwi r0, 0xffff
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/* 80356614 41 82 00 10 */ beq lbl_80356624
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/* 80356618 38 80 FF FA */ li r4, -6
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/* 8035661C 4B FF D6 51 */ bl __CARDPutControlBlock
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/* 80356620 48 00 02 C0 */ b lbl_803568E0
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lbl_80356624:
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/* 80356624 38 A5 00 02 */ addi r5, r5, 2
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/* 80356628 38 C6 00 02 */ addi r6, r6, 2
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/* 8035662C 39 08 00 01 */ addi r8, r8, 1
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lbl_80356630:
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/* 80356630 A0 E3 00 10 */ lhz r7, 0x10(r3)
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/* 80356634 55 00 04 3E */ clrlwi r0, r8, 0x10
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/* 80356638 7C 00 38 40 */ cmplw r0, r7
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/* 8035663C 41 80 FF 90 */ blt lbl_803565CC
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/* 80356640 80 63 00 88 */ lwz r3, 0x88(r3)
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/* 80356644 55 24 04 3E */ clrlwi r4, r9, 0x10
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/* 80356648 A4 03 00 06 */ lhzu r0, 6(r3)
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/* 8035664C 7C 04 00 40 */ cmplw r4, r0
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/* 80356650 41 82 00 0C */ beq lbl_8035665C
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/* 80356654 B1 23 00 00 */ sth r9, 0(r3)
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/* 80356658 3B 80 00 01 */ li r28, 1
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lbl_8035665C:
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/* 8035665C 2C 1C 00 00 */ cmpwi r28, 0
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/* 80356660 41 82 01 C8 */ beq lbl_80356828
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/* 80356664 80 61 00 30 */ lwz r3, 0x30(r1)
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/* 80356668 38 80 1F FC */ li r4, 0x1ffc
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/* 8035666C 7C 84 0E 70 */ srawi r4, r4, 1
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/* 80356670 80 C3 00 88 */ lwz r6, 0x88(r3)
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/* 80356674 38 00 00 00 */ li r0, 0
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/* 80356678 7C 84 01 95 */ addze. r4, r4
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/* 8035667C B0 06 00 02 */ sth r0, 2(r6)
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/* 80356680 38 E6 00 02 */ addi r7, r6, 2
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/* 80356684 38 A6 00 04 */ addi r5, r6, 4
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/* 80356688 B0 06 00 00 */ sth r0, 0(r6)
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/* 8035668C 38 64 00 00 */ addi r3, r4, 0
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/* 80356690 40 81 01 70 */ ble lbl_80356800
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/* 80356694 54 60 E8 FF */ rlwinm. r0, r3, 0x1d, 3, 0x1f
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/* 80356698 7C 09 03 A6 */ mtctr r0
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/* 8035669C 41 82 01 34 */ beq lbl_803567D0
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lbl_803566A0:
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/* 803566A0 A0 86 00 00 */ lhz r4, 0(r6)
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/* 803566A4 A0 05 00 00 */ lhz r0, 0(r5)
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/* 803566A8 7C 04 02 14 */ add r0, r4, r0
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/* 803566AC B0 06 00 00 */ sth r0, 0(r6)
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/* 803566B0 A0 05 00 00 */ lhz r0, 0(r5)
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/* 803566B4 A0 87 00 00 */ lhz r4, 0(r7)
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/* 803566B8 7C 00 00 F8 */ nor r0, r0, r0
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/* 803566BC 7C 04 02 14 */ add r0, r4, r0
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/* 803566C0 B0 07 00 00 */ sth r0, 0(r7)
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/* 803566C4 A0 86 00 00 */ lhz r4, 0(r6)
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/* 803566C8 A0 05 00 02 */ lhz r0, 2(r5)
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/* 803566CC 7C 04 02 14 */ add r0, r4, r0
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/* 803566D0 B0 06 00 00 */ sth r0, 0(r6)
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/* 803566D4 A0 05 00 02 */ lhz r0, 2(r5)
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/* 803566D8 A0 87 00 00 */ lhz r4, 0(r7)
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/* 803566DC 7C 00 00 F8 */ nor r0, r0, r0
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/* 803566E0 7C 04 02 14 */ add r0, r4, r0
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/* 803566E4 B0 07 00 00 */ sth r0, 0(r7)
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/* 803566E8 A0 86 00 00 */ lhz r4, 0(r6)
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/* 803566EC A0 05 00 04 */ lhz r0, 4(r5)
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/* 803566F0 7C 04 02 14 */ add r0, r4, r0
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/* 803566F4 B0 06 00 00 */ sth r0, 0(r6)
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/* 803566F8 A0 05 00 04 */ lhz r0, 4(r5)
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/* 803566FC A0 87 00 00 */ lhz r4, 0(r7)
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/* 80356700 7C 00 00 F8 */ nor r0, r0, r0
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/* 80356704 7C 04 02 14 */ add r0, r4, r0
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/* 80356708 B0 07 00 00 */ sth r0, 0(r7)
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/* 8035670C A0 86 00 00 */ lhz r4, 0(r6)
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/* 80356710 A0 05 00 06 */ lhz r0, 6(r5)
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/* 80356714 7C 04 02 14 */ add r0, r4, r0
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/* 80356718 B0 06 00 00 */ sth r0, 0(r6)
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/* 8035671C A0 05 00 06 */ lhz r0, 6(r5)
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/* 80356720 A0 87 00 00 */ lhz r4, 0(r7)
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/* 80356724 7C 00 00 F8 */ nor r0, r0, r0
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/* 80356728 7C 04 02 14 */ add r0, r4, r0
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/* 8035672C B0 07 00 00 */ sth r0, 0(r7)
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/* 80356730 A0 86 00 00 */ lhz r4, 0(r6)
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/* 80356734 A0 05 00 08 */ lhz r0, 8(r5)
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/* 80356738 7C 04 02 14 */ add r0, r4, r0
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/* 8035673C B0 06 00 00 */ sth r0, 0(r6)
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/* 80356740 A0 05 00 08 */ lhz r0, 8(r5)
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/* 80356744 A0 87 00 00 */ lhz r4, 0(r7)
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/* 80356748 7C 00 00 F8 */ nor r0, r0, r0
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/* 8035674C 7C 04 02 14 */ add r0, r4, r0
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/* 80356750 B0 07 00 00 */ sth r0, 0(r7)
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/* 80356754 A0 86 00 00 */ lhz r4, 0(r6)
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/* 80356758 A0 05 00 0A */ lhz r0, 0xa(r5)
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/* 8035675C 7C 04 02 14 */ add r0, r4, r0
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/* 80356760 B0 06 00 00 */ sth r0, 0(r6)
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/* 80356764 A0 05 00 0A */ lhz r0, 0xa(r5)
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/* 80356768 A0 87 00 00 */ lhz r4, 0(r7)
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/* 8035676C 7C 00 00 F8 */ nor r0, r0, r0
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/* 80356770 7C 04 02 14 */ add r0, r4, r0
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/* 80356774 B0 07 00 00 */ sth r0, 0(r7)
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/* 80356778 A0 86 00 00 */ lhz r4, 0(r6)
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/* 8035677C A0 05 00 0C */ lhz r0, 0xc(r5)
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/* 80356780 7C 04 02 14 */ add r0, r4, r0
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/* 80356784 B0 06 00 00 */ sth r0, 0(r6)
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/* 80356788 A0 05 00 0C */ lhz r0, 0xc(r5)
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/* 8035678C A0 87 00 00 */ lhz r4, 0(r7)
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/* 80356790 7C 00 00 F8 */ nor r0, r0, r0
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/* 80356794 7C 04 02 14 */ add r0, r4, r0
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/* 80356798 B0 07 00 00 */ sth r0, 0(r7)
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/* 8035679C A0 86 00 00 */ lhz r4, 0(r6)
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/* 803567A0 A0 05 00 0E */ lhz r0, 0xe(r5)
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/* 803567A4 7C 04 02 14 */ add r0, r4, r0
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/* 803567A8 B0 06 00 00 */ sth r0, 0(r6)
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/* 803567AC A0 05 00 0E */ lhz r0, 0xe(r5)
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/* 803567B0 38 A5 00 10 */ addi r5, r5, 0x10
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/* 803567B4 A0 87 00 00 */ lhz r4, 0(r7)
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/* 803567B8 7C 00 00 F8 */ nor r0, r0, r0
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/* 803567BC 7C 04 02 14 */ add r0, r4, r0
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/* 803567C0 B0 07 00 00 */ sth r0, 0(r7)
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/* 803567C4 42 00 FE DC */ bdnz lbl_803566A0
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/* 803567C8 70 63 00 07 */ andi. r3, r3, 7
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/* 803567CC 41 82 00 34 */ beq lbl_80356800
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lbl_803567D0:
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/* 803567D0 7C 69 03 A6 */ mtctr r3
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lbl_803567D4:
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/* 803567D4 A0 86 00 00 */ lhz r4, 0(r6)
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/* 803567D8 A0 05 00 00 */ lhz r0, 0(r5)
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/* 803567DC 7C 04 02 14 */ add r0, r4, r0
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/* 803567E0 B0 06 00 00 */ sth r0, 0(r6)
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/* 803567E4 A0 05 00 00 */ lhz r0, 0(r5)
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/* 803567E8 38 A5 00 02 */ addi r5, r5, 2
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/* 803567EC A0 87 00 00 */ lhz r4, 0(r7)
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/* 803567F0 7C 00 00 F8 */ nor r0, r0, r0
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/* 803567F4 7C 04 02 14 */ add r0, r4, r0
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/* 803567F8 B0 07 00 00 */ sth r0, 0(r7)
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|
/* 803567FC 42 00 FF D8 */ bdnz lbl_803567D4
|
|
lbl_80356800:
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|
/* 80356800 A0 06 00 00 */ lhz r0, 0(r6)
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|
/* 80356804 28 00 FF FF */ cmplwi r0, 0xffff
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|
/* 80356808 40 82 00 0C */ bne lbl_80356814
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/* 8035680C 38 00 00 00 */ li r0, 0
|
|
/* 80356810 B0 06 00 00 */ sth r0, 0(r6)
|
|
lbl_80356814:
|
|
/* 80356814 A0 07 00 00 */ lhz r0, 0(r7)
|
|
/* 80356818 28 00 FF FF */ cmplwi r0, 0xffff
|
|
/* 8035681C 40 82 00 0C */ bne lbl_80356828
|
|
/* 80356820 38 00 00 00 */ li r0, 0
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|
/* 80356824 B0 07 00 00 */ sth r0, 0(r7)
|
|
lbl_80356828:
|
|
/* 80356828 80 C1 00 1C */ lwz r6, 0x1c(r1)
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|
/* 8035682C 38 81 00 20 */ addi r4, r1, 0x20
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|
/* 80356830 38 A0 20 00 */ li r5, 0x2000
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|
/* 80356834 68 C0 00 01 */ xori r0, r6, 1
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|
/* 80356838 54 03 10 3A */ slwi r3, r0, 2
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|
/* 8035683C 54 C0 10 3A */ slwi r0, r6, 2
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|
/* 80356840 7C 64 18 2E */ lwzx r3, r4, r3
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|
/* 80356844 7C 84 00 2E */ lwzx r4, r4, r0
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|
/* 80356848 4B CA CC F9 */ bl memcpy
|
|
/* 8035684C 2C 1D 00 00 */ cmpwi r29, 0
|
|
/* 80356850 41 82 00 24 */ beq lbl_80356874
|
|
/* 80356854 28 1A 00 00 */ cmplwi r26, 0
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|
/* 80356858 41 82 00 0C */ beq lbl_80356864
|
|
/* 8035685C 38 00 20 00 */ li r0, 0x2000
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|
/* 80356860 90 1A 00 00 */ stw r0, 0(r26)
|
|
lbl_80356864:
|
|
/* 80356864 38 79 00 00 */ addi r3, r25, 0
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|
/* 80356868 38 9B 00 00 */ addi r4, r27, 0
|
|
/* 8035686C 4B FF F0 B1 */ bl __CARDUpdateDir
|
|
/* 80356870 48 00 00 70 */ b lbl_803568E0
|
|
lbl_80356874:
|
|
/* 80356874 7F C0 E3 79 */ or. r0, r30, r28
|
|
/* 80356878 41 82 00 2C */ beq lbl_803568A4
|
|
/* 8035687C 28 1A 00 00 */ cmplwi r26, 0
|
|
/* 80356880 41 82 00 0C */ beq lbl_8035688C
|
|
/* 80356884 38 00 20 00 */ li r0, 0x2000
|
|
/* 80356888 90 1A 00 00 */ stw r0, 0(r26)
|
|
lbl_8035688C:
|
|
/* 8035688C 80 81 00 30 */ lwz r4, 0x30(r1)
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|
/* 80356890 38 79 00 00 */ addi r3, r25, 0
|
|
/* 80356894 38 BB 00 00 */ addi r5, r27, 0
|
|
/* 80356898 80 84 00 88 */ lwz r4, 0x88(r4)
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|
/* 8035689C 4B FF EE 35 */ bl __CARDUpdateFatBlock
|
|
/* 803568A0 48 00 00 40 */ b lbl_803568E0
|
|
lbl_803568A4:
|
|
/* 803568A4 80 61 00 30 */ lwz r3, 0x30(r1)
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|
/* 803568A8 38 80 00 00 */ li r4, 0
|
|
/* 803568AC 4B FF D3 C1 */ bl __CARDPutControlBlock
|
|
/* 803568B0 28 1B 00 00 */ cmplwi r27, 0
|
|
/* 803568B4 41 82 00 28 */ beq lbl_803568DC
|
|
/* 803568B8 4B FE 6E 3D */ bl OSDisableInterrupts
|
|
/* 803568BC 39 9B 00 00 */ addi r12, r27, 0
|
|
/* 803568C0 7D 88 03 A6 */ mtlr r12
|
|
/* 803568C4 3B 43 00 00 */ addi r26, r3, 0
|
|
/* 803568C8 38 79 00 00 */ addi r3, r25, 0
|
|
/* 803568CC 38 80 00 00 */ li r4, 0
|
|
/* 803568D0 4E 80 00 21 */ blrl
|
|
/* 803568D4 7F 43 D3 78 */ mr r3, r26
|
|
/* 803568D8 4B FE 6E 45 */ bl OSRestoreInterrupts
|
|
lbl_803568DC:
|
|
/* 803568DC 38 60 00 00 */ li r3, 0
|
|
lbl_803568E0:
|
|
/* 803568E0 BB 21 00 3C */ lmw r25, 0x3c(r1)
|
|
/* 803568E4 80 01 00 5C */ lwz r0, 0x5c(r1)
|
|
/* 803568E8 38 21 00 58 */ addi r1, r1, 0x58
|
|
/* 803568EC 7C 08 03 A6 */ mtlr r0
|
|
/* 803568F0 4E 80 00 20 */ blr
|