diff --git a/cores/NES/CORE19.ZX1 b/cores/NES/CORE19.ZX1
index 650b501..0acbc1a 100644
Binary files a/cores/NES/CORE19.ZX1 and b/cores/NES/CORE19.ZX1 differ
diff --git a/cores/NES/src/GameLoader.v b/cores/NES/src/GameLoader.v
index 2a17736..46add8a 100644
--- a/cores/NES/src/GameLoader.v
+++ b/cores/NES/src/GameLoader.v
@@ -1,23 +1,23 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 10:26:48 02/11/2016
-// Design Name:
-// Module Name: GameLoader
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 10:26:48 02/11/2016
+// Design Name:
+// Module Name: GameLoader
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
// Module reads bytes and writes to proper address in ram.
// Done is asserted when the whole game is loaded.
// This parses iNES headers too.
@@ -108,4 +108,4 @@ module GameLoader(input clk, input reset,
endcase
end
end
-endmodule
+endmodule
diff --git a/cores/NES/src/NES_ZXUNO.v b/cores/NES/src/NES_ZXUNO.v
index f52aa48..6feaace 100644
--- a/cores/NES/src/NES_ZXUNO.v
+++ b/cores/NES/src/NES_ZXUNO.v
@@ -1,27 +1,22 @@
-// ZXUNO port by DistWave (2016)
+// ZXUNO port by DistWave (2016)
+// Modifications by Quest
// fpganes
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
-`timescale 1ns / 1ps
-
+`timescale 1ns / 1ps
+
module NES_ZXUNO(
input CLOCK_50,
// VGA
- output vga_v,
- output vga_h,
- output [2:0] vga_r,
- output [2:0] vga_g,
- output [2:0] vga_b,
- output dvga_v,
- output dvga_h,
- output [2:0] dvga_r,
- output [2:0] dvga_g,
- output [2:0] dvga_b,
+ output vga_v, output vga_h, output [2:0] vga_r, output [2:0] vga_g, output [2:0] vga_b,
// Memory
output ram_WE_n, // Write Enable. WRITE when Low.
- output [18:0] ram_a,
- inout [7:0] ram_d,
+ output [20:0] ram_a,
+ inout [7:0] ram_d,
+// output ext_ram_WE_n,
+// output [20:0] ext_ram_a,
+// inout [7:0] ext_ram_d,
output AUDIO_R,
output AUDIO_L,
input P_A,
@@ -29,7 +24,16 @@ module NES_ZXUNO(
input P_U,
input P_D,
input P_L,
- input P_R,
+ input P_R,
+ output P_Fire3,
+ input P2_A,
+ input P2_tr,
+ input P2_U,
+ input P2_D,
+ input P2_L,
+ input P2_R,
+ input SW1,
+ input SW2,
input PS2_CLK,
input PS2_DAT,
input SPI_MISO,
@@ -38,10 +42,14 @@ module NES_ZXUNO(
output SPI_CS,
output led//,
//input reset,
-//input set,
-//output [6:0] sseg_a_to_dp, // cathode of seven segment display( a,b,c,d,e,f,g,dp )
+//input set,
+//output [6:0] sseg_a_to_dp, // cathode of seven segment display( a,b,c,d,e,f,g,dp )
//output [3:0] sseg_an // anaode of seven segment display( AN3,AN2,AN1,AN0 )
- );
+ );
+
+// Parametro tipos de joys segun placa (param: joyType):
+// 0 = un joy, 1 = joySplitter
+parameter joyType = 1;
wire osd_window;
wire osd_pixel;
@@ -55,17 +63,17 @@ module NES_ZXUNO(
wire host_reset_n;
wire host_reset_loader;
- wire host_divert_sdcard;
- wire host_divert_keyboard;
+ wire host_divert_sdcard;
+ wire host_divert_keyboard;
wire host_select;
- wire host_start;
-
+ wire host_start;
+
wire master_reset;
reg boot_state = 1'b0;
-
- wire [31:0] bootdata;
- wire bootdata_req;
+
+ wire [31:0] bootdata;
+ wire bootdata_req;
reg bootdata_ack = 1'b0;
wire AUD_MCLK;
@@ -88,12 +96,6 @@ module NES_ZXUNO(
assign vga_g = vga_osd_g[7:5];
assign vga_b = vga_osd_b[7:5];
- assign dvga_h = vga_hsync;
- assign dvga_v = vga_vsync;
- assign dvga_r = vga_osd_r[7:5];
- assign dvga_g = vga_osd_g[7:5];
- assign dvga_b = vga_osd_b[7:5];
-
assign led = loader_fail;
wire clock_locked;
@@ -108,12 +110,12 @@ module NES_ZXUNO(
wire joypad_data;
- nes_clk clock_21mhz(
- .CLK_IN1(CLOCK_50),
- .CLK_OUT1(clk),
- .CLK_OUT2(clk_ctrl),
- /*.CLK_OUT3(clk4),*/
- .LOCKED(clock_locked)
+ nes_clk clock_21mhz(
+ .CLK_IN1(CLOCK_50),
+ .CLK_OUT1(clk),
+ .CLK_OUT2(clk_ctrl),
+ /*.CLK_OUT3(clk4),*/
+ .LOCKED(clock_locked)
);
// NES Palette -> RGB332 conversion
@@ -143,18 +145,44 @@ module NES_ZXUNO(
wire [7:0] joystick1, joystick2;
wire p_sel = !host_select;
- wire p_start = !host_start;
- assign joystick1 = {~P_R & P_L, ~P_L & P_R, ~P_D & P_U, ~P_U & P_D, ~p_start | (~P_R & ~P_L), ~p_sel | (~P_D & ~P_U), ~P_tr, ~P_A};
+ wire p_start = !host_start;
+
+ reg P_f3;
+ reg [7:0] joy1, joy2;
+
+
+generate //generar segun joyType
+ if (joyType == 1) begin
+ assign P_Fire3 = P_f3;
+ always @(posedge clk_ctrl) begin //2joysplit
+ if (P_f3)
+ joy1 <= {~P_R, ~P_L, ~P_D, ~P_U, ~p_start, ~p_sel, ~P_tr, ~P_A};
+ else
+ joy2 <= {~P_R, ~P_L, ~P_D, ~P_U, ~p_start, ~p_sel, ~P_tr, ~P_A};
+ end
+ assign joystick1 = joy1;
+ assign joystick2 = joy2;
+ end else begin
+ assign joystick1 = {~P_R, ~P_L, ~P_D, ~P_U, ~p_start, ~p_sel, ~P_tr, ~P_A};
+ assign joystick2 = 8'b00000000;
+ assign P_Fire3 = 1'b1;
+ end
+endgenerate
+
always @(posedge clk) begin
if (joypad_strobe) begin
joypad_bits <= joystick1;
joypad_bits2 <= joystick2;
end
- if (!joypad_clock[0] && last_joypad_clock[0])
- joypad_bits <= {1'b0, joypad_bits[7:1]};
- if (!joypad_clock[1] && last_joypad_clock[1])
- joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
+ if (!joypad_clock[0] && last_joypad_clock[0]) begin
+ P_f3 <= 1'b0;
+ joypad_bits <= {1'b0, joypad_bits[7:1]};
+ end
+ if (!joypad_clock[1] && last_joypad_clock[1]) begin
+ P_f3 <= 1'b1;
+ joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
+ end
last_joypad_clock <= joypad_clock;
end
@@ -164,19 +192,19 @@ module NES_ZXUNO(
wire loader_write;
wire [31:0] mapper_flags;
wire loader_done, loader_fail;
- wire empty_fifo;
+ wire empty_fifo;
- GameLoader loader(
- clk_gameloader,
- loader_reset,
- loader_input,
- clk_loader,
- loader_addr,
- loader_write_data,
- loader_write,
- mapper_flags,
- loader_done,
- loader_fail
+ GameLoader loader(
+ clk_gameloader,
+ loader_reset,
+ loader_input,
+ clk_loader,
+ loader_addr,
+ loader_write_data,
+ loader_write,
+ mapper_flags,
+ loader_done,
+ loader_fail
);
wire reset_nes = (!host_reset_n || !loader_done);
@@ -199,27 +227,22 @@ module NES_ZXUNO(
memory_write, memory_dout,
cycle, scanline,
dbgadr,
- dbgctr
+ dbgctr
);
// This is the memory controller to access the board's SRAM
- wire ram_busy;
-
- MemoryController memory(clk,
- memory_read_cpu && run_mem,
- memory_read_ppu && run_mem,
- memory_write && run_mem || loader_write,
- loader_write ? loader_addr : memory_addr,
- loader_write ? loader_write_data : memory_dout,
- memory_din_cpu,
- memory_din_ppu,
- ram_busy,
- ram_WE_n,
- ram_a,
- ram_d,
- debugaddr,
- debugdata);
-
+ wire ram_busy;
+
+ MemoryController memory( clk,
+ memory_read_cpu && run_mem,
+ memory_read_ppu && run_mem,
+ memory_write && run_mem || loader_write,
+ loader_write ? loader_addr : memory_addr,
+ loader_write ? loader_write_data : memory_dout,
+ memory_din_cpu, memory_din_ppu, ram_busy,
+ ram_WE_n, ram_a, ram_d,
+ debugaddr, debugdata);
+
reg ramfail;
always @(posedge clk) begin
if (loader_reset)
@@ -233,21 +256,21 @@ module NES_ZXUNO(
wire [9:0] vga_hcounter, doubler_x;
wire [9:0] vga_vcounter;
- VgaDriver vga(
- clk,
- vga_hsync,
- vga_vsync,
- vga_red,
- vga_green,
- vga_blue,
- vga_hcounter,
- vga_vcounter,
- doubler_x,
- doubler_pixel,
- doubler_sync,
+ VgaDriver vga(
+ clk,
+ vga_hsync,
+ vga_vsync,
+ vga_red,
+ vga_green,
+ vga_blue,
+ vga_hcounter,
+ vga_vcounter,
+ doubler_x,
+ doubler_pixel,
+ doubler_sync,
1'b0);
- wire [14:0] pixel_in = pallut[color];
+ wire [14:0] pixel_in = pallut[color];
Hq2x hq2x(clk, pixel_in, !hq_enable,
scanline[8], // reset_frame
@@ -258,7 +281,7 @@ module NES_ZXUNO(
assign AUDIO_R = audio;
assign AUDIO_L = audio;
- wire audio;
+ wire audio;
sigma_delta_dac sigma_delta_dac (
.DACout (audio),
@@ -267,7 +290,10 @@ module NES_ZXUNO(
.RESET (reset_nes)
);
-wire [31:0] rom_size;
+wire [31:0] rom_size;
+
+wire spi_miso_d;
+assign spi_miso_d = (SPI_CS == 1'b0)? SPI_MISO : 1'b0;
CtrlModule control (
.clk(clk_ctrl),
@@ -278,7 +304,7 @@ wire [31:0] rom_size;
.osd_pixel(osd_pixel),
.ps2k_clk_in(PS2_CLK),
.ps2k_dat_in(PS2_DAT),
- .spi_miso(SPI_MISO),
+ .spi_miso(spi_miso_d), //SPI_MISO
.spi_mosi(SPI_MOSI),
.spi_clk(SPI_CLK),
.spi_cs(SPI_CS),
@@ -292,7 +318,7 @@ wire [31:0] rom_size;
.host_reset_loader(host_reset_loader),
.host_bootdata(bootdata),
.host_bootdata_req(bootdata_req),
- .host_bootdata_ack(bootdata_ack),
+ .host_bootdata_ack(bootdata_ack),
.host_master_reset(master_reset)
);
@@ -312,10 +338,10 @@ wire [31:0] rom_size;
.scanline_ena(scanlines)
);
/*
- SSEG_Driver debugboard ( .clk( clk ),
- .reset( 1'b0 ),
+ SSEG_Driver debugboard ( .clk( clk ),
+ .reset( 1'b0 ),
.data( data ),
- .sseg( sseg_a_to_dp ),
+ .sseg( sseg_a_to_dp ),
.an( sseg_an ) );
*/
reg write_fifo;
@@ -340,29 +366,29 @@ assign clk_gameloader = counter_fifo[6];
.empty(empty_fifo)
);
-always@( posedge clk_ctrl )
-begin
- if (host_reset_loader == 1'b1) begin
- bootdata_ack <= 1'b0;
+always@( posedge clk_ctrl )
+begin
+ if (host_reset_loader == 1'b1) begin
+ bootdata_ack <= 1'b0;
boot_state <= 1'b0;
write_fifo <= 1'b0;
read_fifo <= 1'b0;
skip_fifo <= 1'b0;
- bytesloaded <= 32'h00000000;
+ bytesloaded <= 32'h00000000;
end else begin
if (dout_fifo == 8'h4E) skip_fifo <= 1'b1;
-
- case (boot_state)
- 1'b0:
+
+ case (boot_state)
+ 1'b0:
if (bootdata_req == 1'b1) begin
- if (full_fifo == 1'b0) begin
- boot_state <= 1'b1;
+ if (full_fifo == 1'b0) begin
+ boot_state <= 1'b1;
bootdata_ack <= 1'b1;
write_fifo <= (bytesloaded < rom_size) ? 1'b1 : 1'b0;
- end else read_fifo <= 1'b1;
+ end else read_fifo <= 1'b1;
end else begin
bootdata_ack <= 1'b0;
- end
+ end
1'b1:
begin
if (write_fifo == 1'b1) begin
@@ -371,11 +397,11 @@ begin
end
boot_state <= 1'b0;
bootdata_ack <= 1'b0;
- end
- endcase;
- end
+ end
+ endcase;
+ end
end
-
+
always@( posedge clk )
begin
/*
@@ -395,19 +421,19 @@ begin
counter_fifo <= counter_fifo + 1'b1;
clk_loader <= !clk_fifo && skip_fifo;
-end
+end
always@( posedge clk_loader)
begin
loader_input <= dout_fifo;
// data <= bytesloaded[19:4];
-end
-
-//-----------------Multiboot-------------
+end
+
+//-----------------Multiboot-------------
multiboot el_multiboot (
.clk_icap(clk),
- .REBOOT(master_reset | (~P_R & ~P_L & ~P_D & ~P_U))
- );
-
+ .REBOOT(master_reset)
+ );
+
endmodule
diff --git a/cores/NES/src/fifo_wrapper.v b/cores/NES/src/fifo_wrapper.v
index 91491ad..80492b5 100644
--- a/cores/NES/src/fifo_wrapper.v
+++ b/cores/NES/src/fifo_wrapper.v
@@ -1,23 +1,23 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 00:37:59 02/11/2016
-// Design Name:
-// Module Name: fifo_wrapper
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 00:37:59 02/11/2016
+// Design Name:
+// Module Name: fifo_wrapper
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
module reg_fifo(rst,
rd_clk, rd_en, dout, empty,
wr_clk, wr_en, din, full, prog_full);
@@ -91,4 +91,4 @@ module reg_fifo(rst,
else if (will_update_dout)
middle_valid <= 0;
end
-endmodule
+endmodule
diff --git a/cores/NES/src/multiboot_v4.v b/cores/NES/src/multiboot_v4.v
index 14c951a..9a5c1db 100644
--- a/cores/NES/src/multiboot_v4.v
+++ b/cores/NES/src/multiboot_v4.v
@@ -1,13 +1,13 @@
-module multiboot (
- input wire clk_icap,
- input wire REBOOT
- );
-
- reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
-
- reg [4:0] q = 5'b00000;
- reg reboot_ff = 1'b0;
-
+module multiboot (
+ input wire clk_icap,
+ input wire REBOOT
+ );
+
+ reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
+
+ reg [4:0] q = 5'b00000;
+ reg reboot_ff = 1'b0;
+
always @(posedge clk_icap) begin
q[0] <= REBOOT;
q[1] <= q[0];
@@ -15,20 +15,20 @@ module multiboot (
q[3] <= q[2];
q[4] <= q[3];
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
- end
-
+ end
+
multiboot_spartan6 hacer_multiboot (
.CLK(clk_icap),
- .MBT_RESET(1'b0),
- .MBT_REBOOT(reboot_ff),
+ .MBT_RESET(1'b0),
+ .MBT_REBOOT(reboot_ff),
.spi_addr(spi_addr)
);
-endmodule
-
+endmodule
+
module multiboot_spartan6 (
input wire CLK,
- input wire MBT_RESET,
- input wire MBT_REBOOT,
+ input wire MBT_RESET,
+ input wire MBT_REBOOT,
input wire [23:0] spi_addr
);
@@ -179,10 +179,10 @@ always @*
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
- end
-
-/////// Registro MODE (para carga a 4x tras reboot)
-
+ end
+
+/////// Registro MODE (para carga a 4x tras reboot)
+
MOD_H:
begin
next_state = MOD_L;
@@ -198,7 +198,7 @@ always @*
icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
end
-/////
+/////
NUL_L:
begin
diff --git a/cores/NES/xilinx/NES_ZXUNO.prj b/cores/NES/xilinx/NES_ZXUNO.prj
index 9053cd5..222428a 100644
--- a/cores/NES/xilinx/NES_ZXUNO.prj
+++ b/cores/NES/xilinx/NES_ZXUNO.prj
@@ -1,24 +1,24 @@
-vhdl work "ipcore_dir/nes_clk.vhd"
-vhdl work "ipcore_dir/ram8k.vhd"
-vhdl work "ipcore_dir/ram2k.vhd"
-vhdl work "ipcore_dir/DualPortRAM_Block.vhd"
-vhdl work "ipcore_dir/fifo_loader.vhd"
-vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpupkg.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/CharROM/CharROM_ROM.vhd"
-verilog work "../src/compat.v"
-vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpu_core_flex.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/spi.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/OnScreenDisplay.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/io_ps2_com.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/interrupt_controller.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
-verilog work "../src/vga.v"
-verilog work "../src/sigma_delta_dac.v"
-verilog work "../src/nes.v"
-verilog work "../src/multiboot_v4.v"
-verilog work "../src/memorycontroller.v"
-verilog work "../src/hq2x.v"
-verilog work "../src/GameLoader.v"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/OSD_Overlay.vhd"
-vhdl work "../src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd"
-verilog work "../src/NES_ZXUNO.v"
+vhdl work "ipcore_dir/nes_clk.vhd"
+vhdl work "ipcore_dir/ram8k.vhd"
+vhdl work "ipcore_dir/ram2k.vhd"
+vhdl work "ipcore_dir/fifo_loader.vhd"
+vhdl work "ipcore_dir/DualPortRAM_Block.vhd"
+vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpupkg.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/CharROM/CharROM_ROM.vhd"
+verilog work "../src/compat.v"
+vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpu_core_flex.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/spi.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/OnScreenDisplay.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/io_ps2_com.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/interrupt_controller.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
+verilog work "../src/vga.v"
+verilog work "../src/sigma_delta_dac.v"
+verilog work "../src/nes.v"
+verilog work "../src/multiboot_v4.v"
+verilog work "../src/memorycontroller.v"
+verilog work "../src/hq2x.v"
+verilog work "../src/GameLoader.v"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/OSD_Overlay.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd"
+verilog work "../src/NES_ZXUNO.v"
diff --git a/cores/NES/xilinx/NES_ZXUNO.ut b/cores/NES/xilinx/NES_ZXUNO.ut
index fb52ea8..6d8fcd3 100644
--- a/cores/NES/xilinx/NES_ZXUNO.ut
+++ b/cores/NES/xilinx/NES_ZXUNO.ut
@@ -1,31 +1,30 @@
--w
--g Binary:no
--g Compress
--g CRC:Enable
--g Reset_on_err:No
--g ConfigRate:2
--g ProgPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g ExtMasterCclk_en:Yes
--g ExtMasterCclk_divide:50
--g SPI_buswidth:1
--g TIMER_CFG:0xFFFF
--g multipin_wakeup:No
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:Yes
--g DriveDone:No
--g en_sw_gsr:No
--g drive_awake:No
--g sw_clk:Startupclk
--g sw_gwe_cycle:5
--g sw_gts_cycle:4
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/cores/NES/xilinx/NES_ZXUNO.xst b/cores/NES/xilinx/NES_ZXUNO.xst
index 3a8c425..d876d17 100644
--- a/cores/NES/xilinx/NES_ZXUNO.xst
+++ b/cores/NES/xilinx/NES_ZXUNO.xst
@@ -1,54 +1,53 @@
-set -tmpdir "projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn NES_ZXUNO.prj
--ofn NES_ZXUNO
--ofmt NGC
--p xc6slx9-2-tqg144
--top NES_ZXUNO
--opt_mode Speed
--opt_level 1
--power NO
--uc "timings.xcf"
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--sd {"ipcore_dir" }
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc Auto
--reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--shreg_min_size 2
--use_dsp48 Auto
--iobuf YES
--max_fanout 100000
--bufg 16
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn NES_ZXUNO.prj
+-ofn NES_ZXUNO
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top NES_ZXUNO
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-sd {"ipcore_dir" }
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Block
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/cores/NES/xilinx/ipcore_dir/DualPortRAM_Block.gise b/cores/NES/xilinx/ipcore_dir/DualPortRAM_Block.gise
index def80f1..f009969 100644
--- a/cores/NES/xilinx/ipcore_dir/DualPortRAM_Block.gise
+++ b/cores/NES/xilinx/ipcore_dir/DualPortRAM_Block.gise
@@ -1,31 +1,31 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- 11.1
-
-
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-
-
-
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-
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-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
diff --git a/cores/NES/xilinx/ipcore_dir/fifo_loader.gise b/cores/NES/xilinx/ipcore_dir/fifo_loader.gise
index afc99d2..3f4fce7 100644
--- a/cores/NES/xilinx/ipcore_dir/fifo_loader.gise
+++ b/cores/NES/xilinx/ipcore_dir/fifo_loader.gise
@@ -1,31 +1,31 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- 11.1
-
-
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+
+
+
+
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+
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+
+
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+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
diff --git a/cores/NES/xilinx/ipcore_dir/nes_clk.gise b/cores/NES/xilinx/ipcore_dir/nes_clk.gise
index 7d758c5..346d781 100644
--- a/cores/NES/xilinx/ipcore_dir/nes_clk.gise
+++ b/cores/NES/xilinx/ipcore_dir/nes_clk.gise
@@ -1,31 +1,31 @@
-
-
-
-
-
-
-
-
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- 11.1
-
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+
+
+
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+
+ 11.1
+
+
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+
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+
+
diff --git a/cores/NES/xilinx/ipcore_dir/nes_clk.ncf b/cores/NES/xilinx/ipcore_dir/nes_clk.ncf
index 488c55b..44e5806 100644
--- a/cores/NES/xilinx/ipcore_dir/nes_clk.ncf
+++ b/cores/NES/xilinx/ipcore_dir/nes_clk.ncf
@@ -1,59 +1,59 @@
-# file: nes_clk.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-
-
+# file: nes_clk.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+
+
diff --git a/cores/NES/xilinx/ipcore_dir/ram2k.gise b/cores/NES/xilinx/ipcore_dir/ram2k.gise
index 0d643d0..04e5bbd 100644
--- a/cores/NES/xilinx/ipcore_dir/ram2k.gise
+++ b/cores/NES/xilinx/ipcore_dir/ram2k.gise
@@ -1,31 +1,31 @@
-
-
-
-
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+ 11.1
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diff --git a/cores/NES/xilinx/ipcore_dir/ram8k.gise b/cores/NES/xilinx/ipcore_dir/ram8k.gise
index 17503ae..834e611 100644
--- a/cores/NES/xilinx/ipcore_dir/ram8k.gise
+++ b/cores/NES/xilinx/ipcore_dir/ram8k.gise
@@ -1,31 +1,31 @@
-
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+ 11.1
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