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Subo últimos cambios de test21

This commit is contained in:
antoniovillena 2016-05-23 00:58:24 +02:00
parent 7ae29a8888
commit 0dc903804b
11 changed files with 143 additions and 132 deletions
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5
cores/Spectrum/YM2149_linmix.vhd
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@ -85,7 +85,8 @@ entity YM2149 is
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
CLK : in std_logic; -- note 6 Mhz
CLK28 : in std_logic
);
end;
@ -193,7 +194,7 @@ begin
p_wdata : process
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
wait until rising_edge(CLK);
wait until rising_edge(CLK28);
env_reset <= '0';
if (RESET_L = '0') then

4
cores/Spectrum/coreid.v
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@ -39,8 +39,8 @@ module coreid (
text[ 1] = "2";
text[ 2] = "1";
text[ 3] = "-";
text[ 4] = "1";
text[ 5] = "7";
text[ 4] = "2";
text[ 5] = "2";
text[ 6] = "0";
text[ 7] = "5";
text[ 8] = "2";

102
cores/Spectrum/cuatro_relojes.v
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@ -14,15 +14,16 @@ module clock_generator
output wire CLK_OUT2,
output wire CLK_OUT3,
output wire CLK_OUT4,
output wire cpuclk
output wire cpuclk,
output wire cpuclkplain
);
wire clkin1_buffered;
IBUFG BUFG_IN (
.O(clkin1_buffered),
.I(CLK_IN1)
.I(CLK_IN1)
);
reg [2:0] pll_option_stored = 3'b000;
reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot
always @(posedge clkin1_buffered) begin
@ -40,8 +41,8 @@ module clock_generator
// SSTEP is the input to start a reconfiguration. It should only be
// pulsed for one clock cycle.
.SSTEP(pulso_reconf[7]),
// STATE determines which state the PLL_ADV will be reconfigured to. A
// value of 0 correlates to state 1, and a value of 1 correlates to state
// STATE determines which state the PLL_ADV will be reconfigured to. A
// value of 0 correlates to state 1, and a value of 1 correlates to state
// 2.
.STATE(pll_option_stored),
// RST will reset the entire reference design including the PLL_ADV
@ -49,10 +50,10 @@ module clock_generator
// CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the
// clock for the PLL_DRP module
.CLKIN(clkin1_buffered),
// SRDY pulses for one clock cycle after the PLL_ADV is locked and the
// SRDY pulses for one clock cycle after the PLL_ADV is locked and the
// PLL_DRP module is ready to start another re-configuration
.SRDY(),
// These are the clock outputs from the PLL_ADV.
.CLK0OUT(CLK_OUT1),
.CLK1OUT(CLK_OUT2),
@ -61,54 +62,28 @@ module clock_generator
);
wire cpuclk_selected, cpuclk_3_2, cpuclk_1_0;
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
// .O(cpuclk_3_2),
// .I0(CLK_OUT2),
// .I1(CLK_OUT1),
// .S(turbo_enable[0])
// );
// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
// .O(cpuclk_1_0),
// .I0(CLK_OUT4),
// .I1(CLK_OUT3),
// .S(turbo_enable[0])
// );
//
// BUFGMUX cpuclk_selector (
// .O(cpuclk_selected),
// .I0(cpuclk_1_0),
// .I1(CLK_OUT2),
// .S(turbo_enable[1])
// );
//
// BUFGMUX aplicar_contienda (
// .O(cpuclk),
// .I0(cpuclk_selected), // when no contention, clock is this one
// .I1(1'b1), // during contention, clock is pulled up
// .S(CPUContention) // contention signal
// );
reg [2:0] clkdivider = 3'b000;
always @(posedge CLK_OUT1)
clkdivider <= clkdivider + 3'd1;
BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
.O(cpuclk_1_0),
.I0(clkdivider[2]),
.I1(clkdivider[1]),
BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
.O(cpuclk_3_2),
.I0(CLK_OUT2),
.I1(CLK_OUT1),
.S(turbo_enable[0])
);
BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
.O(cpuclk_1_0),
.I0(CLK_OUT4),
.I1(CLK_OUT3),
.S(turbo_enable[0])
);
BUFGMUX cpuclk_selector (
.O(cpuclk_selected),
.I0(cpuclk_1_0),
.I1(clkdivider[0]),
.I1(CLK_OUT2),
.S(turbo_enable[1])
);
BUFGMUX aplicar_contienda (
.O(cpuclk),
.I0(cpuclk_selected), // when no contention, clock is this one
@ -117,4 +92,37 @@ module clock_generator
);
// reg [2:0] clkdivider = 3'b000;
// always @(posedge CLK_OUT1)
// clkdivider <= clkdivider + 3'd1;
//
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
// .O(cpuclk_3_2),
// .I0(clkdivider[0]),
// .I1(CLK_OUT1),
// .S(turbo_enable[0])
// );
//
// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
// .O(cpuclk_1_0),
// .I0(clkdivider[2]),
// .I1(clkdivider[1]),
// .S(turbo_enable[0])
// );
//
// BUFGMUX cpuclk_selector (
// .O(cpuclk_selected),
// .I0(cpuclk_1_0),
// .I1(cpuclk_3_2/*clkdivider[0]*/),
// .S(turbo_enable[1])
// );
//
// BUFGMUX aplicar_contienda (
// .O(cpuclk),
// .I0(cpuclk_selected), // when no contention, clock is this one
// .I1(1'b1), // during contention, clock is pulled up
// .S(CPUContention) // contention signal
// );
assign cpuclkplain = cpuclk_selected;
endmodule

2
cores/Spectrum/flash_spi.v
View File

@ -33,6 +33,7 @@ module flash_and_sd (
input wire [7:0] din, // del bus de datos de salida de la CPU
output wire [7:0] dout, // al bus de datos de entrada de la CPU
output wire oe_n, // el dato en dout es válido
output wire wait_n, // pausa para la CPU. Mejora estabilidad
input wire in_boot_mode,// Esta interfaz sólo es válida en modo boot
output wire flash_cs_n, //
@ -103,6 +104,7 @@ module flash_and_sd (
.din(din),
.dout(dout),
.oe_n(oe_n),
.wait_n(wait_n),
.spi_clk(sclk),
.spi_di(mosi),

2
cores/Spectrum/new_memory.v
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@ -442,7 +442,7 @@ module new_memory (
oe_n = 1'b0;
end
else begin
dout = 8'hFF;
dout = 8'hZZ;
oe_n = 1'b1;
end
end

6
cores/Spectrum/rom.v
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@ -24,7 +24,7 @@ module rom (
output reg [7:0] dout
);
reg [7:0] mem[0:255]; //127
reg [7:0] mem[0:255];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
for (i=0;i<256;i=i+1) begin
@ -32,8 +32,8 @@ module rom (
end
$readmemh ("bootloader_hex.txt", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a[7:0]]; //6:0
dout <= mem[a[7:0]];
end
endmodule

11
cores/Spectrum/spi.v
View File

@ -27,6 +27,7 @@ module spi (
input wire [7:0] din, // del bus de datos de salida de la CPU
output reg [7:0] dout, // al bus de datos de entrada de la CPU
output reg oe_n, // el dato en dout es válido
output reg wait_n,
output wire spi_clk, // Interface SPI
output wire spi_di, //
@ -44,12 +45,15 @@ module spi (
assign spi_clk = contador[0]; // spi_CLK es la mitad que el reloj del módulo
assign spi_di = data_to_spi[7]; // la transmisión es del bit 7 al 0
initial wait_n = 1'b1;
always @(posedge clk) begin
if (enviar_dato && !ciclo_escritura) begin // si ha sido señalizado, iniciar ciclo de escritura
ciclo_escritura <= 1'b1;
ciclo_lectura <= 1'b0;
contador <= 5'b00000;
data_to_spi <= din;
wait_n <= 1'b0;
end
else if (recibir_dato && !ciclo_lectura) begin // si no, si mirar si hay que iniciar ciclo de lectura
ciclo_lectura <= 1'b1;
@ -57,12 +61,15 @@ module spi (
contador <= 5'b00000;
data_to_cpu <= data_from_spi;
data_from_spi <= 8'h00;
data_to_spi <= 8'hFF; // mientras leemos, MOSI debe estar a nivel alto!
data_to_spi <= 8'hFF; // mientras leemos, MOSI debe estar a nivel alto!
wait_n <= 1'b0;
end
// FSM para enviar un dato a la spi
else if (ciclo_escritura==1'b1) begin
if (contador!=5'b10000) begin
if (contador == 5'b01000)
wait_n <= 1'b1;
if (spi_clk==1'b1) begin
data_to_spi <= {data_to_spi[6:0],1'b0};
data_from_spi <= {data_from_spi[6:0],spi_do};
@ -78,6 +85,8 @@ module spi (
// FSM para leer un dato de la spi
else if (ciclo_lectura==1'b1) begin
if (contador!=5'b10000) begin
if (contador == 5'b01000)
wait_n <= 1'b1;
if (spi_clk==1'b1)
data_from_spi <= {data_from_spi[6:0],spi_do};
contador <= contador + 1;

21
cores/Spectrum/tld_zxuno.v
View File

@ -39,7 +39,7 @@ module tld_zxuno (
output wire stdn,
output wire stdnb,
output wire [18:0] sram_addr,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
@ -61,14 +61,16 @@ module tld_zxuno (
input wire joyfire
);
wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk;
wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk,cpuclkplain;
wire CPUContention;
wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option;
assign wssclk = 1'b0; // de momento, sin WSS
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
assign sram_addr[19] = 1'b0;
assign sram_addr[20] = 1'b0;
clock_generator relojes_maestros
(// Clock in ports
@ -81,7 +83,8 @@ module tld_zxuno (
.CLK_OUT2 (clk14),
.CLK_OUT3 (clk7),
.CLK_OUT4 (clk3d5),
.cpuclk (cpuclk)
.cpuclk (cpuclk),
.cpuclkplain (cpuclkplain)
);
wire audio_out;
@ -94,12 +97,12 @@ module tld_zxuno (
wire vga_enable, scanlines_enable;
zxuno la_maquina (
.clk(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ahí, para el resto del circuito
.wssclk(wssclk), // 5MHz, reloj para el WSS
.clk28(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ahí, para el resto del circuito
.clk14(clk14),
.clk7(clk7),
.clk3d5(clk3d5),
.cpuclk(cpuclk),
.cpuclkplain(cpuclkplain),
.CPUContention(CPUContention),
.power_on_reset_n(1'b1), // sólo para simulación. Para implementacion, dejar a 1
.r(ri),
@ -144,8 +147,8 @@ module tld_zxuno (
vga_scandoubler #(.CLKVIDEO(14000)) salida_vga (
.clkvideo(clk14),
.clkvga(sysclk),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.ri(ri),
.gi(gi),
.bi(bi),
@ -168,6 +171,4 @@ module tld_zxuno (
// end
// assign testled = ~monoestable[21];
endmodule

6
cores/Spectrum/turbosound.v
View File

@ -67,7 +67,8 @@ YM2149 ay1 (
.O_IOB_OE_L(),
.ENA(~disable_ay),
.RESET_L(reset_n),
.CLK(clkay)
.CLK(clkay),
.CLK28(clk)
);
YM2149 ay2 (
@ -89,7 +90,8 @@ YM2149 ay2 (
.O_IOB_OE_L(),
.ENA(~disable_ay & ~disable_turboay),
.RESET_L(reset_n),
.CLK(clkay)
.CLK(clkay),
.CLK28(clk)
);
endmodule

22
cores/Spectrum/ula_radas.v
View File

@ -23,9 +23,10 @@
module ula_radas (
// Clocks
input wire clk14, // 14MHz master clock
input wire clk28,
input wire clkregs, // clock to load registers
input wire clk14, // 14MHz master clock
input wire clk7,
input wire wssclk, // 5MHz WSS clock
input wire cpuclk,
output wire CPUContention,
input wire rst_n, // reset para volver al modo normal
@ -150,7 +151,7 @@ module ula_radas (
// Border register
reg [2:0] Border = 3'b010; // initial border colour is red
always @(posedge clk7) begin
always @(posedge clkregs) begin
if (WriteToPortFE)
Border <= din[2:0];
end
@ -182,7 +183,7 @@ module ula_radas (
wire HR = TimexConfigReg[2];
assign doc_ext_option = enable_timexmmu & TimexConfigReg[7];
wire [2:0] HRInk = TimexConfigReg[5:3];
always @(posedge clk7) begin
always @(posedge clkregs) begin
if (rst_n == 1'b0)
TimexConfigReg <= 8'h00;
else if (TimexConfigLoad)
@ -245,8 +246,8 @@ module ula_radas (
`define full 3'b111
reg [8:0] Std9bitColour;
always @* begin
Std9bitColour = {`none,`none,`none};
case (StdPixelColour) // speccy colour to GGGRRRBBB colour. If you want to alter the standard palette, this is what you need to touch ;)
case (StdPixelColour) // speccy colour to GGGRRRBBB colour. If you want to alter the standard palette,
// this is what you need to touch ;)
0,8: Std9bitColour = {`none,`none,`none};
1: Std9bitColour = {`none,`none,`half};
2: Std9bitColour = {`none,`half,`none};
@ -262,12 +263,13 @@ module ula_radas (
13: Std9bitColour = {`full,`none,`full};
14: Std9bitColour = {`full,`full,`none};
15: Std9bitColour = {`full,`full,`full};
default: Std9bitColour = {`none,`none,`none};
endcase
end
// PaletteReg register (ULAplus)
reg [6:0] PaletteReg = 7'h00;
always @(posedge clk7) begin
always @(posedge clkregs) begin
if (PaletteRegLoad)
PaletteReg <= din[6:0];
end
@ -276,7 +278,7 @@ module ula_radas (
reg [1:0] ConfigReg = 2'b00;
wire ULAplusEnabled = ConfigReg[0];
assign RadasEnabled = ConfigReg[1];
always @(posedge clk7) begin
always @(posedge clkregs) begin
if (rst_n == 1'b0)
ConfigReg <= 2'b00;
else if (ConfigRegLoad)
@ -293,7 +295,7 @@ module ula_radas (
wire [5:0] AddressA2 = (RadasEnabled)? {2'b00,InputToAttrOutput[3:0]} :
{InputToAttrOutput[7:6],1'b0,InputToAttrOutput[2:0]};
lut palette (
.clk(clk7),
.clk(clk28),
.load(PaletteLoad),
.din(din),
.a1(AddressA1),
@ -444,7 +446,7 @@ module ula_radas (
// Z80 writes values into registers
// Port 0xFE
always @(posedge clk7) begin
always @(posedge clkregs) begin
if (WriteToPortFE) begin
{spk,mic} <= din[4:3];
end

94
cores/Spectrum/zxuno.v
View File

@ -22,13 +22,13 @@
//////////////////////////////////////////////////////////////////////////////////
module zxuno (
// Relojes
input wire clk, // 28MHz, reloj del sistema
input wire wssclk, // 5MHz, reloj de la señal WSS
input wire clk28,
input wire clk14,
input wire clk7,
input wire clk3d5,
input wire cpuclk,
output wire CPUContention,
input wire cpuclkplain, // reloj seleccionado para la CPU, antes de aplicar contención
input wire cpuclk, // reloj seleccionado par ala CPU, después de aplicar contención
output wire CPUContention, // Señal de contención del reloj de la CPU
input wire power_on_reset_n,
// E/S
@ -78,7 +78,7 @@ module zxuno (
);
// Señales de la CPU
wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n;
wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n,wait_n;
wire enable_nmi_n;
wire [15:0] cpuaddr;
reg [7:0] cpudin;
@ -191,24 +191,6 @@ module zxuno (
// Asignación de dato para la CPU segun la decodificación de todos los dispositivos
// conectados a ella.
// assign cpudin = (oe_n_romyram==1'b0)? memory_dout :
// (oe_n_ay==1'b0)? ay_dout :
// (oe_n_joystick==1'b0)? joystick_dout :
// (oe_n_zxunoaddr==1'b0)? zxuno_addr_to_cpu :
// (oe_n_spi==1'b0)? spi_dout :
// (oe_n_scancode==1'b0)? scancode_dout :
// (oe_n_kbstatus==1'b0)? kbstatus_dout :
// (oe_n_coreid==1'b0)? coreid_dout :
// (oe_n_keymap==1'b0)? keymap_dout :
// (oe_n_scratch==1'b0)? scratch_dout :
// (oe_n_scndblctrl==1'b0)? scndblctrl_dout :
// (oe_n_nmievents==1'b0)? nmievents_dout :
// (oe_n_kmouse==1'b0)? kmouse_dout :
// (oe_n_mousedata==1'b0)? mousedata_dout :
// (oe_n_mousestatus==1'b0)? mousestatus_dout :
// (oe_n_rasterint==1'b0)? rasterint_dout :
// (oe_n_devoptions==1'b0)? devoptions_dout :
// ula_dout;
always @* begin
case (1'b0)
oe_n_ay : cpudin = ay_dout;
@ -246,7 +228,7 @@ module zxuno (
.reset_n(rst_n & mrst_n & power_on_reset_n), // cualquiera de los dos resets
.clk(cpuclk),
.wait_n(1'b1),
.wait_n(wait_n),
.int_n(int_n),
.nmi_n((nmi_n | enable_nmi_n) & nmispecial_n),
.busrq_n(1'b1),
@ -255,22 +237,23 @@ module zxuno (
ula_radas la_ula (
// Clocks
.clk28(clk28),
.clkregs(cpuclkplain),
.clk14(clk14), // 14MHz master clock
.clk7(clk7),
.wssclk(wssclk), // 5MHz WSS clock
.cpuclk(cpuclk),
.CPUContention(CPUContention),
.rst_n(mrst_n & rst_n & power_on_reset_n),
// CPU interface
.a(cpuaddr),
.a(cpuaddr),
.access_to_contmem(access_to_screen),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.int_n(int_n),
.din(cpudout),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.int_n(int_n),
.din(cpudout),
.dout(ula_dout),
.rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable),
@ -293,15 +276,15 @@ module zxuno (
.enable_timexmmu(enable_timexmmu),
// Video
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.vsync(vsync)
);
zxunoregs addr_reg_zxuno (
.clk(clk),
.clk(cpuclkplain),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.a(cpuaddr),
.iorq_n(iorq_n),
@ -317,7 +300,7 @@ module zxuno (
);
flash_and_sd cacharros_con_spi (
.clk(clk),
.clk(clk28),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
@ -328,6 +311,7 @@ module zxuno (
.din(cpudout),
.dout(spi_dout),
.oe_n(oe_n_spi),
.wait_n(wait_n),
.in_boot_mode(in_boot_mode),
.flash_cs_n(flash_cs_n),
@ -343,8 +327,8 @@ module zxuno (
new_memory bootrom_rom_y_ram (
// Relojes y reset
.clk(clk), // Reloj del sistema CLK7
.mclk(clk), // Reloj para el modulo de memoria de doble puerto
.clk(cpuclkplain), // Reloj para registros de configuración
.mclk(clk28), // Reloj para el modulo de memoria de doble puerto
.mrst_n(mrst_n & power_on_reset_n),
.rst_n(rst_n & power_on_reset_n),
@ -395,7 +379,7 @@ module zxuno (
);
ps2_keyb el_teclado (
.clk(clk),
.clk(cpuclkplain),
.clkps2(clkps2),
.dataps2(dataps2),
.rows(kbdrow),
@ -420,7 +404,7 @@ module zxuno (
);
joystick_protocols los_joysticks (
.clk(clk),
.clk(cpuclkplain),
//-- cpu interface
.a(cpuaddr),
.iorq_n(iorq_n),
@ -441,7 +425,7 @@ module zxuno (
);
coreid identificacion_del_core (
.clk(clk),
.clk(cpuclkplain),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
@ -451,7 +435,7 @@ module zxuno (
);
scratch_register scratch (
.clk(clk),
.clk(cpuclkplain),
.poweron_rst_n(power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
@ -462,7 +446,7 @@ module zxuno (
);
control_enable_options device_enables (
.clk(clk),
.clk(cpuclkplain),
.rst_n(mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
@ -481,7 +465,7 @@ module zxuno (
);
scandoubler_ctrl control_scandoubler (
.clk(clk),
.clk(cpuclkplain),
.a(cpuaddr),
.iorq_n(iorq_n),
.wr_n(wr_n),
@ -498,7 +482,7 @@ module zxuno (
);
rasterint_ctrl control_rasterint (
.clk(clk),
.clk(cpuclkplain),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
@ -513,7 +497,7 @@ module zxuno (
);
nmievents nmi_especial_de_antonio (
.clk(clk),
.clk(cpuclkplain),
.rst_n(rst_n & mrst_n & power_on_reset_n),
//------------------------------
.zxuno_addr(zxuno_addr),
@ -532,7 +516,7 @@ module zxuno (
);
ps2_mouse_kempston el_raton (
.clk(clk),
.clk(cpuclkplain),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.clkps2(mouseclk),
.dataps2(mousedata),
@ -554,7 +538,7 @@ module zxuno (
);
multiboot el_multiboot (
.clk(clk),
.clk(cpuclkplain),
.clk_icap(clk14),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.kb_boot_core(boot_second_core),
@ -577,7 +561,7 @@ module zxuno (
assign bc1 = (cpuaddr[15] && cpuaddr[1:0]==2'b01 && cpuaddr[14] && !iorq_n)? 1'b1 : 1'b0;
turbosound dos_ays (
.clk(clk),
.clk(cpuclkplain),
.clkay(clk3d5),
.disable_ay(disable_ay),
.disable_turboay(disable_turboay),
@ -596,13 +580,15 @@ module zxuno (
///////////////////////////////////
// 8-bit mixer to generate different audio levels according to input sources
mixer audio_mix(
.clkdac(clk),
.clkdac(clk28),
.reset(1'b0),
// Audio sources to mix
.mic(mic),
.spk(spk),
.ear(ear),
.ay1(ay1_audio),
.ear(ear),
.ay1(ay1_audio),
.ay2(ay2_audio),
// PWM output mixed (monoaural ATM)
.audio(audio_out)
);