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Actualizo test21

This commit is contained in:
antoniovillena 2016-05-14 16:29:44 +02:00
parent 5620c6fe99
commit 0f38950b29
9 changed files with 236 additions and 128 deletions
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27
cores/Spectrum/audio_management.v
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@ -19,7 +19,7 @@
// //
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
`define MSBI 9 // Most significant Bit of DAC input `define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter //This is a Delta-Sigma Digital to Analog Converter
module dac (DACout, DACin, Clk, Reset); module dac (DACout, DACin, Clk, Reset);
@ -37,7 +37,7 @@ module dac (DACout, DACin, Clk, Reset);
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1); always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB; always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch; always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset) always @(posedge Clk)
begin begin
if(Reset) if(Reset)
begin begin
@ -63,7 +63,11 @@ module mixer (
output wire audio output wire audio
); );
reg [9:0] mezcla = 10'h000; parameter
SRC_BEEPER = 2'd0,
SRC_AY1 = 2'd1,
SRC_AY2 = 2'd2;
wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 : wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 : ({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 : ({ear,spk,mic}==3'b010)? 8'd184 :
@ -72,10 +76,21 @@ module mixer (
({ear,spk,mic}==3'b101)? 8'd48 : ({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255; ({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
wire [9:0] mezcla10bits = {2'b00,ay1} + {2'b00,ay2} + {2'b00,beeper} ; reg [7:0] mezcla;
reg [3:0] cntsamples = 4'd0;
reg [1:0] sndsource = 2'd0;
always @(posedge clkdac) always @(posedge clkdac) begin
mezcla <= mezcla10bits; if (cntsamples == 4'd0) begin // cada 256 cuentas de reloj, cambiamos de fuente de sonido
case (sndsource)
SRC_BEEPER: mezcla <= beeper;
SRC_AY1 : mezcla <= ay1;
SRC_AY2 : mezcla <= ay2;
endcase
sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
end
cntsamples <= cntsamples + 4'd1;
end
dac audio_dac ( dac audio_dac (
.DACout(audio), .DACout(audio),

80
cores/Spectrum/cuatro_relojes.v
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@ -8,7 +8,7 @@ module clock_generator
input wire CLK_IN1, input wire CLK_IN1,
input wire CPUContention, input wire CPUContention,
input wire [2:0] pll_option, input wire [2:0] pll_option,
input wire turbo_enable, input wire [1:0] turbo_enable,
// Clock out ports // Clock out ports
output wire CLK_OUT1, output wire CLK_OUT1,
output wire CLK_OUT2, output wire CLK_OUT2,
@ -17,8 +17,6 @@ module clock_generator
output wire cpuclk output wire cpuclk
); );
wire cpuclk_selected;
reg [2:0] pll_option_stored = 3'b000; reg [2:0] pll_option_stored = 3'b000;
reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot
always @(posedge CLK_IN1) begin always @(posedge CLK_IN1) begin
@ -56,14 +54,82 @@ module clock_generator
.CLK3OUT(CLK_OUT4) .CLK3OUT(CLK_OUT4)
); );
BUFGMUX cpuclk_selector ( // wire clk28, clk14, clk7, clk3d5, cpuclk_3_2, cpuclk_1_0;
.O(cpuclk_selected), //
// BUFGMUX reloj28_contenido (
// .O(clk28),
// .I0(CLK_OUT1),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj14_contenido (
// .O(clk14),
// .I0(CLK_OUT2),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj7_contenido (
// .O(clk7),
// .I0(CLK_OUT3),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj3d5_contenido (
// .O(clk3d5),
// .I0(CLK_OUT4),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
// .O(cpuclk_3_2),
// .I0(clk14),
// .I1(clk28),
// .S(turbo_enable[0])
// );
//
// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
// .O(cpuclk_1_0),
// .I0(clk3d5),
// .I1(clk7),
// .S(turbo_enable[0])
// );
//
// BUFGMUX cpuclk_selector (
// .O(cpuclk),
// .I0(cpuclk_1_0),
// .I1(cpuclk_3_2),
// .S(turbo_enable[1])
// );
wire cpuclk_selected, cpuclk_3_2, cpuclk_1_0;
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
// .O(cpuclk_3_2),
// .I0(CLK_OUT2),
// .I1(CLK_OUT1),
// .S(turbo_enable[0])
// );
BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
.O(cpuclk_1_0),
.I0(CLK_OUT4), .I0(CLK_OUT4),
.I1(CLK_OUT3), .I1(CLK_OUT3),
.S(turbo_enable) .S(turbo_enable[0])
); );
BUFGMUX selector_reloj_cpu ( BUFGMUX cpuclk_selector (
.O(cpuclk_selected),
.I0(cpuclk_1_0),
.I1(CLK_OUT2),
.S(turbo_enable[1])
);
BUFGMUX aplicar_contienda (
.O(cpuclk), .O(cpuclk),
.I0(cpuclk_selected), // when no contention, clock is this one .I0(cpuclk_selected), // when no contention, clock is this one
.I1(1'b1), // during contention, clock is pulled up .I1(1'b1), // during contention, clock is pulled up

9
cores/Spectrum/flash_spi.v
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@ -22,7 +22,7 @@
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module flash_and_sd ( module flash_and_sd (
input wire clk, // 7MHz input wire clk, //
input wire [15:0] a, // input wire [15:0] a, //
input wire iorq_n, // Señales de control de E/S estándar input wire iorq_n, // Señales de control de E/S estándar
input wire rd_n, // para manejar los puertos ZXMMC y DIVMMC input wire rd_n, // para manejar los puertos ZXMMC y DIVMMC
@ -40,6 +40,7 @@ module flash_and_sd (
output wire flash_di, // output wire flash_di, //
input wire flash_do, // input wire flash_do, //
input wire disable_spisd,
output wire sd_cs_n, // output wire sd_cs_n, //
output wire sd_clk, // Interface SPI con la SD/MMC output wire sd_clk, // Interface SPI con la SD/MMC
output wire sd_mosi, // (de momento, solo puertos ZXMMC) output wire sd_mosi, // (de momento, solo puertos ZXMMC)
@ -74,7 +75,7 @@ module flash_and_sd (
flashpincs <= din[0]; flashpincs <= din[0];
sdpincs <= 1'b1; // si accedemos a la flash para cambiar su estado CS, automaticamente deshabilitamos la SD sdpincs <= 1'b1; // si accedemos a la flash para cambiar su estado CS, automaticamente deshabilitamos la SD
end end
else if (!iorq_n && (a[7:0]==SDCS || a[7:0]==DIVCS) && !wr_n) begin else if (!disable_spisd && !iorq_n && (a[7:0]==SDCS || a[7:0]==DIVCS) && !wr_n) begin
sdpincs <= din[0]; sdpincs <= din[0];
flashpincs <= 1'b1; // y lo mismo hacemos si es la SD a la que estamos accediendo flashpincs <= 1'b1; // y lo mismo hacemos si es la SD a la que estamos accediendo
end end
@ -84,11 +85,11 @@ module flash_and_sd (
reg enviar_dato; reg enviar_dato;
reg recibir_dato; reg recibir_dato;
always @* begin always @* begin
if ((addr==SPIPORT && ior && in_boot_mode) || (!iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !rd_n)) if ((addr==SPIPORT && ior && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !rd_n))
recibir_dato = 1'b1; recibir_dato = 1'b1;
else else
recibir_dato = 1'b0; recibir_dato = 1'b0;
if ((addr==SPIPORT && iow && in_boot_mode) || (!iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !wr_n)) if ((addr==SPIPORT && iow && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !wr_n))
enviar_dato = 1'b1; enviar_dato = 1'b1;
else else
enviar_dato = 1'b0; enviar_dato = 1'b0;

21
cores/Spectrum/multiboot.v
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@ -223,31 +223,12 @@ always @*
end end
GEN2_L: GEN2_L:
begin
next_state = MOD_H;
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
end
/////// Registro MODE (para carga a 4x tras reboot)
MOD_H:
begin
next_state = MOD_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3301; // Escritura a reg MODE
end
MOD_L:
begin begin
next_state = NUL_L; next_state = NUL_L;
icap_ce = 0; icap_ce = 0;
icap_wr = 0; icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config icap_din = {8'h03, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA
end end
/////
NUL_L: NUL_L:
begin begin

6
cores/Spectrum/scandoubler_ctrl.v
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@ -34,7 +34,7 @@ module scandoubler_ctrl (
output wire vga_enable, output wire vga_enable,
output wire scanlines_enable, output wire scanlines_enable,
output wire [2:0] freq_option, output wire [2:0] freq_option,
output wire turbo_enable output wire [1:0] turbo_enable
); );
parameter SCANDBLCTRL = 8'h0B; parameter SCANDBLCTRL = 8'h0B;
@ -45,14 +45,14 @@ module scandoubler_ctrl (
assign vga_enable = scandblctrl[0]; assign vga_enable = scandblctrl[0];
assign scanlines_enable = scandblctrl[1]; assign scanlines_enable = scandblctrl[1];
assign freq_option = scandblctrl[4:2]; assign freq_option = scandblctrl[4:2];
assign turbo_enable = scandblctrl[7]; assign turbo_enable = scandblctrl[7:6];
reg [7:0] scandblctrl = 8'h00; // initial value reg [7:0] scandblctrl = 8'h00; // initial value
always @(posedge clk) begin always @(posedge clk) begin
if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1) if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1)
scandblctrl <= din; scandblctrl <= din;
else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL) else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL)
scandblctrl[7] <= (din[3:0] == 4'b0000)? 1'b0 : 1'b1; scandblctrl[7:6] <= din[1:0];
dout <= scandblctrl; dout <= scandblctrl;
end end
endmodule endmodule

2
cores/Spectrum/tld_zxuno.v
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@ -63,7 +63,7 @@ module tld_zxuno (
wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk; wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk;
wire CPUContention; wire CPUContention;
wire turbo_enable; wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option; wire [2:0] pll_frequency_option;
assign wssclk = 1'b0; // de momento, sin WSS assign wssclk = 1'b0; // de momento, sin WSS

8
cores/Spectrum/turbosound.v
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@ -24,6 +24,8 @@ module turbosound (
input wire clk, input wire clk,
input wire clkay, input wire clkay,
input wire reset_n, input wire reset_n,
input wire disable_ay,
input wire disable_turboay,
input wire bdir, input wire bdir,
input wire bc1, input wire bc1,
input wire [7:0] din, input wire [7:0] din,
@ -37,7 +39,7 @@ module turbosound (
always @(posedge clk) begin always @(posedge clk) begin
if (reset_n==1'b0) if (reset_n==1'b0)
ay_select <= 1'b1; ay_select <= 1'b1;
else if (bdir && bc1 && din[7:1]==7'b1111111) else if (disable_ay == 1'b0 && disable_turboay == 1'b0 && bdir && bc1 && din[7:1]==7'b1111111)
ay_select <= din[0]; ay_select <= din[0];
end end
@ -63,7 +65,7 @@ YM2149 ay1 (
.I_IOB(8'h00), .I_IOB(8'h00),
.O_IOB(), .O_IOB(),
.O_IOB_OE_L(), .O_IOB_OE_L(),
.ENA(1'b1), .ENA(~disable_ay),
.RESET_L(reset_n), .RESET_L(reset_n),
.CLK(clkay) .CLK(clkay)
); );
@ -85,7 +87,7 @@ YM2149 ay2 (
.I_IOB(8'h00), .I_IOB(8'h00),
.O_IOB(), .O_IOB(),
.O_IOB_OE_L(), .O_IOB_OE_L(),
.ENA(1'b1), .ENA(~disable_ay & ~disable_turboay),
.RESET_L(reset_n), .RESET_L(reset_n),
.CLK(clkay) .CLK(clkay)
); );

11
cores/Spectrum/ula_radas.v
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@ -58,6 +58,7 @@ module ula_radas (
input wire disable_contention, input wire disable_contention,
input wire access_to_contmem, input wire access_to_contmem,
output wire doc_ext_option, output wire doc_ext_option,
input wire enable_timexmmu,
// Video // Video
output wire [2:0] r, output wire [2:0] r,
@ -179,7 +180,7 @@ module ula_radas (
wire PG = TimexConfigReg[0]; wire PG = TimexConfigReg[0];
wire HCL = TimexConfigReg[1]; wire HCL = TimexConfigReg[1];
wire HR = TimexConfigReg[2]; wire HR = TimexConfigReg[2];
assign doc_ext_option = TimexConfigReg[7]; assign doc_ext_option = enable_timexmmu & TimexConfigReg[7];
wire [2:0] HRInk = TimexConfigReg[5:3]; wire [2:0] HRInk = TimexConfigReg[5:3];
always @(posedge clk7) begin always @(posedge clk7) begin
if (rst_n == 1'b0) if (rst_n == 1'b0)
@ -444,12 +445,10 @@ module ula_radas (
// Z80 writes values into registers // Z80 writes values into registers
// Port 0xFE // Port 0xFE
always @(posedge clk7) begin always @(posedge clk7) begin
if (iorq_n==1'b0 && wr_n==1'b0) begin if (WriteToPortFE) begin
if (a[0]==1'b0 && a[7:0]!=8'hF4) begin
{spk,mic} <= din[4:3]; {spk,mic} <= din[4:3];
end end
end end
end
// TIMEX and ULAplus ports // TIMEX and ULAplus ports
always @* begin always @* begin
@ -494,7 +493,9 @@ module ula_radas (
dout = PaletteEntryToCPU; dout = PaletteEntryToCPU;
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1) else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1)
dout = {7'b0000000,ConfigReg}; dout = {7'b0000000,ConfigReg};
else if (a[7:0]==TIMEXPORT) begin else if (a[7:0]==TIMEXPORT && enable_timexmmu)
dout = TimexConfigReg;
else begin
if (BitmapAddr || AttrAddr) if (BitmapAddr || AttrAddr)
dout = vramdata; dout = vramdata;
else else

48
cores/Spectrum/zxuno.v
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@ -74,7 +74,7 @@ module zxuno (
output wire vga_enable, output wire vga_enable,
output wire scanlines_enable, output wire scanlines_enable,
output wire [2:0] freq_option, output wire [2:0] freq_option,
output wire turbo_enable output wire [1:0] turbo_enable
); );
// Señales de la CPU // Señales de la CPU
@ -162,6 +162,18 @@ module zxuno (
wire [7:0] rasterint_dout; wire [7:0] rasterint_dout;
wire oe_n_rasterint; wire oe_n_rasterint;
// Device enable options
wire disable_ay;
wire disable_turboay;
wire disable_7ffd;
wire disable_1ffd;
wire disable_romsel7f;
wire disable_romsel1f;
wire enable_timexmmu;
wire disable_spisd;
wire [7:0] devoptions_dout;
wire oe_n_devoptions;
// NMI events // NMI events
wire [7:0] nmievents_dout; wire [7:0] nmievents_dout;
wire oe_n_nmievents; wire oe_n_nmievents;
@ -195,6 +207,7 @@ module zxuno (
(oe_n_mousedata==1'b0)? mousedata_dout : (oe_n_mousedata==1'b0)? mousedata_dout :
(oe_n_mousestatus==1'b0)? mousestatus_dout : (oe_n_mousestatus==1'b0)? mousestatus_dout :
(oe_n_rasterint==1'b0)? rasterint_dout : (oe_n_rasterint==1'b0)? rasterint_dout :
(oe_n_devoptions==1'b0)? devoptions_dout :
ula_dout; ula_dout;
tv80n_wrapper el_z80 ( tv80n_wrapper el_z80 (
@ -255,6 +268,7 @@ module zxuno (
.mode(timing_mode), .mode(timing_mode),
.disable_contention(disable_contention), .disable_contention(disable_contention),
.doc_ext_option(doc_ext_option), .doc_ext_option(doc_ext_option),
.enable_timexmmu(enable_timexmmu),
// Video // Video
.r(r), .r(r),
@ -281,7 +295,7 @@ module zxuno (
); );
flash_and_sd cacharros_con_spi ( flash_and_sd cacharros_con_spi (
.clk(clk14), .clk(clk),
.a(cpuaddr), .a(cpuaddr),
.iorq_n(iorq_n), .iorq_n(iorq_n),
.rd_n(rd_n), .rd_n(rd_n),
@ -298,7 +312,7 @@ module zxuno (
.flash_clk(flash_clk), .flash_clk(flash_clk),
.flash_di(flash_di), .flash_di(flash_di),
.flash_do(flash_do), .flash_do(flash_do),
.disable_spisd(disable_spisd),
.sd_cs_n(sd_cs_n), .sd_cs_n(sd_cs_n),
.sd_clk(sd_clk), .sd_clk(sd_clk),
.sd_mosi(sd_mosi), .sd_mosi(sd_mosi),
@ -345,6 +359,13 @@ module zxuno (
.iow(zxuno_regwr), .iow(zxuno_regwr),
.in_boot_mode(in_boot_mode), .in_boot_mode(in_boot_mode),
// Interface con modulo de habilitacion de opciones
.disable_7ffd(disable_7ffd),
.disable_1ffd(disable_1ffd),
.disable_romsel7f(disable_romsel7f),
.disable_romsel1f(disable_romsel1f),
.enable_timexmmu(enable_timexmmu),
// Interface con la SRAM // Interface con la SRAM
.sram_addr(sram_addr), .sram_addr(sram_addr),
.sram_data(sram_data), .sram_data(sram_data),
@ -418,6 +439,25 @@ module zxuno (
.oe_n(oe_n_scratch) .oe_n(oe_n_scratch)
); );
control_enable_options device_enables (
.clk(clk),
.rst_n(mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(devoptions_dout),
.oe_n(oe_n_devoptions),
.disable_ay(disable_ay),
.disable_turboay(disable_turboay),
.disable_7ffd(disable_7ffd),
.disable_1ffd(disable_1ffd),
.disable_romsel7f(disable_romsel7f),
.disable_romsel1f(disable_romsel1f),
.enable_timexmmu(enable_timexmmu),
.disable_spisd(disable_spisd)
);
scandoubler_ctrl control_scandoubler ( scandoubler_ctrl control_scandoubler (
.clk(clk), .clk(clk),
.a(cpuaddr), .a(cpuaddr),
@ -517,6 +557,8 @@ module zxuno (
turbosound dos_ays ( turbosound dos_ays (
.clk(clk), .clk(clk),
.clkay(clk3d5), .clkay(clk3d5),
.disable_ay(disable_ay),
.disable_turboay(disable_turboay),
.reset_n(rst_n & mrst_n & power_on_reset_n), .reset_n(rst_n & mrst_n & power_on_reset_n),
.bdir(bdir), .bdir(bdir),
.bc1(bc1), .bc1(bc1),