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bad, but working vga

This commit is contained in:
byrtolet 2018-10-21 20:23:47 +03:00
parent e76acbdb97
commit 12596389f8
3 changed files with 44 additions and 30 deletions
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24
cores/Oric/source/oricatmos.vhd
View File

@ -476,18 +476,18 @@ begin
-- 381
-- output video timing
hA => 11, -- h front porch
hB => 46, -- h sync
hC => 24, -- h back porch
hA => 10, -- 7.62 11, -- h front porch
hB => 46, -- 45,759682224 -- h sync
hC => 24,-- 22,879841112-- h back porch
hD => 240, -- visible video
vA => 5, -- v front porch (not used)
vB => 1, -- v sync
--- total 381.33
vA => 40, -- v front porch (not used)
vB => 2, -- v sync
vC => 16, -- v back porch
vD => 224, -- visible video
vD => 240, -- visible video
hpad => 30, -- H black border
vpad => 10 -- V black border
hpad => 32, -- H black border
vpad => 0 -- V black border
)
port map (
I_VIDEO(15 downto 12) => "0000",
@ -526,9 +526,9 @@ begin
--Q
--Para scandoubler descomentar esto y comentar las directas de la ULA
O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2) ;
O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2) ;
O_VIDEO_B <= VideoB(0) & VideoB(1) & VideoB(2) ;
O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2);-- when s_cmpblk_n_out = '1' else (others => '0');
O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2);-- when s_cmpblk_n_out = '1' else (others => '0');
O_VIDEO_B <= VideoB(0) & VideoB(1) & VideoB(2);-- when s_cmpblk_n_out = '1' else (others => '0');
O_HSYNC <= HSync;
O_VSYNC <= VSync;

42
cores/Oric/source/scan_converter.vhd
View File

@ -90,6 +90,7 @@ architecture RTL of VGA_SCANCONV is
-- input timing
--
signal ivsync_last_x2 : std_logic := '1';
signal ihsync_last_x2 : std_logic := '1';
signal ihsync_last : std_logic := '1';
signal hpos_i : std_logic_vector( 9 downto 0) := (others => '0');
@ -98,6 +99,8 @@ architecture RTL of VGA_SCANCONV is
--
signal hpos_o : std_logic_vector(9 downto 0) := (others => '0');
signal O_VIDEOb : std_logic_vector(15 downto 0);
signal O_CMPBLK_Nb : std_logic;
signal vcnt : integer range 0 to 1023 := 0;
signal hcnt : integer range 0 to 1023 := 0;
signal hcnti : integer range 0 to 1023 := 0;
@ -135,7 +138,7 @@ begin
CLKA => CLK_x2,
-- output
DOB => O_VIDEO,
DOB => O_VIDEOb,
DIB => x"0000",
DOPB => open,
DIPB => "00",
@ -180,21 +183,31 @@ begin
-- VGA H and V counters, synchronized to input frame V sync, then H sync
p_out_ctrs : process
variable trigger : boolean;
variable triggerh : boolean;
begin
wait until rising_edge(CLK_x2);
ivsync_last_x2 <= I_VSYNC;
ihsync_last_x2 <= I_HSYNC;
if (I_VSYNC = '0') and (ivsync_last_x2 = '1') then
trigger := true;
elsif trigger and I_HSYNC = '0' then
trigger := false;
hcnt <= 0;
vcnt <= 0;
trigger := true;
end if;
if trigger and (I_HSYNC = '1') and (ihsync_last_x2 = '0') then
triggerh := true;
end if;
if trigger and triggerh then
trigger := false;
triggerh:= false;
hcnt <= 0;
vcnt <= 0;
else
hcnt <= hcnt + 1;
if hcnt = (hA+hB+hC+hD+hpad+hpad-1) then
hcnt <= 0;
vcnt <= vcnt + 1;
hcnt <= 0;
if (vcnt <1023) then
vcnt <= vcnt + 1;
end if;
end if;
end if;
end process;
@ -216,7 +229,7 @@ begin
begin
wait until rising_edge(CLK_x2);
-- V sync timing
if (vcnt < vB+vA) and (vcnt >= vA) then
if (vcnt < vB) then
O_VSYNC <= '0';
else
O_VSYNC <= '1';
@ -228,7 +241,7 @@ begin
begin
wait until rising_edge(CLK_x2);
-- visible video area doubled from the original game
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vA + vB + vC+vpad)) and (vcnt <= 2*(vA + vB + vC + vD + vpad))) then
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt >= 2*(vB + vC+vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then
hpos_o <= hpos_o + 1;
else
hpos_o <= (others => '0');
@ -240,11 +253,12 @@ begin
begin
wait until rising_edge(CLK_X2);
-- active video area 640x480 (VGA) after padding with blank borders
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vA + vB + vC)) and (vcnt <= 2*(vA + vB + vC + vD + 2*vpad))) then
O_CMPBLK_N <= '1';
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt >= 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then
O_CMPBLK_Nb <= '1';
else
O_CMPBLK_N <= '0';
O_CMPBLK_Nb <= '0';
end if;
end process;
O_VIDEO <= O_VIDEOb when O_CMPBLK_Nb = '1' else (others => '0');
O_CMPBLK_N <= O_CMPBLK_Nb;
end architecture RTL;

8
cores/Oric/source/ula.vhd
View File

@ -352,8 +352,8 @@ begin
lRELOAD_SEL <= '1' when (lCTR_H >= 49) else '0';
-- Vertical Synchronisation
lVSYNC50n <= '0' when (lCTR_V >= 258) and (lCTR_V <= 259) else '1'; -- 50Hz
lVSYNC60n <= '0' when (lCTR_V >= 241) and (lCTR_V <= 242) else '1'; -- 60Hz
lVSYNC50n <= '0' when (lCTR_V >= 258) else '1'; -- 50Hz
lVSYNC60n <= '0' when (lCTR_V >= 241) else '1'; -- 60Hz
lVSYNCn <= lVSYNC50n when lFREQ_SEL='1' else lVSYNC60n;
-- Vertical Blank
@ -431,7 +431,7 @@ begin
elsif rising_edge(CLK_24) then
if (RELD_REG = '1' and isAttrib = '1') then
case lREGHOLD(6 downto 3) is
when "0000" => lREG_INK <= lREGHOLD(2 downto 0);
when "0000" => lREG_INK <= lREGHOLD(2 downto 0);
when "0001" => lREG_STYLE <= lREGHOLD(2 downto 0);
when "0010" => lREG_PAPER <= lREGHOLD(2 downto 0);
when "0011" => lREG_MODE <= lREGHOLD(2 downto 0);
@ -445,7 +445,7 @@ begin
lALT_SEL <= lREG_STYLE(0); -- Character set select : 0=Standard 1=Alternate
lDBLHGT_SEL <= lREG_STYLE(1); -- Character type select: 0=Standard 1=Double
lFLASH_SEL <= lREG_STYLE(2); -- Flash select : 0=Steady 1=Flashing
lFREQ_SEL <= lREG_MODE(1); -- Frequency select : 0=60Hz 1=50Hz
lFREQ_SEL <= '0'; -- lREG_MODE(1); -- Frequency select : 0=60Hz 1=50Hz
lHIRES_SEL <= lREG_MODE(2); -- Mode Select : 0=Text 1=Hires
-- Output signal for text/hires mode decode