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Finaly fixed the timer bug

This commit is contained in:
byrtolet 2018-11-18 16:31:07 +02:00
parent 66ee769668
commit 2a9734d5b6
5 changed files with 14 additions and 28 deletions
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4
cores/Oric/build/ORIC.prj
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@ -10,8 +10,8 @@ vhdl work "../source/keyboard/keymap.vhd"
vhdl work "../source/YM2149_linmix.vhd"
vhdl work "../source/ula.vhd"
vhdl work "../source/scan_converter.vhd"
vhdl work "../source/pravetz.vhd"
#vhdl work "../source/rom_oa.vhd"
#vhdl work "../source/pravetz.vhd"
vhdl work "../source/rom_oa.vhd"
vhdl work "../source/ram48k.vhd"
vhdl work "../source/m6522.vhd"
vhdl work "../source/keyboard/keyboard.vhd"

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cores/Oric/disk/good1.dsk Normal file
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26
cores/Oric/source/m6522.vhd
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@ -191,22 +191,18 @@ architecture RTL of M6522 is
signal final_irq : std_logic;
begin
p_phase : process
p_phase : process(RESET_L, CLK)
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if rising_edge(CLK) then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
case phase is
when "00" => phase <= "01";
when "01" => phase <= "10";
when "10" => phase <= "11";
when "11" => phase <= "00";
when others => null;
end case;
if (ENA_4 = '1') then
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
elsif (p2_h_t1 = '1') and (I_P2_H = '0') then
phase <= "00";
else
phase <= "01";
end if;
end if;
end if;
end process;
@ -649,7 +645,7 @@ begin
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
if (phase = "00") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;

4
cores/Oric/source/oricatmos.vhd
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@ -197,7 +197,6 @@ architecture RTL of ORIC is
signal ula_OE_SRAM : std_logic;
signal ula_WE_SRAM : std_logic;
signal ula_LE_SRAM : std_logic;
signal ula_CLK_4 : std_logic;
signal ula_VIDEO_R : std_logic;
signal ula_VIDEO_G : std_logic;
signal ula_VIDEO_B : std_logic;
@ -460,7 +459,6 @@ begin
port map (
RESETn => cpu_reset_n,
CLK => clk24,
CLK_4 => ula_CLK_4,
RW => cpu_rw,
ADDR => CPU_ADDR(15 downto 0),
@ -641,7 +639,7 @@ begin
RESET_L => cpu_reset_n,
I_P2_H => ula_phi2,
ENA_4 => '1',
CLK => ula_CLK_4
CLK => CLK24
);
------------------------------------------------------------

8
cores/Oric/source/ula.vhd
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@ -80,7 +80,6 @@ library ieee;
entity ula is
port (
RESETn : in std_logic; -- RESET master
CLK_4 : out std_logic; -- 4 MHz internal
CLK : in std_logic; -- 24 MHz -- pin 07
PHI2 : out std_logic; -- 1 MHz CPU & system -- pin 14
@ -124,7 +123,6 @@ architecture RTL of ula is
-- Signal CLOCK
signal CLK_24 : std_logic; -- CLOCK 24 MHz internal
signal CLK_4_INT : std_logic; -- CLOCK 4 MHz internal
signal CLK_1_INT : std_logic; -- CLOCK 1 MHz internal
signal CLK_PIXEL_INT : std_logic; -- CLOCK PIXEL internal
signal CLK_FLASH : std_logic; -- CLOCK FLASH external
@ -223,7 +221,6 @@ begin
CSIOn <= CSIOn_INT;
CSROMn <= CSROMn_INT;
CSRAMn <= CSRAMn_INT;
CLK_4 <= CLK_4_INT;
------------------
-- SRAM signals --
@ -294,11 +291,6 @@ begin
-- CPU clock --
CLK_1_INT <= ph(2);
-- VIA 6522 clock
CLK_4_INT <= c(23) or c(0) or c(1)
or c(5) or c(6) or c(7)
or c(11) or c(12) or c(13)
or c(17) or c(18) or c(19);
-- LD_REG_0 <= isAttrib and c(5);