diff --git a/cores/Atari2600/zxuno/A2601_zxuno_Ap.ucf b/cores/Atari2600/zxuno/A2601_zxuno_Ap.ucf
new file mode 100644
index 0000000..8cc2583
--- /dev/null
+++ b/cores/Atari2600/zxuno/A2601_zxuno_Ap.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "LED"             LOC="P2"   | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "VGA_R[2]"        LOC="P97"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[1]"        LOC="P95"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[0]"        LOC="P94"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[2]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[1]"        LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[0]"        LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "VGA_HS"          LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "VGA_VS"          LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "NTSC"            LOC="P51"  | IOSTANDARD = LVCMOS33;
+NET "PAL"             LOC="P50"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P98"  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P57"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+                            
+NET "SRAM_nWE"        LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_CLK"         LOC="P80"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MOSI"        LOC="P79"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MISO"        LOC="P81"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P74"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P67"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P59"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P58"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P75"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+
+
diff --git a/cores/Atari2600/zxuno/A2601_zxuno_v2.ucf b/cores/Atari2600/zxuno/A2601_zxuno_v2.ucf
new file mode 100644
index 0000000..bfd1d27
--- /dev/null
+++ b/cores/Atari2600/zxuno/A2601_zxuno_v2.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "LED"             LOC="P10"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "VGA_R[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "VGA_HS"          LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "VGA_VS"          LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "NTSC"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+NET "PAL"             LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P94"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+
+NET "SRAM_nWE"        LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+
+
diff --git a/cores/Atari2600/zxuno/A2601_zxuno_v3.ucf b/cores/Atari2600/zxuno/A2601_zxuno_v3.ucf
new file mode 100644
index 0000000..9c9a0b0
--- /dev/null
+++ b/cores/Atari2600/zxuno/A2601_zxuno_v3.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "LED"             LOC="P10"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "VGA_R[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "VGA_HS"          LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "VGA_VS"          LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "NTSC"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+NET "PAL"             LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P94"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P143" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P134" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P121" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+
+NET "SRAM_nWE"        LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+
+
diff --git a/cores/Atari2600/zxuno/A2601_zxuno_v4.ucf b/cores/Atari2600/zxuno/A2601_zxuno_v4.ucf
new file mode 100644
index 0000000..2de562c
--- /dev/null
+++ b/cores/Atari2600/zxuno/A2601_zxuno_v4.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "LED"             LOC="P11"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "VGA_R[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "VGA_R[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "VGA_G[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "VGA_B[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "VGA_HS"          LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "VGA_VS"          LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "NTSC"            LOC="P66"  | IOSTANDARD = LVCMOS33;
+NET "PAL"             LOC="P67"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P10"  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P94"  | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P99"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P134" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P104" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P100" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+                            
+NET "SRAM_nWE"        LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+
+
diff --git a/cores/Atari2600/zxuno/A6500_summary.html b/cores/Atari2600/zxuno/A6500_summary.html
deleted file mode 100644
index 6a3e9ef..0000000
--- a/cores/Atari2600/zxuno/A6500_summary.html
+++ /dev/null
@@ -1,82 +0,0 @@
-<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
-<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>EP4CE6_A2601 Project Status (11/21/2015 - 19:06:06)</B></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>zxuno_a2601.xise</TD>
-<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
-<TD> No Errors </TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>A6500</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>Programming File Not Generated</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc6slx9-2tqg144</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
-<TD>
-&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
-</TR>
-</TABLE>
-
-
-
-
-
-
-
-
-
-
-
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
-<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/nestor/Projects/zxuno/TCA2601/zxuno/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>sáb nov 21 19:06:05 2015</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/nestor/Projects/zxuno/TCA2601/zxuno/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>sáb nov 21 19:06:06 2015</TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 11/21/2015 - 19:48:16</center>
-</BODY></HTM
\ No newline at end of file
diff --git a/cores/Atari2600/zxuno/ALU_summary.html b/cores/Atari2600/zxuno/ALU_summary.html
deleted file mode 100644
index c4d4cfd..0000000
--- a/cores/Atari2600/zxuno/ALU_summary.html
+++ /dev/null
@@ -1,82 +0,0 @@
-<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
-<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>EP4CE6_A2601 Project Status (11/21/2015 - 19:06:06)</B></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>zxuno_a2601.xise</TD>
-<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
-<TD> No Errors </TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>ALU</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>Programming File Not Generated</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc6slx9-2tqg144</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
-<TD>
-&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
-</TR>
-</TABLE>
-
-
-
-
-
-
-
-
-
-
-
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
-<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/nestor/Projects/zxuno/TCA2601/zxuno/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>sáb nov 21 19:06:05 2015</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/nestor/Projects/zxuno/TCA2601/zxuno/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>sáb nov 21 19:06:06 2015</TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 11/21/2015 - 19:48:16</center>
-</BODY></HTM
\ No newline at end of file
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601.prj b/cores/Atari2600/zxuno/ZXUNO_A2601.prj
new file mode 100644
index 0000000..12241df
--- /dev/null
+++ b/cores/Atari2600/zxuno/ZXUNO_A2601.prj
@@ -0,0 +1,26 @@
+verilog work "ipcore_dir/pll.v"
+vhdl work "../A6500/src/cpu65xx_e.vhd"
+vhdl work "../TIA/src/VGAColorTable.vhd"
+vhdl work "../TIA/src/NTSCLookups.vhd"
+vhdl work "../TIA/src/Common.vhd"
+vhdl work "../A6500/src/cpu65xx_fast.vhd"
+vhdl work "../A2601/src/pacman_dblscan.vhd"
+vhdl work "ipcore_dir/DualPortRAM_Block.vhd"
+vhdl work "../TIA/src/TIA.vhd"
+vhdl work "../CtrlModule/ZPUFlex/RTL/zpupkg.vhd"
+vhdl work "../CtrlModule/CtrlModule/CharROM/CharROM_ROM.vhd"
+vhdl work "../A6532/src/A6532.vhd"
+vhdl work "../A6500/src/A6507.vhd"
+verilog work "ipcore_dir/ramcart.v"
+vhdl work "../CtrlModule/ZPUFlex/RTL/zpu_core_flex.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/spi.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/OnScreenDisplay.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/io_ps2_com.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/interrupt_controller.vhd"
+vhdl work "../CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
+vhdl work "../A2601/src/DeltaSigma.vhd"
+vhdl work "../A2601/src/A2601Core.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/OSD_Overlay.vhd"
+vhdl work "../CtrlModule/CtrlModule/RTL/CtrlModule.vhd"
+vhdl work "../A2601/src/A2601NoFlash.vhd"
+vhdl work "ZXUNO_A2601.vhd"
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601.ut b/cores/Atari2600/zxuno/ZXUNO_A2601.ut
new file mode 100644
index 0000000..dfd4060
--- /dev/null
+++ b/cores/Atari2600/zxuno/ZXUNO_A2601.ut
@@ -0,0 +1,30 @@
+-w
+-g Binary:no
+-g Compress
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601.xst b/cores/Atari2600/zxuno/ZXUNO_A2601.xst
new file mode 100644
index 0000000..90a68b4
--- /dev/null
+++ b/cores/Atari2600/zxuno/ZXUNO_A2601.xst
@@ -0,0 +1,53 @@
+set -tmpdir "projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn ZXUNO_A2601.prj
+-ofn ZXUNO_A2601
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top ZXUNO_A2601
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-sd {"ipcore_dir"  }
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601_bitgen.xwbt b/cores/Atari2600/zxuno/ZXUNO_A2601_bitgen.xwbt
deleted file mode 100644
index 1292203..0000000
--- a/cores/Atari2600/zxuno/ZXUNO_A2601_bitgen.xwbt
+++ /dev/null
@@ -1,8 +0,0 @@
-INTSTYLE=ise
-INFILE=/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/ZXUNO_A2601.ncd
-OUTFILE=/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/ZXUNO_A2601.bit
-FAMILY=Spartan6
-PART=xc6slx9-2tqg144
-WORKINGDIR=/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno
-LICENSE=WebPack
-USER_INFO=211086823_0_0_417
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601_summary.html b/cores/Atari2600/zxuno/ZXUNO_A2601_summary.html
deleted file mode 100644
index 3d6becb..0000000
--- a/cores/Atari2600/zxuno/ZXUNO_A2601_summary.html
+++ /dev/null
@@ -1,78 +0,0 @@
-<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
-<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>ZXUNO_A2601 Project Status</B></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>zxuno_a2601.xise</TD>
-<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>ZXUNO_A2601</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc6slx9-2tqg144</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
-<TD>
-&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
-</TR>
-</TABLE>
-
-
-
-
-
-
-
-
-
-
-
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
-<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 02/10/2016 - 14:28:42</center>
-</BODY></HTML>
\ No newline at end of file
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601_v2.ucf b/cores/Atari2600/zxuno/ZXUNO_A2601_v2.ucf
deleted file mode 100644
index a4f70a6..0000000
--- a/cores/Atari2600/zxuno/ZXUNO_A2601_v2.ucf
+++ /dev/null
@@ -1,93 +0,0 @@
-
-
-NET "VGA_B[0]" LOC = P79;
-NET "VGA_B[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_B[1]" LOC = P80;
-NET "VGA_B[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_B[2]" LOC = P81;
-NET "VGA_B[2]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[0]" LOC = P82;
-NET "VGA_G[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[1]" LOC = P83;
-NET "VGA_G[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[2]" LOC = P84;
-NET "VGA_G[2]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[0]" LOC = P88;
-NET "VGA_R[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[1]" LOC = P92;
-NET "VGA_R[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[2]" LOC = P93;
-NET "VGA_R[2]" IOSTANDARD = LVCMOS33;
-NET "CLOCK_50" LOC = P55;
-NET "CLOCK_50" IOSTANDARD = LVCMOS33;
-NET "SRAM_nWE" LOC = P134;
-NET "SRAM_nWE" IOSTANDARD = LVCMOS33;
-NET "SRAM_nWE" SLEW = FAST;
-NET "VGA_VS" LOC = P85;
-NET "VGA_VS" IOSTANDARD = LVCMOS33;
-NET "VGA_HS" LOC = P87;
-NET "VGA_HS" IOSTANDARD = LVCMOS33;
-NET "LED" LOC = P10;
-NET "LED" IOSTANDARD = LVCMOS33;
-NET "AUDIO_L" LOC = P8;
-NET "AUDIO_L" IOSTANDARD = LVCMOS33;
-NET "AUDIO_R" LOC = P9;
-NET "AUDIO_R" IOSTANDARD = LVCMOS33;
-
-
-NET "P_A" LOC = P6;
-NET "P_A" IOSTANDARD = LVCMOS33;
-NET "P_A" PULLUP;
-NET "P_D" LOC = P1;
-NET "P_D" IOSTANDARD = LVCMOS33;
-NET "P_D" PULLUP;
-NET "P_L" LOC = P2;
-NET "P_L" IOSTANDARD = LVCMOS33;
-NET "P_L" PULLUP;
-NET "P_R" LOC = P5;
-NET "P_R" IOSTANDARD = LVCMOS33;
-NET "P_R" PULLUP;
-NET "P_U" LOC = P142;
-NET "P_U" IOSTANDARD = LVCMOS33;
-NET "P_U" PULLUP;
-
-
-NET "PS2_CLK" LOC = P98;
-NET "PS2_CLK" IOSTANDARD = LVCMOS33;
-NET "PS2_CLK" PULLUP;
-NET "PS2_DAT" LOC = P97;
-NET "PS2_DAT" IOSTANDARD = LVCMOS33;
-NET "PS2_DAT" PULLUP;
-
-
-NET "SPI_MOSI" LOC = P74;
-NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "SPI_MOSI" DRIVE = 8;
-NET "SPI_MOSI" SLEW = FAST;
-NET "SPI_MISO" LOC = P78;
-NET "SPI_MISO" IOSTANDARD = LVCMOS33;
-NET "SPI_MISO" DRIVE = 8;
-NET "SPI_MISO" SLEW = FAST;
-NET "SPI_CLK" LOC = P75;
-NET "SPI_CLK" IOSTANDARD = LVCMOS33;
-NET "SPI_CLK" DRIVE = 8;
-NET "SPI_CLK" SLEW = FAST;
-NET "SPI_CS" LOC = P59;
-NET "SPI_CS" IOSTANDARD = LVCMOS33;
-NET "SPI_CS" DRIVE = 8;
-NET "SPI_CS" SLEW = FAST;
-
-
-NET "PAL" LOC = P66;
-NET "PAL" IOSTANDARD = LVCMOS33;
-NET "NTSC" LOC = P67;
-NET "NTSC" IOSTANDARD = LVCMOS33;
-
-# PlanAhead Generated physical constraints 
-
-NET "P_tr" LOC = P143;
-
-# PlanAhead Generated IO constraints 
-
-NET "P_tr" IOSTANDARD = LVCMOS33;
-NET "P_tr" PULLUP;
diff --git a/cores/Atari2600/zxuno/ZXUNO_A2601_v3.ucf b/cores/Atari2600/zxuno/ZXUNO_A2601_v3.ucf
deleted file mode 100644
index b481ee7..0000000
--- a/cores/Atari2600/zxuno/ZXUNO_A2601_v3.ucf
+++ /dev/null
@@ -1,93 +0,0 @@
-
-
-NET "VGA_B[0]" LOC = P79;
-NET "VGA_B[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_B[1]" LOC = P80;
-NET "VGA_B[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_B[2]" LOC = P81;
-NET "VGA_B[2]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[0]" LOC = P82;
-NET "VGA_G[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[1]" LOC = P83;
-NET "VGA_G[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_G[2]" LOC = P84;
-NET "VGA_G[2]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[0]" LOC = P88;
-NET "VGA_R[0]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[1]" LOC = P92;
-NET "VGA_R[1]" IOSTANDARD = LVCMOS33;
-NET "VGA_R[2]" LOC = P93;
-NET "VGA_R[2]" IOSTANDARD = LVCMOS33;
-NET "CLOCK_50" LOC = P55;
-NET "CLOCK_50" IOSTANDARD = LVCMOS33;
-NET "SRAM_nWE" LOC = P118;
-NET "SRAM_nWE" IOSTANDARD = LVCMOS33;
-NET "SRAM_nWE" SLEW = FAST;
-NET "VGA_VS" LOC = P85;
-NET "VGA_VS" IOSTANDARD = LVCMOS33;
-NET "VGA_HS" LOC = P87;
-NET "VGA_HS" IOSTANDARD = LVCMOS33;
-NET "LED" LOC = P10;
-NET "LED" IOSTANDARD = LVCMOS33;
-NET "AUDIO_L" LOC = P8;
-NET "AUDIO_L" IOSTANDARD = LVCMOS33;
-NET "AUDIO_R" LOC = P9;
-NET "AUDIO_R" IOSTANDARD = LVCMOS33;
-
-
-NET "P_A" LOC = P2;
-NET "P_A" IOSTANDARD = LVCMOS33;
-NET "P_A" PULLUP;
-NET "P_D" LOC = P5;
-NET "P_D" IOSTANDARD = LVCMOS33;
-NET "P_D" PULLUP;
-NET "P_L" LOC = P6;
-NET "P_L" IOSTANDARD = LVCMOS33;
-NET "P_L" PULLUP;
-NET "P_R" LOC = P7;
-NET "P_R" IOSTANDARD = LVCMOS33;
-NET "P_R" PULLUP;
-NET "P_U" LOC = P1;
-NET "P_U" IOSTANDARD = LVCMOS33;
-NET "P_U" PULLUP;
-
-
-NET "PS2_CLK" LOC = P98;
-NET "PS2_CLK" IOSTANDARD = LVCMOS33;
-NET "PS2_CLK" PULLUP;
-NET "PS2_DAT" LOC = P97;
-NET "PS2_DAT" IOSTANDARD = LVCMOS33;
-NET "PS2_DAT" PULLUP;
-
-
-NET "SPI_MOSI" LOC = P74;
-NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "SPI_MOSI" DRIVE = 8;
-NET "SPI_MOSI" SLEW = FAST;
-NET "SPI_MISO" LOC = P78;
-NET "SPI_MISO" IOSTANDARD = LVCMOS33;
-NET "SPI_MISO" DRIVE = 8;
-NET "SPI_MISO" SLEW = FAST;
-NET "SPI_CLK" LOC = P75;
-NET "SPI_CLK" IOSTANDARD = LVCMOS33;
-NET "SPI_CLK" DRIVE = 8;
-NET "SPI_CLK" SLEW = FAST;
-NET "SPI_CS" LOC = P59;
-NET "SPI_CS" IOSTANDARD = LVCMOS33;
-NET "SPI_CS" DRIVE = 8;
-NET "SPI_CS" SLEW = FAST;
-
-
-NET "PAL" LOC = P66;
-NET "PAL" IOSTANDARD = LVCMOS33;
-NET "NTSC" LOC = P67;
-NET "NTSC" IOSTANDARD = LVCMOS33;
-
-# PlanAhead Generated physical constraints 
-
-NET "P_tr" LOC = P39;
-
-# PlanAhead Generated IO constraints 
-
-NET "P_tr" IOSTANDARD = LVCMOS33;
-NET "P_tr" PULLUP;
diff --git a/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/cg.xmsgs b/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/cg.xmsgs
deleted file mode 100644
index 5fa756f..0000000
--- a/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/cg.xmsgs
+++ /dev/null
@@ -1,27 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated
-     by the Xilinx ISE software.  Any direct editing or
-     changes made to this file may result in unpredictable
-     behavior or data corruption.  It is strongly advised that
-     users do not edit the contents of this file. -->
-<messages>
-<msg type="info" file="sim" num="172" delta="old" >Generating IP...
-</msg>
-
-<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;DualPortRAM_Block&apos; already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
-
-<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;DualPortRAM_Block&apos;...</arg>
-</msg>
-
-<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/ipcore_dir/tmp/_cg/DualPortRAM_Block/doc/blk_mem_gen_v7_3_vinfo.html with file from view xilinx_documentation</arg>
-</msg>
-
-<msg type="info" file="sim" num="949" delta="new" >Finished generation of ASY schematic symbol.
-</msg>
-
-<msg type="info" file="sim" num="948" delta="new" >Finished FLIST file generation.
-</msg>
-
-</messages>
-
diff --git a/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/pn_parser.xmsgs b/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index a38ed26..0000000
--- a/cores/Atari2600/zxuno/ipcore_dir/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated   -->
-<!--     by the Xilinx ISE software.  Any direct editing or        -->
-<!--     changes made to this file may result in unpredictable     -->
-<!--     behavior or data corruption.  It is strongly advised that -->
-<!--     users do not edit the contents of this file.              -->
-<!--                                                               -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
-
-<messages>
-</messages>
-
diff --git a/cores/Atari2600/zxuno/ipcore_dir/pll.ncf b/cores/Atari2600/zxuno/ipcore_dir/pll.ncf
deleted file mode 100644
index f4a46ea..0000000
--- a/cores/Atari2600/zxuno/ipcore_dir/pll.ncf
+++ /dev/null
@@ -1,59 +0,0 @@
-# file: pll.ucf
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-# Input clock periods. These duplicate the values entered for the
-#  input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints 
-
-
diff --git a/cores/Atari2600/zxuno/iseconfig/EP4CE6_A2601.xreport b/cores/Atari2600/zxuno/iseconfig/EP4CE6_A2601.xreport
deleted file mode 100644
index b975d7f..0000000
--- a/cores/Atari2600/zxuno/iseconfig/EP4CE6_A2601.xreport
+++ /dev/null
@@ -1,215 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
-  <DateModified>2015-11-21T13:38:31</DateModified>
-  <ModuleName>ZXUNO_A2601</ModuleName>
-  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
-  <SavedFilePath>/home/nestor/Projects/zxuno/TCA2601/zxuno/iseconfig/EP4CE6_A2601.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>/home/nestor/Projects/zxuno/TCA2601/zxuno</ImplementationReportsDirectory>
-  <DateInitialized>2015-11-21T13:38:30</DateInitialized>
-  <EnableMessageFiltering>true</EnableMessageFiltering>
- </header>
- <body>
-  <viewgroup label="Design Overview" >
-   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ZXUNO_A2601_summary.html" label="Summary" >
-    <toc-item title="Design Overview" target="Design Overview" />
-    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
-    <toc-item title="Performance Summary" target="Performance Summary" />
-    <toc-item title="Failing Constraints" target="Failing Constraints" />
-    <toc-item title="Detailed Reports" target="Detailed Reports" />
-   </view>
-   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ZXUNO_A2601_envsettings.html" label="System Settings" />
-   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ZXUNO_A2601_map.xrpt" label="IOB Properties" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ZXUNO_A2601_map.xrpt" label="Control Set Information" />
-   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ZXUNO_A2601_map.xrpt" label="Module Level Utilization" />
-   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ZXUNO_A2601.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
-   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ZXUNO_A2601_par.xrpt" label="Pinout Report" />
-   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ZXUNO_A2601_par.xrpt" label="Clock Report" />
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ZXUNO_A2601.twx" label="Static Timing" />
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ZXUNO_A2601_html/fit/report.htm" label="CPLD Fitter Report" />
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ZXUNO_A2601_html/tim/report.htm" label="CPLD Timing Report" />
-  </viewgroup>
-  <viewgroup label="XPS Errors and Warnings" >
-   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
-   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
-   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
-  </viewgroup>
-  <viewgroup label="XPS Reports" >
-   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
-   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
-   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
-   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ZXUNO_A2601.log" label="System Log File" />
-  </viewgroup>
-  <viewgroup label="Errors and Warnings" >
-   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
-   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
-   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
-   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
-   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
-   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
-   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
-   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
-   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
-   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
-   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
-  </viewgroup>
-  <viewgroup label="Detailed Reports" >
-   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ZXUNO_A2601.syr" label="Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
-    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
-    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
-    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
-    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
-    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
-    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
-    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
-    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
-    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
-    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
-    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
-    <toc-item title="Partition Report" target="   Partition Report     " />
-    <toc-item title="Final Report" target="   Final Report   " />
-    <toc-item title="Design Summary" target="   Design Summary   " />
-    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
-    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
-    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
-    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
-    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
-    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
-    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
-    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
-    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
-   </view>
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.srr" label="Synplify Report" />
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.prec_log" label="Precision Report" />
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="ZXUNO_A2601.bld" label="Translation Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Command Line" target="Command Line:" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
-   </view>
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601_map.mrp" label="Map Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
-    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
-    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
-    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
-    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
-    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
-    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
-    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
-    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
-    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
-    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
-    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
-    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.par" label="Place and Route Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
-    <toc-item title="Router Information" target="Starting Router" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Clock Report" target="Generating Clock Report" />
-    <toc-item title="Timing Results" target="Timing Score:" />
-    <toc-item title="Final Summary" target="Peak Memory Usage:" />
-   </view>
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.twr" label="Post-PAR Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.rpt" label="CPLD Fitter Report (Text)" >
-    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
-    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
-    <toc-item title="Pin Resources" target="** Pin Resources **" />
-    <toc-item title="Global Resources" target="** Global Control Resources **" />
-   </view>
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.tim" label="CPLD Timing Report (Text)" >
-    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
-    <toc-item title="Performance Summary" target="Performance Summary:" />
-   </view>
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="ZXUNO_A2601.pwr" label="Power Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Power summary" target="Power summary" />
-    <toc-item title="Thermal summary" target="Thermal summary" />
-   </view>
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.bgn" label="Bitgen Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
-    <toc-item title="Final Summary" target="DRC detected" />
-   </view>
-  </viewgroup>
-  <viewgroup label="Secondary Reports" >
-   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ZXUNO_A2601_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ZXUNO_A2601_translate.nlf" label="Post-Translate Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ZXUNO_A2601_map.map" label="Map Log File" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Design Information" target="Design Information" />
-    <toc-item title="Design Summary" target="Design Summary" />
-   </view>
-   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_preroute.twr" label="Post-Map Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ZXUNO_A2601_map.nlf" label="Post-Map Simulation Model Report" />
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_map.psr" label="Physical Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ZXUNO_A2601_pad.txt" label="Pad Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ZXUNO_A2601.unroutes" label="Unroutes Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_preroute.tsi" label="Post-Map Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.grf" label="Guide Results Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.dly" label="Asynchronous Delay Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.clk_rgn" label="Clock Region Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.tsi" label="Post-Place and Route Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ZXUNO_A2601_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_sta.nlf" label="Primetime Netlist Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.ibs" label="IBIS Model" >
-    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
-    <toc-item title="Component" target="Component " />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.lck" label="Back-annotate Pin Report" >
-    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
-    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.lpc" label="Locked Pin Constraints" >
-    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
-    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
-   </view>
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ZXUNO_A2601_timesim.nlf" label="Post-Fit Simulation Model Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
-  </viewgroup>
- </body>
-</report-views>
diff --git a/cores/Atari2600/zxuno/iseconfig/ZXUNO_A2601.xreport b/cores/Atari2600/zxuno/iseconfig/ZXUNO_A2601.xreport
deleted file mode 100644
index 62e0761..0000000
--- a/cores/Atari2600/zxuno/iseconfig/ZXUNO_A2601.xreport
+++ /dev/null
@@ -1,215 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
-  <DateModified>2016-02-10T14:28:42</DateModified>
-  <ModuleName>ZXUNO_A2601</ModuleName>
-  <SummaryTimeStamp>2016-02-10T14:27:58</SummaryTimeStamp>
-  <SavedFilePath>/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/iseconfig/ZXUNO_A2601.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/</ImplementationReportsDirectory>
-  <DateInitialized>2015-11-21T19:51:54</DateInitialized>
-  <EnableMessageFiltering>true</EnableMessageFiltering>
- </header>
- <body>
-  <viewgroup label="Design Overview" >
-   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ZXUNO_A2601_summary.html" label="Summary" >
-    <toc-item title="Design Overview" target="Design Overview" />
-    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
-    <toc-item title="Performance Summary" target="Performance Summary" />
-    <toc-item title="Failing Constraints" target="Failing Constraints" />
-    <toc-item title="Detailed Reports" target="Detailed Reports" />
-   </view>
-   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ZXUNO_A2601_envsettings.html" label="System Settings" />
-   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ZXUNO_A2601_map.xrpt" showConstraints="0" label="IOB Properties" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ZXUNO_A2601_map.xrpt" label="Control Set Information" />
-   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ZXUNO_A2601_map.xrpt" label="Module Level Utilization" />
-   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ZXUNO_A2601.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
-   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ZXUNO_A2601_par.xrpt" showConstraints="0" label="Pinout Report" />
-   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ZXUNO_A2601_par.xrpt" showConstraints="0" label="Clock Report" />
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ZXUNO_A2601.twx" label="Static Timing" />
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ZXUNO_A2601_html/fit/report.htm" label="CPLD Fitter Report" />
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ZXUNO_A2601_html/tim/report.htm" label="CPLD Timing Report" />
-  </viewgroup>
-  <viewgroup label="XPS Errors and Warnings" >
-   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
-   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
-   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
-  </viewgroup>
-  <viewgroup label="XPS Reports" >
-   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
-   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
-   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
-   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ZXUNO_A2601.log" label="System Log File" />
-  </viewgroup>
-  <viewgroup label="Errors and Warnings" >
-   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
-   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
-   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
-   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
-   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
-   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
-   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
-   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
-   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
-   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
-   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
-  </viewgroup>
-  <viewgroup label="Detailed Reports" >
-   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ZXUNO_A2601.syr" label="Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
-    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
-    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
-    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
-    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
-    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
-    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
-    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
-    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
-    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
-    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
-    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
-    <toc-item title="Partition Report" target="   Partition Report     " />
-    <toc-item title="Final Report" target="   Final Report   " />
-    <toc-item title="Design Summary" target="   Design Summary   " />
-    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
-    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
-    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
-    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
-    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
-    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
-    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
-    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
-    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
-   </view>
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.srr" label="Synplify Report" />
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.prec_log" label="Precision Report" />
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="ZXUNO_A2601.bld" label="Translation Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Command Line" target="Command Line:" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
-   </view>
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601_map.mrp" label="Map Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
-    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
-    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
-    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
-    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
-    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
-    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
-    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
-    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
-    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
-    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
-    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
-    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.par" label="Place and Route Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
-    <toc-item title="Router Information" target="Starting Router" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Clock Report" target="Generating Clock Report" />
-    <toc-item title="Timing Results" target="Timing Score:" />
-    <toc-item title="Final Summary" target="Peak Memory Usage:" />
-   </view>
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.twr" label="Post-PAR Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.rpt" label="CPLD Fitter Report (Text)" >
-    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
-    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
-    <toc-item title="Pin Resources" target="** Pin Resources **" />
-    <toc-item title="Global Resources" target="** Global Control Resources **" />
-   </view>
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ZXUNO_A2601.tim" label="CPLD Timing Report (Text)" >
-    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
-    <toc-item title="Performance Summary" target="Performance Summary:" />
-   </view>
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="ZXUNO_A2601.pwr" label="Power Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Power summary" target="Power summary" />
-    <toc-item title="Thermal summary" target="Thermal summary" />
-   </view>
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ZXUNO_A2601.bgn" label="Bitgen Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
-    <toc-item title="Final Summary" target="DRC detected" />
-   </view>
-  </viewgroup>
-  <viewgroup label="Secondary Reports" >
-   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ZXUNO_A2601_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ZXUNO_A2601_translate.nlf" label="Post-Translate Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ZXUNO_A2601_map.map" label="Map Log File" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Design Information" target="Design Information" />
-    <toc-item title="Design Summary" target="Design Summary" />
-   </view>
-   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_preroute.twr" label="Post-Map Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ZXUNO_A2601_map.nlf" label="Post-Map Simulation Model Report" />
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_map.psr" label="Physical Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ZXUNO_A2601_pad.txt" label="Pad Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ZXUNO_A2601.unroutes" label="Unroutes Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_preroute.tsi" label="Post-Map Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.grf" label="Guide Results Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.dly" label="Asynchronous Delay Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.clk_rgn" label="Clock Region Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.tsi" label="Post-Place and Route Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ZXUNO_A2601_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601_sta.nlf" label="Primetime Netlist Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.ibs" label="IBIS Model" >
-    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
-    <toc-item title="Component" target="Component " />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.lck" label="Back-annotate Pin Report" >
-    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
-    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ZXUNO_A2601.lpc" label="Locked Pin Constraints" >
-    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
-    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
-   </view>
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ZXUNO_A2601_timesim.nlf" label="Post-Fit Simulation Model Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
-  </viewgroup>
- </body>
-</report-views>
diff --git a/cores/Atari2600/zxuno/iseconfig/filter.filter b/cores/Atari2600/zxuno/iseconfig/filter.filter
deleted file mode 100644
index d47ae35..0000000
--- a/cores/Atari2600/zxuno/iseconfig/filter.filter
+++ /dev/null
@@ -1,7 +0,0 @@
-<!--                                                                                                 -->
-<!--This is an internal file that has been generated by the Xilinx ISE software.  Any direct         -->
-<!--editing of this file may result in data corruption or in unpredictable behavior.  It is strongly -->
-<!--advised that users do not directly edit the contents of this file.                               -->
-<!--                                                                                                 -->
-<filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
-</filters>
diff --git a/cores/Atari2600/zxuno/iseconfig/zxuno_a2601.projectmgr b/cores/Atari2600/zxuno/iseconfig/zxuno_a2601.projectmgr
deleted file mode 100644
index ca1f0e7..0000000
--- a/cores/Atari2600/zxuno/iseconfig/zxuno_a2601.projectmgr
+++ /dev/null
@@ -1,128 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<!--This is an ISE project configuration file.-->
-<!--It holds project specific layout data for the projectmgr plugin.-->
-<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
-<Project version="2" owner="projectmgr" name="zxuno_a2601" >
-   <!--This is an ISE project configuration file.-->
-   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
-      <ClosedNodes>
-         <ClosedNodesVersion>2</ClosedNodesVersion>
-         <ClosedNode>/A6500 - arch |home|nestor|Projects|zxuno|TCA2601|A6500|src|A6500.vhd</ClosedNode>
-         <ClosedNode>/A6502 - arch |home|nestor|Projects|zxuno|TCA2601|A6500|src|A6502.vhd/cpu_A6500 - A6500 - arch</ClosedNode>
-         <ClosedNode>/EP4CE6_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/cpu_A6507 - A6507 - arch</ClosedNode>
-         <ClosedNode>/EP4CE6_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/riot_A6532 - A6532 - arch</ClosedNode>
-         <ClosedNode>/EP4CE6_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch/bl - ball - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch/m0 - missile - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch/m1 - missile - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch/p0 - player - arch</ClosedNode>
-         <ClosedNode>/ZXUNO_A2601 - rtl |home|nestor|Projects|zxuno|TCA2601|zxuno|ZXUNO_A2601.vhd/a2601Instance - A2601NoFlash - arch/ms_A2601 - A2601 - arch/tia_inst - TIA - arch/p1 - player - arch</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem>ZXUNO_A2601 - rtl (/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/ZXUNO_A2601.vhd)</SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >39</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029b000000020000000000000000000000000200000064ffffffff0000008100000003000000020000029b0000000100000003000000000000000100000003</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>ZXUNO_A2601 - rtl (/home/nestor/Projects/zxuno/git/zxuno_a2600/TCA2601/zxuno/ZXUNO_A2601.vhd)</CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>Configure Target Device</ClosedNode>
-         <ClosedNode>Design Utilities</ClosedNode>
-         <ClosedNode>Implement Design</ClosedNode>
-         <ClosedNode>Synthesize - XST</ClosedNode>
-         <ClosedNode>User Constraints</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem/>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000128000000010000000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem/>
-   </ItemView>
-   <ItemView guiview="File" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000370000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b600000001000000000000002900000001000000000000008400000001000000000000020d0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>A2601Core.vhd</CurrentItem>
-   </ItemView>
-   <ItemView guiview="Library" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000125000000010001000100000000000000000000000064ffffffff000000810000000000000001000001250000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>work</CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>CORE Generator</ClosedNode>
-         <ClosedNode>Configure Target Device</ClosedNode>
-         <ClosedNode>Design Utilities</ClosedNode>
-         <ClosedNode>Implement Design</ClosedNode>
-         <ClosedNode>Synthesize - XST</ClosedNode>
-         <ClosedNode>User Constraints</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem>Generate Programming File</SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012a0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>Generate Programming File</CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" />
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem/>
-   </ItemView>
-   <SourceProcessView>000000ff00000000000000020000014a0000011b01000000040100000002</SourceProcessView>
-   <CurrentView>Implementation</CurrentView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>CORE Generator</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem></SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012a0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem></CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" ></ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem></CurrentItem>
-   </ItemView>
-</Project>
diff --git a/cores/Atari2600/zxuno/make.bat b/cores/Atari2600/zxuno/make.bat
new file mode 100644
index 0000000..3313028
--- /dev/null
+++ b/cores/Atari2600/zxuno/make.bat
@@ -0,0 +1,8 @@
+SET machine=zxuno_a2601
+SET ruta_ucf=a2601
+SET ruta_bat=..\..\
+call %ruta_bat%genxst.bat
+call %ruta_bat%generar.bat v2
+call %ruta_bat%generar.bat v3
+call %ruta_bat%generar.bat v4
+call %ruta_bat%generar.bat Ap
diff --git a/cores/Atari2600/zxuno/par_usage_statistics.html b/cores/Atari2600/zxuno/par_usage_statistics.html
deleted file mode 100644
index b52897a..0000000
--- a/cores/Atari2600/zxuno/par_usage_statistics.html
+++ /dev/null
@@ -1,32 +0,0 @@
-<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
-<xtag-section name="ParStatistics">
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>3005</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>11992</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>11992</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>10739</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>3.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>9.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>10.2 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>16.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>17.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>17.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>17.7 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>18.3 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>9.1</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>5.6092</xtag-par-property-value></TD></TR>
-</xtag-section>
-</TABLE>
diff --git a/cores/Atari2600/zxuno/zxuno_a2601.gise b/cores/Atari2600/zxuno/zxuno_a2601.gise
deleted file mode 100644
index d59ceb7..0000000
--- a/cores/Atari2600/zxuno/zxuno_a2601.gise
+++ /dev/null
@@ -1,39 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="zxuno_a2601.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_NCD" xil_pn:name="ZXUNO_A2601_guide.ncd" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ipcore_dir/DualPortRAM_Block.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="ipcore_dir/pll.veo" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ipcore_dir/ramcart.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="ipcore_dir/ramcart.veo" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1455109967" xil_pn:in_ck="668993404727884190" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1455109967">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/cores/Atari2600/zxuno/zxuno_a2601.xise b/cores/Atari2600/zxuno/zxuno_a2601.xise
deleted file mode 100644
index a72bdf3..0000000
--- a/cores/Atari2600/zxuno/zxuno_a2601.xise
+++ /dev/null
@@ -1,471 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="ZXUNO_A2601.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
-    </file>
-    <file xil_pn:name="../A2601/src/A2601NoFlash.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
-    </file>
-    <file xil_pn:name="../A2601/src/A2601Core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
-    </file>
-    <file xil_pn:name="../A2601/src/DeltaSigma.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
-    </file>
-    <file xil_pn:name="../A2601/src/pacman_dblscan.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
-    </file>
-    <file xil_pn:name="../A6500/src/A6507.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-    </file>
-    <file xil_pn:name="../A6500/src/cpu65xx_e.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="../A6500/src/cpu65xx_fast.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="../A6532/src/A6532.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-    </file>
-    <file xil_pn:name="../TIA/src/Common.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="../TIA/src/NTSCLookups.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="../TIA/src/TIA.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
-    </file>
-    <file xil_pn:name="../TIA/src/VGAColorTable.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/ZPUFlex/RTL/zpu_core_flex.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/ZPUFlex/RTL/zpupkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/CharROM/CharROM_ROM.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/CtrlModule.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/interrupt_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/io_ps2_com.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/OnScreenDisplay.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/OSD_Overlay.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/pll.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ramcart.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
-    </file>
-    <file xil_pn:name="../CtrlModule/CtrlModule/RTL/spi.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
-    </file>
-    <file xil_pn:name="ZXUNO_A2601_v3.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/DualPortRAM_Block.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/pll.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ramcart.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ZXUNO_A2601|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ZXUNO_A2601.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ZXUNO_A2601" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="ZXUNO_A2601" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ZXUNO_A2601_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ZXUNO_A2601_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ZXUNO_A2601_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ZXUNO_A2601_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target UCF File Name" xil_pn:value="ZXUNO_A2601.ucf" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="zxuno_a2601" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-11-21T13:16:11" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF4E5219C6991D4B14C66C6F1DE53DB4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>