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wip

This commit is contained in:
byrtolet 2018-10-19 22:20:14 +03:00
parent 0c046f4fed
commit 3586e47703
12 changed files with 1673 additions and 212 deletions
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1
.gitignore vendored
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@ -52,3 +52,4 @@ cores/Oric/build/out.my
cores/Oric/source/_impact.cmd
cores/Oric/source/_impact.log
cores/Oric/build/oric.v4_my.bit

3
cores/Oric/source/controller_8dos.vhd
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@ -73,9 +73,8 @@ begin
begin
if (rising_edge(CLK_24)) then
if (RESETn = '0') then
IMAGE_NUMBER <= "0000000000";
IMAGE_NUMBER <= "0000000001";
else
IMAGE_UP_old <= IMAGE_UP_cur;
IMAGE_UP_cur <= IMAGE_UP;
IMAGE_DOWN_old <= IMAGE_DOWN_cur;

1212
cores/Oric/source/diff Normal file
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19
cores/Oric/source/disk_ii.vhd
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@ -293,21 +293,20 @@ begin
'0'; -- C08C
write_d_out:process(CLK)
begin
D_OUT <= (others => '0');
if rising_edge(CLK) then
if read_disk = '1' and track_byte_addr(0) = '0' and TRACK_GOOD = '1' and DRIVE_ON ='1' then
if read_disk = '1' and track_byte_addr(0) = '0' and TRACK_GOOD = '1' and DRIVE_ON ='1' then
D_OUT <= ram_do;
else if (q6 = '1') then
if (DRIVE_ON = '1')then
D_OUT <= x"20";
else
D_OUT <= x"00";
end if;
end if;
elsif (q6 = '1') and A(0) = '0' and DRIVE_ON = '1' then
D_OUT <= x"20";
elsif (q6 = '1') and A(0) = '0' and DRIVE_ON = '0' then
D_OUT <= x"00";
elsif (q7 = '1') and (q6 = '0') and A(0) = '0' then
D_OUT <= x"80";
else
D_OUT <= x"00";
end if;
end if;
end process;
track_addr <= track_byte_addr(14 downto 1);

BIN
cores/Oric/source/new8dos.rom Normal file
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1
cores/Oric/source/oric_zxuno_my.ucf
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@ -134,6 +134,7 @@ NET "SD_CLK" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "disk_a_on" LOC="P35" | IOSTANDARD = LVCMOS25;
NET "track_ok" LOC="P34" | IOSTANDARD = LVCMOS25;
NET "out_MAPn" LOC="P33" | IOSTANDARD = LVCMOS25;
NET "image_buton_up" LOC="P112" | IOSTANDARD = LVCMOS25;
NET "image_buton_down" LOC="P114" | IOSTANDARD = LVCMOS25;
#PIN "controller8dos/sdcard_interface/Mmux_spi_clk11.A4" CLOCK_DEDICATED_ROUTE = FALSE;

118
cores/Oric/source/oric_zxuno_v4_my.ucf Normal file
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@ -0,0 +1,118 @@
#UCF for ZX-UNO
NET "CLK_50" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET O_VIDEO_R(2) LOC="P81" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS33;
# Audio
NET "AUDIO_OUT" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "AUDIO_OUT2" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "K7_TAPEOUT" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEIN" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "PS2CLK1" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PS2DAT1" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET SRAM_ADDR<0> LOC="P141" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<1> LOC="P139" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<2> LOC="P137" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<3> LOC="P134" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<4> LOC="P133" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<5> LOC="P120" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<6> LOC="P118" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<7> LOC="P116" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<8> LOC="P114" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<9> LOC="P112" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<10> LOC="P104" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<11> LOC="P102" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<12> LOC="P101" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<13> LOC="P100" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<14> LOC="P111" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<15> LOC="P131" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<16> LOC="P138" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<17> LOC="P140" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<18> LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(0) LOC="P132" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(1) LOC="P127" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(2) LOC="P124" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(3) LOC="P123" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(4) LOC="P115" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(5) LOC="P117" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(6) LOC="P119" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(7) LOC="P126" | IOSTANDARD = LVCMOS33;
NET SRAM_WE_N LOC="P121" | IOSTANDARD = LVCMOS33;
NET SRAM_CS_N LOC="P144" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
NET "SD_DAT" LOC="P78" | IOSTANDARD = LVCMOS33;
NET "SD_DAT3" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "SD_CMD" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "SD_CLK" LOC="P75" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Switch
#NET "I_RESET" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "I_NMI" LOC="P15" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "image_buton_up" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "image_buton_down" LOC="P15" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;
# NET D_VIDEO_R(2) LOC="P51" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(1) LOC="P50" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(0) LOC="P47" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(2) LOC="P40" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(1) LOC="P35" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(0) LOC="P33" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(2) LOC="P23" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(1) LOC="P17" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(0) LOC="P24" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_HSYNC LOC="P57" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VSYNC LOC="P58" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
PIN "inst_buf3.O" CLOCK_DEDICATED_ROUTE = FALSE;

116
cores/Oric/source/oric_zxuno_v4_my.ucf~ Normal file
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@ -0,0 +1,116 @@
#UCF for ZX-UNO
NET "CLK_50" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET O_VIDEO_R(2) LOC="P81" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS33;
# Audio
NET "AUDIO_OUT" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "AUDIO_OUT2" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "K7_TAPEOUT" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEIN" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "PS2CLK1" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PS2DAT1" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET SRAM_ADDR<0> LOC="P141" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<1> LOC="P139" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<2> LOC="P137" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<3> LOC="P134" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<4> LOC="P133" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<5> LOC="P120" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<6> LOC="P118" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<7> LOC="P116" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<8> LOC="P114" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<9> LOC="P112" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<10> LOC="P104" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<11> LOC="P102" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<12> LOC="P101" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<13> LOC="P100" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<14> LOC="P111" | IOSTANDARD = LVCMOS33;
NET SRAM_ADDR<15> LOC="P131" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<16> LOC="P138" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<17> LOC="P140" | IOSTANDARD = LVCMOS33;
#NET SRAM_ADDR<18> LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(0) LOC="P132" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(1) LOC="P127" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(2) LOC="P124" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(3) LOC="P123" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(4) LOC="P115" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(5) LOC="P117" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(6) LOC="P119" | IOSTANDARD = LVCMOS33;
NET SRAM_DQ(7) LOC="P126" | IOSTANDARD = LVCMOS33;
NET SRAM_WE_N LOC="P121" | IOSTANDARD = LVCMOS33;
NET SRAM_CS_N LOC="P144" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
NET "SD_DAT" LOC="P78" | IOSTANDARD = LVCMOS33;
NET "SD_DAT3" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "SD_CMD" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "SD_CLK" LOC="P75" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Switch
NET "I_RESET" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "I_NMI" LOC="P15" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;
# NET D_VIDEO_R(2) LOC="P51" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(1) LOC="P50" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(0) LOC="P47" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(2) LOC="P40" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(1) LOC="P35" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(0) LOC="P33" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(2) LOC="P23" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(1) LOC="P17" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(0) LOC="P24" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_HSYNC LOC="P57" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
# NET D_VSYNC LOC="P58" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
PIN "inst_buf3.O" CLOCK_DEDICATED_ROUTE = FALSE;

294
cores/Oric/source/oricatmos.vhd
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@ -23,7 +23,6 @@ use unisim.vcomponents.all;
entity ORIC is
port (
I_RESET : in std_logic;
-- Keyboard
PS2CLK1 : in std_logic;
@ -35,9 +34,9 @@ entity ORIC is
AUDIO_OUT2 : out std_logic;
-- VGA out
O_VIDEO_R : out std_logic_vector(2 downto 2); --Q
O_VIDEO_G : out std_logic_vector(2 downto 2); --Q
O_VIDEO_B : out std_logic_vector(2 downto 2); --Q
O_VIDEO_R : out std_logic_vector(2 downto 0); --Q
O_VIDEO_G : out std_logic_vector(2 downto 0); --Q
O_VIDEO_B : out std_logic_vector(2 downto 0); --Q
O_HSYNC : out std_logic;
O_VSYNC : out std_logic;
@ -56,7 +55,8 @@ entity ORIC is
-- K7_REMOTE : out std_logic;
-- K7_AUDIOOUT : out std_logic;
I_NMI : in std_logic;
-- I_RESET : in std_logic;
-- I_NMI : in std_logic;
-- PRINTER
-- PRT_DATA : inout std_logic_vector(7 downto 0);
-- PRT_STR : out std_logic; -- strobe
@ -72,6 +72,12 @@ entity ORIC is
O_NTSC : out std_logic; --Q
O_PAL : out std_logic; --Q
-- SRAM
SRAM_DQ : inout std_logic_vector(7 downto 0); -- Data bus 8 Bits
SRAM_ADDR : out std_logic_vector(15 downto 0); -- Address bus 20 Bits
SRAM_WE_N : out std_logic; -- Write Enable
SRAM_CS_N : out std_logic;
--sd card controller
SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut" //misoP117
@ -79,17 +85,18 @@ entity ORIC is
SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"mosiP119
SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK" //sckP115
disk_a_on : out std_logic; -- 0 when disk is active else 1
track_ok : out std_logic; -- 0 when disk is active else 1
out_MAPn : out std_logic;
-- disk_a_on : out std_logic; -- 0 when disk is active else 1
-- track_ok : out std_logic; -- 0 when disk is active else 1
-- out_MAPn : out std_logic;
image_buton_up : in std_logic;
image_buton_down: in std_logic;
image_buton_down : in std_logic; -- 0 when disk is active else 1
-- image_buton_down: in std_logic;
-- Clk master
CLK_50 : in std_logic; -- MASTER CLK
CLK_50 : in std_logic -- MASTER CLK
-- 7 segment led indicators
segment : out std_logic_vector( 7 downto 0);
position : out std_logic_vector( 7 downto 0)
-- segment : out std_logic_vector( 7 downto 0);
-- position : out std_logic_vector( 7 downto 0)
);
end;
@ -98,7 +105,9 @@ architecture RTL of ORIC is
-- Resets
signal loc_reset_n : std_logic; --active low
signal I_RESET : std_logic := '1';
signal I_NMI : std_logic := '1';
-- Internal clocks
signal CLKFB : std_logic := '0';
signal clk24 : std_logic := '0';
@ -149,6 +158,7 @@ architecture RTL of ORIC is
signal PSG_OUT : std_logic_vector( 7 downto 0);
signal vaudio_out : std_logic_vector(7 downto 0);
signal audio_out_tmp : std_logic := '0';
-- ULA
@ -210,6 +220,11 @@ architecture RTL of ORIC is
signal image_buton_up_db : std_logic;
signal image_buton_down_db: std_logic;
-- previous were ports
signal disk_a_on : std_logic; -- 0 when disk is active else 1
signal track_ok : std_logic; -- 0 when disk is active else 1
begin
-----------------------------------------------
@ -322,16 +337,24 @@ begin
ad(15 downto 0) <= ula_AD_SRAM when ula_phi2 = '0' else CPU_ADDR(15 downto 0);
-- ad(17 downto 16) <= "00";
inst_ram : entity work.ram48k
port map(
clk => clk24,
cs => ula_CE_SRAM,
oe => ula_OE_SRAM,
we => ula_WE_SRAM,
addr => ad,
di => CPU_DO,
do => SRAM_DO
);
SRAM_DQ(7 downto 0) <= (others => '0') when loc_reset_n = '0' else CPU_DO when ula_WE_SRAM = '1' else (others => 'Z'); --added Data part of SRAM init when reset to jump disk boot code.
SRAM_ADDR(15 downto 0) <= ad(15 downto 0);
SRAM_WE_N <= '1' when loc_reset_n = '0' else not ula_WE_SRAM;
SRAM_CS_N <= '1' when loc_reset_n = '0' else not ula_CE_SRAM;
SRAM_DO <= SRAM_DQ when ula_CE_SRAM = '1' and ula_WE_SRAM = '0' else (others => '0');
-- inst_ram : entity work.ram48k
-- port map(
-- clk => clk24,
-- cs => ula_CE_SRAM,
-- oe => ula_OE_SRAM,
-- we => ula_WE_SRAM,
-- addr => ad,
-- di => CPU_DO,
-- do => SRAM_DO
-- );
------------------------------------------------------------
-- ULA
@ -385,60 +408,60 @@ begin
-----------------------------------------------------------------
-- total resolution 354x312, active resolution 240x224, H 15625 Hz, V 50.08 Hz
-- take note: the values below are relative to the CLK period not standard VGA clock period
inst_scan_conv : entity work.VGA_SCANCONV
generic map (
-- mark active area of input video
cstart => 65, -- composite sync start
clength => 240, -- composite sync length
-- inst_scan_conv : entity work.VGA_SCANCONV
-- generic map (
-- -- mark active area of input video
-- cstart => 65, -- composite sync start
-- clength => 240, -- composite sync length
-- output video timing
hA => 10, -- h front porch
hB => 46, -- h sync
hC => 24, -- h back porch
hD => 240, -- visible video
-- -- output video timing
-- hA => 10, -- h front porch
-- hB => 46, -- h sync
-- hC => 24, -- h back porch
-- hD => 240, -- visible video
vA => 40, -- v front porch (not used)
vB => 2, -- v sync
vC => 2, -- v back porch
vD => 240, -- visible video
-- -- vA => 40, -- v front porch (not used)
-- vB => 2, -- v sync
-- vC => 2, -- v back porch
-- vD => 240, -- visible video
hpad => 32, -- H black border
vpad => 0 -- V black border
)
port map (
I_VIDEO(15 downto 12) => "0000",
-- hpad => 32, -- H black border
-- vpad => 0 -- V black border
-- )
-- port map (
-- I_VIDEO(15 downto 12) => "0000",
-- only 3 bit color
I_VIDEO(11) => ULA_VIDEO_R,
I_VIDEO(10) => ULA_VIDEO_R,
I_VIDEO(9) => ULA_VIDEO_R,
I_VIDEO(8) => ULA_VIDEO_R,
-- -- only 3 bit color
-- I_VIDEO(11) => ULA_VIDEO_R,
-- I_VIDEO(10) => ULA_VIDEO_R,
-- I_VIDEO(9) => ULA_VIDEO_R,
-- I_VIDEO(8) => ULA_VIDEO_R,
I_VIDEO(7) => ULA_VIDEO_G,
I_VIDEO(6) => ULA_VIDEO_G,
I_VIDEO(5) => ULA_VIDEO_G,
I_VIDEO(4) => ULA_VIDEO_G,
-- I_VIDEO(7) => ULA_VIDEO_G,
-- I_VIDEO(6) => ULA_VIDEO_G,
-- I_VIDEO(5) => ULA_VIDEO_G,
-- I_VIDEO(4) => ULA_VIDEO_G,
I_VIDEO(3) => ULA_VIDEO_B,
I_VIDEO(2) => ULA_VIDEO_B,
I_VIDEO(1) => ULA_VIDEO_B,
I_VIDEO(0) => ULA_VIDEO_B,
I_HSYNC => hs_int,
I_VSYNC => vs_int,
-- I_VIDEO(3) => ULA_VIDEO_B,
-- I_VIDEO(2) => ULA_VIDEO_B,
-- I_VIDEO(1) => ULA_VIDEO_B,
-- I_VIDEO(0) => ULA_VIDEO_B,
-- I_HSYNC => hs_int,
-- I_VSYNC => vs_int,
-- for VGA output, feed these signals to VGA monitor
O_VIDEO(15 downto 12)=> dummy,
O_VIDEO(11 downto 8) => VideoR,
O_VIDEO( 7 downto 4) => VideoG,
O_VIDEO( 3 downto 0) => VideoB,
O_HSYNC => HSync,
O_VSYNC => VSync,
O_CMPBLK_N => s_cmpblk_n_out,
-- -- for VGA output, feed these signals to VGA monitor
-- O_VIDEO(15 downto 12)=> dummy,
-- O_VIDEO(11 downto 8) => VideoR,
-- O_VIDEO( 7 downto 4) => VideoG,
-- O_VIDEO( 3 downto 0) => VideoB,
-- O_HSYNC => HSync,
-- O_VSYNC => VSync,
-- O_CMPBLK_N => s_cmpblk_n_out,
--
CLK => clk6,
CLK_x2 => clk12
);
-- --
-- CLK => clk6,
-- CLK_x2 => clk12
-- );
--Q
-- Para scandoubler descomentar esto y comentar las directas de la ULA
@ -463,11 +486,21 @@ begin
--O_VIDEO_G(2) <= ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
--O_VIDEO_B(2) <= ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
-- vga output
O_HSYNC <= HSync;
O_VSYNC <= VSync;
O_VIDEO_R(2) <= VideoR(3); -- ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
O_VIDEO_G(2) <= VideoG(3); -- ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
O_VIDEO_B(2) <= VideoB(3);-- ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
O_NTSC <= '0';
O_PAL <= '1';
O_HSYNC <= ULA_SYNC;
O_VSYNC <= vs_int;
O_VIDEO_R <= ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R;
O_VIDEO_G <= ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G;
O_VIDEO_B <= ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B;
-- O_HSYNC <= HSync;
-- O_VSYNC <= VSync;
-- O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2) ;
-- O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2) ;
-- O_VIDEO_B <= VideoB(0) & VideoB(1) & VideoB(2) ;
-- O_VIDEO_R(2) <= VideoR(3); -- ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
-- O_VIDEO_G(2) <= VideoG(3); -- ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
-- O_VIDEO_B(2) <= VideoB(3);-- ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
----
--fQ
@ -576,70 +609,67 @@ begin
clk_i => clk24,
resetn => loc_reset_n,
dac_i => PSG_OUT,
dac_o => AUDIO_OUT2
dac_o => audio_out_tmp
);
AUDIO_OUT <= audio_out_tmp;
AUDIO_OUT2 <= audio_out_tmp;
-- this is my piezo output
onebit : entity work.XSP6X9_onebit
generic map (k => 21)
port map (
nreset => loc_reset_n,
clk => clk24,
input => PSG_OUT,
output => AUDIO_OUT,
voutput => vaudio_out
);
--process
--begin
-- wait until rising_edge(clk24);
-- AUDIO_OUT <= PSG_OUT(5);
--end process;
inst_clock_div :entity work.clkdiv
generic map (
DIVRATIO => 1000000
)
port map (
nreset => loc_reset_n,
clk =>clk6,
clkout => led_signal_update
);
inst_clock_div_multiplex :entity work.clkdiv
generic map (
DIVRATIO => 3750 -- 200Hz whole refresh
)
port map (
nreset => loc_reset_n,
clk =>clk6,
clkout => led_mutiplex_clk
);
-- onebit : entity work.XSP6X9_onebit
-- generic map (k => 21)
-- port map (
-- nreset => loc_reset_n,
-- clk => clk24,
-- input => PSG_OUT,
-- output => AUDIO_OUT,
-- voutput => vaudio_out
-- );
-- inst_clock_div :entity work.clkdiv
-- generic map (
-- DIVRATIO => 1000000
-- )
-- port map (
-- nreset => loc_reset_n,
-- clk =>clk6,
-- clkout => led_signal_update
-- );
-- inst_clock_div_multiplex :entity work.clkdiv
-- generic map (
-- DIVRATIO => 3750 -- 200Hz whole refresh
-- )
-- port map (
-- nreset => loc_reset_n,
-- clk =>clk6,
-- clkout => led_mutiplex_clk
-- );
update_led :process(led_signal_update)
begin
if (rising_edge(led_signal_update)) then
-- led_signals_save(15 downto 0) <= CPU_ADDR(15 downto 0);
-- --led_signals_save(11 downto 8) <= X"e";
-- --led_signals_save(15 downto 12) <= X"f";
-- --led_signals_save(19 downto 16) <= X"a";
led_signals_save(15 downto 0) <= CPU_ADDR(15 downto 0);
-- led_signals_save(13 downto 0) <= disk_track_addr;
-- led_signals_save(15 downto 14) <= (others => '0');
led_signals_save(23 downto 16) <= IMAGE_NUMBER_out(7 downto 0);
led_signals_save(27 downto 24) <= disk_cur_TRACK(3 downto 0);
led_signals_save(29 downto 28) <= disk_cur_TRACK(5 downto 4);
led_signals_save(31 downto 30) <= (others => '0');
end if;
end process;
-- update_led :process(led_signal_update)
-- begin
-- if (rising_edge(led_signal_update)) then
-- -- led_signals_save(15 downto 0) <= CPU_ADDR(15 downto 0);
-- -- --led_signals_save(11 downto 8) <= X"e";
-- -- --led_signals_save(15 downto 12) <= X"f";
-- -- --led_signals_save(19 downto 16) <= X"a";
-- led_signals_save(15 downto 0) <= CPU_ADDR(15 downto 0);
-- -- led_signals_save(13 downto 0) <= disk_track_addr;
-- -- led_signals_save(15 downto 14) <= (others => '0');
-- led_signals_save(23 downto 16) <= IMAGE_NUMBER_out(7 downto 0);
-- led_signals_save(27 downto 24) <= disk_cur_TRACK(3 downto 0);
-- led_signals_save(29 downto 28) <= disk_cur_TRACK(5 downto 4);
-- led_signals_save(31 downto 30) <= (others => '0');
-- end if;
-- end process;
led_display : entity work.XSP6X9_Led_Output
port map (
clk => clk6, --led_mutiplex_clk,
inputs (31 downto 0) => led_signals_save,
segment => segment,
position => position
);
-- led_display : entity work.XSP6X9_Led_Output
-- port map (
-- clk => clk6, --led_mutiplex_clk,
-- inputs (31 downto 0) => led_signals_save,
-- segment => segment,
-- position => position
-- );
out_MAPn <= cont_MAPn;
-- out_MAPn <= cont_MAPn;
controller8dos : entity work.controller_8dos
port map
(
@ -723,7 +753,7 @@ begin
------------------------------------------------------------
-- K7 PORT
------------------------------------------------------------
K7_TAPEOUT <= via_out(7);
-- K7_TAPEOUT <= via_out(7);
-- K7_REMOTE <= via_out(6);
-- K7_AUDIOOUT <= AUDIO_OUT;

80
cores/Oric/source/scan_converter.vhd
View File

@ -28,7 +28,7 @@
-- VSYNC |__| VSYNC |__| VSYNC
-- Scan converter input and output timings compared to standard VGA
-- esolution - Frame | Pixel | Front | HSYNC | Back | Active | HSYNC | Front | VSYNC | Back | Active | VSYNC
-- Resolution - Frame | Pixel | Front | HSYNC | Back | Active | HSYNC | Front | VSYNC | Back | Active | VSYNC
-- - Rate | Clock | Porch hA | Pulse hB | Porch hC | Video hD | Polarity | Porch vA | Pulse vB | Porch vC | Video vD | Polarity
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-- In 256x224 - 59.18Hz | 6.000 MHz | 38 pixels | 32 pixels | 58 pixels | 256 pixels | negative | 16 lines | 8 lines | 16 lines | 224 lines | negative
@ -58,7 +58,7 @@ entity VGA_SCANCONV is
hC : integer range 0 to 1023 := 48; -- h back porch
hD : integer range 0 to 1023 := 640; -- visible video
vA : integer range 0 to 1023 := 16; -- v front porch
-- vA : integer range 0 to 1023 := 16; -- v front porch
vB : integer range 0 to 1023 := 2; -- v sync
vC : integer range 0 to 1023 := 33; -- v back porch
vD : integer range 0 to 1023 := 480; -- visible video
@ -82,11 +82,7 @@ entity VGA_SCANCONV is
end;
architecture RTL of VGA_SCANCONV is
type ram_t is array (0 to 1023) of std_logic_vector(15 downto 0);
signal ram : ram_t := (others => (others => '0'));
attribute ram_style: string;
attribute ram_style of ram : signal is "distributed";
--
--
-- input timing
--
signal ivsync_last_x2 : std_logic := '1';
@ -105,46 +101,32 @@ attribute ram_style of ram : signal is "distributed";
signal CLK_x2_n : std_logic := '1';
begin
-- dual port line buffer, max line of 1024 pixels
ram_write :process(CLK_x2)
begin
if rising_edge(CLK_x2) then
ram(to_integer(unsigned((hpos_i)))) <= I_VIDEO;
end if;
end process;
ram_read :process(CLK_x2)
begin
if falling_edge(CLK_x2) then
O_VIDEO <= ram(to_integer(unsigned(hpos_o)));
end if;
end process;
-- dual port line buffer, max line of 1024 pixels
u_ram : RAMB16_S18_S18
generic map (INIT_A => X"00000", INIT_B => X"00000", SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
port map (
-- input
DOA => open,
DIA => I_VIDEO,
DOPA => open,
DIPA => "00",
ADDRA => hpos_i,
WEA => '1',
ENA => CLK,
SSRA => '0',
CLKA => CLK_x2,
-- u_ram : RAMB16_S18_S18
-- generic map (INIT_A => X"00000", INIT_B => X"00000", SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
-- port map (
-- -- input
-- DOA => open,
-- DIA => I_VIDEO,
-- DOPA => open,
-- DIPA => "00",
-- ADDRA => hpos_i,
-- WEA => '1',
-- ENA => CLK,
-- SSRA => '0',
-- CLKA => CLK_x2,
-- -- output
-- DOB => O_VIDEO,
-- DIB => x"0000",
-- DOPB => open,
-- DIPB => "00",
-- ADDRB => hpos_o,
-- WEB => '0',
-- ENB => '1',
-- SSRB => '0',
-- CLKB => CLK_x2_n
-- );
-- output
DOB => O_VIDEO,
DIB => x"0000",
DOPB => open,
DIPB => "00",
ADDRB => hpos_o,
WEB => '0',
ENB => '1',
SSRB => '0',
CLKB => CLK_x2_n
);
CLK_x2_n <= not CLK_x2;
@ -216,7 +198,7 @@ begin
begin
wait until rising_edge(CLK_x2);
-- V sync timing
if (vcnt < vB+vA) and (vcnt >= vA) then
if (vcnt < vB) then
O_VSYNC <= '0';
else
O_VSYNC <= '1';
@ -228,7 +210,7 @@ begin
begin
wait until rising_edge(CLK_x2);
-- visible video area doubled from the original game
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vA + vB + vC+vpad)) and (vcnt <= 2*(vA + vB + vC + vD + vpad))) then
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vB + vC + vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then
hpos_o <= hpos_o + 1;
else
hpos_o <= (others => '0');
@ -240,7 +222,7 @@ begin
begin
wait until rising_edge(CLK_X2);
-- active video area 640x480 (VGA) after padding with blank borders
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vA + vB + vC)) and (vcnt <= 2*(vA + vB + vC + vD + 2*vpad))) then
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then
O_CMPBLK_N <= '1';
else
O_CMPBLK_N <= '0';

25
cores/Oric/source/spi_controller.vhd
View File

@ -104,18 +104,19 @@ begin
-- If slow_clk is true, spi_clk = CLK_14M / 32 and SCLK = 223.214kHz, which
-- is between 100kHz and 400kHz, as required for MMC compatibility.
--
var_clkgen : process (CLK_14M, slow_clk)
variable var_clk : unsigned(4 downto 0) := (others => '0');
begin
if slow_clk then
spi_clk <= var_clk(4);
if rising_edge(CLK_14M) then
var_clk := var_clk + 1;
end if;
else
spi_clk <= CLK_14M;
end if;
end process;
spi_clk <= CLK_14M;
-- var_clkgen : process (CLK_14M, slow_clk)
-- variable var_clk : unsigned(4 downto 0) := (others => '0');
-- begin
-- if slow_clk then
-- spi_clk <= var_clk(4);
-- if rising_edge(CLK_14M) then
-- var_clk := var_clk + 1;
-- end if;
-- else
-- spi_clk <= CLK_14M;
-- end if;
-- end process;
SCLK <= sclk_sig;
--

16
cores/Oric/source/ula.vhd
View File

@ -190,6 +190,7 @@ architecture RTL of ula is
signal lDATABUS : std_logic_vector( 7 downto 0);
signal lSHFREG : std_logic_vector( 5 downto 0);
signal lREGHOLD : std_logic_vector( 6 downto 0);
signal lATTR_REGHOLD : std_logic_vector( 6 downto 0);
signal lRGB : std_logic_vector( 2 downto 0);
signal lREG_INK : std_logic_vector( 2 downto 0);
signal lREG_STYLE : std_logic_vector( 2 downto 0);
@ -228,7 +229,7 @@ begin
-- phase 1 phase 2 phase 3
SRAM_OE <= ph(0) or ph(1) or RW_INT ;
SRAM_CE <= ph(0) or ph(1) or (ph(2) and (not CSRAMn_INT) );
SRAM_CE <= (ph(0) and not c(0) ) or (ph(1) and not c(8) ) or (not c(16) and ph(2) and (not CSRAMn_INT) );
SRAM_WE <= (not CSRAMn_INT) and (not RW_INT) and c(17) ;
@ -328,8 +329,8 @@ begin
elsif rising_edge(CLK_1_INT) then
if (lCTR_H = 63) then
-- 50Hz = 312 lines, 60Hz = 260 lines
if ((lCTR_V < 312) and lFREQ_SEL='1') or
((lCTR_V < 260) and lFREQ_SEL='0') then
if ((lCTR_V < 311) and lFREQ_SEL='1') or
((lCTR_V < 259) and lFREQ_SEL='0') then
lCTR_V <= lCTR_V + 1;
else
lCTR_V <= (others => '0');
@ -349,7 +350,7 @@ begin
lHBLANKn <= '1' when (lCTR_H >= 1) and (lCTR_H <= 40) else '0';
-- Signal to Reload Register to reset attributes
lRELOAD_SEL <= '1' when (lCTR_H >= 62) else '0';
lRELOAD_SEL <= '1' when (lCTR_H >= 49) else '0';
-- Vertical Synchronisation
lVSYNC50n <= '0' when (lCTR_V >= 258) and (lCTR_V <= 259) else '1'; -- 50Hz
@ -391,8 +392,9 @@ begin
lInv_hold <= '0';
elsif rising_edge(CLK_24) then
if ATTRIB_DEC = '1' then
IsATTRIB <= not (DB_INT(6) or DB_INT(5)); -- 1 = attribute, 0 = not an attribute
lInv_hold <= DB_INT(7);
IsATTRIB <= not (DB_INT(6) or DB_INT(5)); -- 1 = attribute, 0 = not an attribute
lATTR_REGHOLD <= DB_INT(6 downto 0);
lInv_hold <= DB_INT(7);
end if;
end if;
end process;
@ -430,7 +432,7 @@ begin
lREG_PAPER <= (others=>'0');
elsif rising_edge(CLK_24) then
if (RELD_REG = '1' and isAttrib = '1') then
case lREGHOLD(6 downto 3) is
case lATTR_REGHOLD(6 downto 3) is
when "0000" => lREG_INK <= lREGHOLD(2 downto 0);
when "0001" => lREG_STYLE <= lREGHOLD(2 downto 0);
when "0010" => lREG_PAPER <= lREGHOLD(2 downto 0);