falso
/
zxuno-git
mirror of https://github.com/zxdos/zxuno.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

genero core

This commit is contained in:
antoniovillena 2022-04-30 00:05:19 +02:00
parent cd61ab37a3
commit 3f2d48d821
9 changed files with 53 additions and 1217 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
cores/Spectrum/binaries/core02_zxunovga.zx1 Normal file
View File

Binary file not shown.

BIN
cores/Spectrum/binaries/zxunovga.bit Normal file
View File

Binary file not shown.

6
cores/Spectrum/common/config.vh
View File

@ -27,8 +27,8 @@
// The following two defines are taken into account only if LOAD_ROM_FROM_FLASH_OPTION is not defined
`define DEFAULT_SYSTEM_ROM "128en.hex"
`define DEFAULT_DIVMMC_ROM "esxdos088.hex"
`define MIDI_SYNTH_OPTION
`define UART_ESP8266_OPTION
//`define MIDI_SYNTH_OPTION
//`define UART_ESP8266_OPTION
`define F11_ESP8266_FEATURE
`define PZX_PLAYER_OPTION
`define VGA_OUTPUT_OPTION
@ -52,7 +52,7 @@
//`define AD724_CONTROL_SUPPORT
//`define FPGA_GENERATES_COLOR_CLOCK_OPTION
`define MONOCHROMERGB
//`define SAA1099
`define SAA1099
`define INITIAL_KB_RESET
// ZXUNO core ID string. Must be padded with zero bytes to the right (16 bytes total)
localparam COREID_STRING = {"EXP27-030422", 8'h00, 8'h00, 8'h00, 8'h00};

16
cores/Spectrum/zxunovga/pines_zxuncore.ucf
View File

@ -79,16 +79,16 @@ NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; #para que no quede flotante en el uZX1
# MIDI
NET "midi_out" LOC="P43" | IOSTANDARD = LVCMOS33 | DRIVE=12; # MIDI_OUT del addon MIDI
NET "clkbd" LOC="P50" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "wsbd" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dabd" LOC="P46" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "midi_out" LOC="P43" | IOSTANDARD = LVCMOS33 | DRIVE=12; # MIDI_OUT del addon MIDI
#NET "clkbd" LOC="P50" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "wsbd" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "dabd" LOC="P46" | IOSTANDARD = LVCMOS33 | PULLUP;
# UART
NET "uart_tx" LOC="P16" | IOSTANDARD = LVCMOS33;
NET "uart_rx" LOC="P12" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "uart_rts" LOC="P22" | IOSTANDARD = LVCMOS33;
NET "uart_reset" LOC="P21" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "uart_tx" LOC="P16" | IOSTANDARD = LVCMOS33;
#NET "uart_rx" LOC="P12" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "uart_rts" LOC="P22" | IOSTANDARD = LVCMOS33;
#NET "uart_reset" LOC="P21" | IOSTANDARD = LVCMOS33 | PULLUP;
# Keyboard and mouse
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN

126
cores/Spectrum/zxunovga/pines_zxuno_v4vga.ucf
View File

@ -1,126 +0,0 @@
#NET "sysclk" PERIOD=28 ns; # 28.125 MHz actual frequency for 50Hz vertical refresh
#NET "clk14" PERIOD=56 ns;
#NET "clk7" PERIOD=112 ns;
#NET "clk3d5" PERIOD=224 ns;
############################################################################
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
#PIN "relojes_maestros/speed_3_and_2.O" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "relojes_maestros/speed_1_and_0.O" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "relojes_maestros/cpuclk_selector.O" CLOCK_DEDICATED_ROUTE = FALSE;
# Video output
NET "hsync" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # hs
NET "vsync" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # vs
NET "r<5>" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<5>
NET "r<4>" LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<4>
NET "r<3>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<3>
NET "r<2>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<2>
NET "r<1>" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<1>
NET "r<0>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # r<0>
NET "g<5>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<5>
NET "g<4>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<4>
NET "g<3>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<3>
NET "g<2>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<2>
NET "g<1>" LOC="P29" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<1>
NET "g<0>" LOC="P27" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # g<0>
NET "b<5>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<5>
NET "b<4>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<4>
NET "b<3>" LOC="P24" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<3>
NET "b<2>" LOC="P21" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<2>
NET "b<1>" LOC="P14" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<1>
NET "b<0>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW=FAST; # b<0>
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
# SRAM
NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
NET "joybtn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
NET "dr<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "dr<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "dr<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "dg<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "dg<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "dg<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "db<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "db<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "db<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "dhsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "dvsync" LOC="P85" | IOSTANDARD = LVCMOS33;
# UART
NET "uart_tx" LOC="P16" | IOSTANDARD = LVCMOS33;
NET "uart_rx" LOC="P12" | IOSTANDARD = LVCMOS33;
NET "uart_rts" LOC="P22" | IOSTANDARD = LVCMOS33;
NET "uart_reset" LOC="P26" | IOSTANDARD = LVCMOS33 | PULLUP;

12
cores/Spectrum/zxunovga/tld_zxuncore.v
View File

@ -44,16 +44,6 @@ module tld_zxuncore (
output wire audio_out_left,
output wire audio_out_right,
output wire midi_out,
input wire clkbd,
input wire wsbd,
input wire dabd,
output wire uart_tx,
input wire uart_rx,
output wire uart_rts,
output wire uart_reset,
output wire stdn,
output wire stdnb,
@ -89,6 +79,8 @@ module tld_zxuncore (
wire disable_genclk;
wire [2:0] pll_frequency_option;
wire midi_out, clkbd, wsbd, dabd, uart_tx, uart_rx, uart_rts, uart_reset;
assign dr = r[5:3];
assign dg = g[5:3];
assign db = b[5:3];

194
cores/Spectrum/zxunovga/tld_zxuno_vga.v
View File

@ -1,194 +0,0 @@
`timescale 1ns / 1ns
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:28:18 02/06/2014
// Design Name:
// Module Name: test1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_zxuno (
input wire clk50mhz,
inout wire [2:0] r,
inout wire [2:0] g,
inout wire [2:0] b,
inout wire hsync,
inout wire vsync,
output wire [2:0] dr,
output wire [2:0] dg,
output wire [2:0] db,
output wire dhsync,
output wire dvsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
output wire audio_out_right,
output wire stdn,
output wire stdnb,
output wire flash_ext1,
output wire flash_ext2,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
output wire flash_cs_n,
output wire flash_clk,
output wire flash_mosi,
input wire flash_miso,
output wire sd_cs_n,
output wire sd_clk,
output wire sd_mosi,
input wire sd_miso,
output wire testled, // nos servirá como testigo de uso de la SPI
input wire joyup,
input wire joydown,
input wire joyleft,
input wire joyright,
input wire joyfire,
input wire joybtn2,
input wire uart_rx,
output wire uart_tx,
output wire uart_rts,
input wire uart_reset,
input wire uart_ch_pd,
input wire uart_gpio0,
input wire uart_gpio2
);
wire sysclk,clk14,clk7,clk3d5,cpuclk;
wire CPUContention;
wire clkcpu_enable;
wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option;
assign dr = r[5:3];
assign dg = g;
assign db = b;
assign dhsync = hsync;
assign dvsync = vsync;
clock_generator relojes_maestros
(// Clock in ports
.CLK_IN1 (clk50mhz),
.CPUContention (CPUContention),
.pll_option (pll_frequency_option),
.turbo_enable (turbo_enable),
// Clock out ports
.CLK_OUT1 (sysclk),
.CLK_OUT2 (clk14),
.CLK_OUT3 (clk7),
.CLK_OUT4 (clk3d5),
.cpuclk (cpuclk),
.clkcpu_enable (clkcpu_enable)
);
wire [2:0] ri, gi, bi;
wire hsync_pal, vsync_pal, csync_pal;
wire vga_enable, scanlines_enable;
zxuno la_maquina (
.clk28(sysclk),
.clk14(clk14),
.clk7(clk7),
.clk3d5(clk3d5),
.cpuclk(cpuclk),
.CPUContention(CPUContention),
.clkcpu_enable(clkcpu_enable),
.power_on_reset_n(1'b1), // sólo para simulación. Para implementacion, dejar a 1
.r(ri),
.g(gi),
.b(bi),
.hsync(hsync_pal),
.vsync(vsync_pal),
.csync(csync_pal),
.clkps2(clkps2),
.dataps2(dataps2),
.ear_ext(~ear), // negada porque el hardware tiene un transistor inversor
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n),
.flash_cs_n(flash_cs_n),
.flash_clk(flash_clk),
.flash_di(flash_mosi),
.flash_do(flash_miso),
.sd_cs_n(sd_cs_n),
.sd_clk(sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso),
.joyup(joyup),
.joydown(joydown),
.joyleft(joyleft),
.joyright(joyright),
.joyfire(joyfire),
.joybtn2(joybtn2),
.mouseclk(mouseclk),
.mousedata(mousedata),
.vga_enable(vga_enable),
.scanlines_enable(scanlines_enable),
.freq_option(pll_frequency_option),
.turbo_enable(turbo_enable),
.ad724_xtal(stdnb),
.ad724_mode(stdn),
.uart_tx(uart_tx),
.uart_rx(uart_rx),
.uart_rts(uart_rts),
.uart_reset(uart_reset),
.uart_ch_pd(uart_ch_pd),
.uart_gpio0(uart_gpio0),
.uart_gpio2(uart_gpio2)
);
vga_scandoubler #(.CLKVIDEO(14000)) salida_vga (
.clkvideo(clk14),
.clkvga(sysclk),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.csync_ext_n(csync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
assign testled = (!flash_cs_n || !sd_cs_n);
assign flash_ext1 = 1'b1;
assign flash_ext2 = 1'b1;
endmodule

80
cores/Spectrum/zxunovga/zxuncore.xise
View File

@ -17,7 +17,7 @@
<files>
<file xil_pn:name="../common/audio_management.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../common/T80.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -40,55 +40,55 @@
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="tld_zxuncore.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../common/tv80_to_t80_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../common/lut.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../common/zxunoregs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../common/flash_spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../common/rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../common/ula_radas.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../common/turbosound.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../common/ps2_keyb.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../common/ps2_port.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../common/scancode_to_speccy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../common/joystick_protocols.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../common/coreid.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../common/scratch_register.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -100,18 +100,18 @@
</file>
<file xil_pn:name="../common/ps2_mouse_kempston.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../common/ps2mouse_to_kmouse.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="pines_zxuncore.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../common/scandoubler_ctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="pll_drp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -119,35 +119,35 @@
</file>
<file xil_pn:name="pll_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../common/pal_sync_generator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../common/control_rasterint.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../common/new_memory.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../common/control_enable_options.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../common/specdrum.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../common/dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../common/cpu_and_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../common/ctrl_ad724.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
@ -155,15 +155,15 @@
</file>
<file xil_pn:name="../common/disk_drive.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../common/total_memory_register.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="relojes.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../common/debug.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
@ -171,27 +171,27 @@
</file>
<file xil_pn:name="../common/i2s_decoder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../common/uart.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../common/zxunouart.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../common/clk_enables.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="multiboot_spartan6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../common/ay_3_8192.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../common/gencolorclk.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
@ -199,27 +199,27 @@
</file>
<file xil_pn:name="../common/spi_protocol.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../common/monochrome_rgb_18bits.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../common/zxuno.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../common/vga_scandoubler_18bits.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../common/saa1099s.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../common/pzx_player.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
</files>

836
cores/Spectrum/zxunovga/zxuno_vga.v
View File

@ -1,836 +0,0 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:16:16 02/06/2014
// Design Name:
// Module Name: zxuno
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module zxuno (
// Relojes
input wire clk28,
input wire clk14,
input wire clk7,
input wire clk3d5,
input wire cpuclk, // reloj seleccionado par ala CPU, después de aplicar contención
output wire CPUContention, // Señal de contención del reloj de la CPU
input wire clkcpu_enable,
input wire power_on_reset_n,
// E/S
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
output wire csync,
inout wire clkps2,
inout wire dataps2,
input wire ear_ext,
output wire audio_out_left,
output wire audio_out_right,
// SRAM
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
// Flash SPI
output wire flash_cs_n,
output wire flash_clk,
output wire flash_di,
input wire flash_do,
// SD/MMC
output wire sd_cs_n,
output wire sd_clk,
output wire sd_mosi,
input wire sd_miso,
// DB9 JOYSTICK
input wire joyup,
input wire joydown,
input wire joyleft,
input wire joyright,
input wire joyfire,
input wire joybtn2,
// MOUSE
inout wire mouseclk,
inout wire mousedata,
// SCANDOUBLER CTRL
output wire vga_enable,
output wire scanlines_enable,
output wire [2:0] freq_option,
output wire [1:0] turbo_enable,
// AD724
output wire ad724_xtal,
output wire ad724_mode,
// UART
input wire uart_rx,
output wire uart_tx,
output wire uart_rts,
input wire uart_reset,
input wire uart_ch_pd,
input wire uart_gpio0,
input wire uart_gpio2
);
// Señales de la CPU
wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n;
wire enable_nmi_n;
wire [15:0] cpuaddr;
reg [7:0] cpudin;
wire [7:0] cpudout;
wire [7:0] ula_dout;
// Señales acceso RAM por parte de la ULA
wire [13:0] vram_addr;
wire [7:0] vram_dout;
// Señales acceso RAM por parte de la CPU
wire [7:0] memory_dout;
wire oe_n_romyram;
// Señales de acceso del AY por parte de la CPU
wire [7:0] ay_dout;
wire bc1,bdir;
wire oe_n_ay;
// Señales de acceso a registro de direcciones ZX-Uno
wire [7:0] zxuno_addr_to_cpu; // al bus de datos de entrada del Z80
wire [7:0] zxuno_addr; // direccion de registro actual
wire regaddr_changed; // indica que se ha escrito un nuevo valor en el registro de direcciones
wire oe_n_zxunoaddr; // el dato en el bus de entrada del Z80 es válido
wire zxuno_regrd; // Acceso de lectura en el puerto de datos de ZX-Uno
wire zxuno_regwr; // Acceso de escritura en el puerto de datos del ZX-Uno
wire in_boot_mode; // Vae 1 cuando el sistema está en modo boot (ejecutando la BIOS)
// Señales de acceso al módulo Flash SPI
wire [7:0] spi_dout;
wire oe_n_spi;
wire wait_spi_n;
// Fuentes de sonido y control del mixer
wire mic;
wire spk;
wire [7:0] ay1_audio;
wire [7:0] ay2_audio;
wire [7:0] ay1_cha, ay1_chb, ay1_chc;
wire [7:0] ay2_cha, ay2_chb, ay2_chc;
wire [7:0] specdrum_left, specdrum_right;
wire [7:0] mixer_dout;
wire oe_n_mixer;
// Interfaz de acceso al teclado
wire [4:0] kbdcol;
wire [7:0] kbdrow = cpuaddr[15:8]; // las filas del teclado son A8-A15 de la CPU;
wire mrst_n,rst_n; // los dos resets suministrados por el teclado
wire [7:0] scancode_dout; // scancode original desde el teclado PC
wire oe_n_scancode;
wire [7:0] keymap_dout;
wire oe_n_keymap;
wire [7:0] kbstatus_dout;
wire oe_n_kbstatus;
wire [8:0] user_fnt;
wire video_output_change; // señal que da la tecla Scroll Lock para cambiar de modo de video
// Interfaz joystick configurable
wire oe_n_joystick;
wire [4:0] kbd_joy;
wire [7:0] joystick_dout;
wire [4:0] kbdcol_to_ula;
// Configuración ULA
wire [1:0] timing_mode;
wire issue2_keyboard;
wire disable_contention;
wire access_to_screen;
wire doc_ext_option; // bit 7 del puerto $FF del Timex
wire ioreqbank;
// CoreID
wire oe_n_coreid;
wire [7:0] coreid_dout;
// Scratch register
wire oe_n_scratch;
wire [7:0] scratch_dout;
// AD724 control
wire oe_n_ad724;
wire [7:0] ad724_dout;
// Memory report register
wire oe_n_memrep;
wire [7:0] memrep_dout;
// Multiboot
wire oe_n_multiboot;
wire [7:0] multiboot_dout;
// Scandoubler control
wire csync_option;
wire [7:0] scndblctrl_dout;
wire oe_n_scndblctrl;
// Raster INT control
wire rasterint_enable;
wire vretraceint_disable;
wire [8:0] raster_line;
wire raster_int_in_progress;
wire [7:0] rasterint_dout;
wire oe_n_rasterint;
// Device enable options
wire disable_ay;
wire disable_turboay;
wire disable_7ffd;
wire disable_1ffd;
wire disable_romsel7f;
wire disable_romsel1f;
wire enable_timexmmu;
wire disable_spisd;
wire disable_timexscr;
wire disable_ulaplus;
wire disable_radas;
wire disable_specdrum;
wire disable_mixer;
wire [7:0] devoptions_dout;
wire oe_n_devoptions;
// NMI events
wire [7:0] nmievents_dout;
wire oe_n_nmievents;
wire nmispecial_n;
wire page_configrom_active;
// Kempston mouse
wire [7:0] kmouse_dout;
wire [7:0] mousedata_dout;
wire [7:0] mousestatus_dout;
wire oe_n_kmouse, oe_n_mousedata, oe_n_mousestatus;
// UART
wire oe_n_uart;
wire [7:0] uart_dout;
// DMA device interface
wire [7:0] dma_dout;
wire oe_n_dma;
// Disk drive
wire [7:0] diskdrive_dout;
wire oe_n_diskdrive;
// Lector PZX
wire [20:0] pzx_addr;
wire [7:0] pzx_dout;
wire oe_n_pzx;
wire enable_pzx;
wire pzx_playing;
wire pzx_output;
wire in48kmode;
wire play = user_fnt[0];
wire stop = user_fnt[1];
wire jump = user_fnt[2];
wire [7:0] data_from_pzx;
wire [7:0] data_to_pzx;
wire write_data_pzx;
wire ear = (pzx_playing == 1'b1)? pzx_output : ear_ext;
// Asignación de dato para la CPU segun la decodificación de todos los dispositivos
// conectados a ella.
always @* begin
case (1'b0)
oe_n_ay : cpudin = ay_dout;
oe_n_joystick : cpudin = joystick_dout;
oe_n_zxunoaddr : cpudin = zxuno_addr_to_cpu;
oe_n_spi : cpudin = spi_dout;
oe_n_scancode : cpudin = scancode_dout;
oe_n_kbstatus : cpudin = kbstatus_dout;
oe_n_coreid : cpudin = coreid_dout;
oe_n_keymap : cpudin = keymap_dout;
oe_n_scratch : cpudin = scratch_dout;
oe_n_scndblctrl : cpudin = scndblctrl_dout;
oe_n_nmievents : cpudin = nmievents_dout;
oe_n_kmouse : cpudin = kmouse_dout;
oe_n_mousedata : cpudin = mousedata_dout;
oe_n_mousestatus : cpudin = mousestatus_dout;
oe_n_rasterint : cpudin = rasterint_dout;
oe_n_devoptions : cpudin = devoptions_dout;
oe_n_romyram : cpudin = memory_dout;
oe_n_multiboot : cpudin = multiboot_dout;
oe_n_mixer : cpudin = mixer_dout;
oe_n_dma : cpudin = dma_dout;
oe_n_ad724 : cpudin = ad724_dout;
oe_n_diskdrive : cpudin = diskdrive_dout;
oe_n_pzx : cpudin = pzx_dout;
oe_n_memrep : cpudin = memrep_dout;
oe_n_uart : cpudin = uart_dout;
default : cpudin = ula_dout;
endcase
end
// tv80n_wrapper el_z80 (
// .m1_n(m1_n),
// .mreq_n(mreq_n),
// .iorq_n(iorq_n),
// .rd_n(rd_n),
// .wr_n(wr_n),
// .rfsh_n(rfsh_n),
// .halt_n(),
// .busak_n(),
// .A(cpuaddr),
// .dout(cpudout),
//
// .reset_n(rst_n & mrst_n & power_on_reset_n), // cualquiera de los dos resets
// .clk(cpuclk),
// .wait_n(wait_n),
// .int_n(int_n),
// .nmi_n((nmi_n | enable_nmi_n) & nmispecial_n),
// .busrq_n(1'b1),
// .di(cpudin)
// );
cpu_and_dma el_z80_con_su_dma (
.m1_n(m1_n),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.halt_n(),
.A(cpuaddr),
.dout(cpudout),
.reset_n(rst_n & mrst_n & power_on_reset_n), // cualquiera de los tres resets
.clkcpu(cpuclk),
.clk_enable(clkcpu_enable),
.clkdma(clk28),
.wait_n(wait_spi_n),
.int_n(int_n),
.nmi_n((nmi_n | enable_nmi_n) & nmispecial_n),
.di(cpudin),
.zxuno_addr(zxuno_addr),
.regaddr_changed(regaddr_changed),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.dmadevicedin(cpudout),
.dmadevicedout(dma_dout),
.oe_n(oe_n_dma)
);
ula_radas la_ula (
// Clocks
.clk28(clk28),
.clkregs(clk28),
.clk14(clk14), // 14MHz master clock
.clk7(clk7),
.cpuclk(cpuclk),
.CPUContention(CPUContention),
.rst_n(mrst_n & rst_n & power_on_reset_n),
// CPU interface
.a(cpuaddr),
.access_to_contmem(access_to_screen),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.int_n(int_n),
.din(cpudout),
.dout(ula_dout),
.rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable),
.raster_line(raster_line),
.raster_int_in_progress(raster_int_in_progress),
// VRAM interface
.va(vram_addr), // 16KB videoram, 2 pages
.vramdata(vram_dout),
// ZX-UNO register interface
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.regaddr_changed(regaddr_changed),
// I/O ports
.ear(ear),
.mic(mic),
.spk(spk),
.kbd(kbdcol_to_ula),
.issue2_keyboard(issue2_keyboard),
.mode(timing_mode),
.ioreqbank(ioreqbank),
.disable_contention(disable_contention),
.doc_ext_option(doc_ext_option),
.enable_timexmmu(enable_timexmmu),
.disable_timexscr(disable_timexscr),
.disable_ulaplus(disable_ulaplus),
.disable_radas(disable_radas),
.csync_option(csync_option),
// Video
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.vsync(vsync),
.csync(csync)
);
zxunoregs addr_reg_zxuno (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(cpudout),
.dout(zxuno_addr_to_cpu),
.oe_n(oe_n_zxunoaddr),
.addr(zxuno_addr),
.read_from_reg(zxuno_regrd),
.write_to_reg(zxuno_regwr),
.regaddr_changed(regaddr_changed)
);
flash_and_sd cacharros_con_spi (
.clk(clk28),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.addr(zxuno_addr),
.ior(zxuno_regrd),
.iow(zxuno_regwr),
.din(cpudout),
.dout(spi_dout),
.oe_n(oe_n_spi),
.wait_n(wait_spi_n),
.in_boot_mode(in_boot_mode),
.flash_cs_n(flash_cs_n),
.flash_clk(flash_clk),
.flash_di(flash_di),
.flash_do(flash_do),
.disable_spisd(disable_spisd),
.sd_cs_n(sd_cs_n),
.sd_clk(sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso)
);
new_memory bootrom_rom_y_ram (
// Relojes y reset
.clk(clk28), // Reloj para registros de configuración
.mclk(clk28), // Reloj para el modulo de memoria de doble puerto
.mrst_n(mrst_n & power_on_reset_n),
.rst_n(rst_n & power_on_reset_n),
// Interface con la CPU
.a(cpuaddr),
.din(cpudout), // proveniente del bus de datos de salida de la CPU
.dout(memory_dout), // hacia el bus de datos de entrada de la CPU
.oe_n(oe_n_romyram), // el dato es valido
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.m1_n(m1_n), // Necesarios para implementar DIVMMC
.rfsh_n(rfsh_n),
.enable_nmi_n(enable_nmi_n),
.page_configrom_active(page_configrom_active), // Para habilitar la ROM de ayuda y configuración
// Interface con la ULA
.vramaddr(vram_addr),
.vramdout(vram_dout),
.doc_ext_option(doc_ext_option),
.issue2_keyboard_enabled(issue2_keyboard),
.timing_mode(timing_mode),
.disable_contention(disable_contention),
.access_to_screen(access_to_screen),
.ioreqbank(ioreqbank),
// Interface con el bus externo (TO-DO)
.inhibit_rom(1'b0),
.din_external(8'h00),
// Interface para registros ZXUNO
.addr(zxuno_addr),
.ior(zxuno_regrd),
.iow(zxuno_regwr),
.in_boot_mode(in_boot_mode),
// Interface con modulo de habilitacion de opciones
.disable_7ffd(disable_7ffd),
.disable_1ffd(disable_1ffd),
.disable_romsel7f(disable_romsel7f),
.disable_romsel1f(disable_romsel1f),
.enable_timexmmu(enable_timexmmu),
// Interface con el lector PZX
.pzx_addr(pzx_addr),
.enable_pzx(enable_pzx),
.in48kmode(in48kmode),
.data_from_pzx(data_from_pzx),
.data_to_pzx(data_to_pzx),
.write_data_pzx(write_data_pzx),
// Interface con la SRAM
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
);
ps2_keyb el_teclado (
.clk(clk28),
.clkps2(clkps2),
.dataps2(dataps2),
.rows(kbdrow),
.cols(kbdcol),
.joy(kbd_joy), // Implementación joystick en teclado numerico
.rst_out_n(rst_n), // esto son salidas, no entradas
.nmi_out_n(nmi_n), // Señales de reset y NMI
.mrst_out_n(mrst_n), // generadas por pulsaciones especiales del teclado
.user_fnt(user_fnt), // funciones de usuario
.video_output_change(video_output_change),
//----------------------------
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.regaddr_changed(regaddr_changed),
.din(cpudout),
.keymap_dout(keymap_dout),
.oe_n_keymap(oe_n_keymap),
.scancode_dout(scancode_dout),
.oe_n_scancode(oe_n_scancode),
.kbstatus_dout(kbstatus_dout),
.oe_n_kbstatus(oe_n_kbstatus)
);
joystick_protocols los_joysticks (
.clk(clk28),
//-- cpu interface
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.din(cpudout),
.dout(joystick_dout),
.oe_n(oe_n_joystick),
//-- interface with ZXUNO reg bank
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
//-- actual joystick and keyboard signals
.kbdjoy_in(kbd_joy),
.db9joy_in({joybtn2, joyfire, joyup, joydown, joyleft, joyright}),
.kbdcol_in(kbdcol),
.kbdcol_out(kbdcol_to_ula),
.vertical_retrace_int_n(int_n) // this is used as base clock for autofire
);
coreid identificacion_del_core (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.regaddr_changed(regaddr_changed),
.dout(coreid_dout),
.oe_n(oe_n_coreid)
);
// DESHABILITADO!!!!!!!!!!!!!!!!!!!!!!!!!!!!
scratch_register scratch (
.clk(1'b0 /*cpuclkplain*/),
.poweron_rst_n(power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(scratch_dout),
.oe_n(oe_n_scratch)
);
control_ad724 ad724 (
.clk(clk28),
.poweron_rst_n(power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(ad724_dout),
.oe_n(oe_n_ad724),
.ad724_xtal(ad724_xtal),
.ad724_mode(ad724_mode)
);
control_enable_options device_enables (
.clk(clk28),
.rst_n(mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(devoptions_dout),
.oe_n(oe_n_devoptions),
.disable_ay(disable_ay),
.disable_turboay(disable_turboay),
.disable_7ffd(disable_7ffd),
.disable_1ffd(disable_1ffd),
.disable_romsel7f(disable_romsel7f),
.disable_romsel1f(disable_romsel1f),
.enable_timexmmu(enable_timexmmu),
.disable_spisd(disable_spisd),
.disable_timexscr(disable_timexscr),
.disable_ulaplus(disable_ulaplus),
.disable_radas(disable_radas),
.disable_specdrum(disable_specdrum),
.disable_mixer(disable_mixer)
);
scandoubler_ctrl control_scandoubler (
.clk(clk28),
.a(cpuaddr),
.kbd_change_video_output(video_output_change),
.iorq_n(iorq_n),
.wr_n(wr_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(scndblctrl_dout),
.oe_n(oe_n_scndblctrl),
.vga_enable(vga_enable),
.scanlines_enable(scanlines_enable),
.freq_option(freq_option),
.turbo_enable(turbo_enable),
.csync_option(csync_option)
);
rasterint_ctrl control_rasterint (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(rasterint_dout),
.oe_n(oe_n_rasterint),
.rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable),
.raster_line(raster_line),
.raster_int_in_progress(raster_int_in_progress)
);
// DESHABILITADO!!!!!!!!!!!!!!!!!!!!!!!!!
nmievents nmi_especial_de_antonio (
.clk(1'b0 /*cpuclkplain*/),
.rst_n(rst_n & mrst_n & power_on_reset_n),
//------------------------------
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
//------------------------------
.userevents(user_fnt),
//------------------------------
.a(cpuaddr),
.m1_n(m1_n),
.mreq_n(mreq_n),
.rd_n(rd_n),
.dout(nmievents_dout),
.oe_n(oe_n_nmievents),
.nmiout_n(nmispecial_n),
.page_configrom_active(page_configrom_active)
);
ps2_mouse_kempston el_raton (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.clkps2(mouseclk),
.dataps2(mousedata),
//---------------------------------
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.kmouse_dout(kmouse_dout),
.oe_n_kmouse(oe_n_kmouse),
//---------------------------------
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.mousedata_dout(mousedata_dout),
.oe_n_mousedata(oe_n_mousedata),
.mousestatus_dout(mousestatus_dout),
.oe_n_mousestatus(oe_n_mousestatus)
);
multiboot el_multiboot (
.clk(clk28),
.clk_icap(clk14),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.zxuno_addr(zxuno_addr),
.regaddr_changed(regaddr_changed),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(multiboot_dout),
.oe_n(oe_n_multiboot)
);
specdrum the_specdrum (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.a(cpuaddr),
.iorq_n(iorq_n | disable_specdrum),
.wr_n(wr_n),
.d(cpudout),
.specdrum_left(specdrum_left),
.specdrum_right(specdrum_right)
);
disk_drive el_disco (
.clk(clk28),
.rst_n(rst_n & mrst_n & power_on_reset_n),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(cpudout),
.dout(diskdrive_dout),
.oe_n(oe_n_diskdrive)
);
pzx_player cassette_digital (
.clk(clk28),
.sram_access_allowed(enable_pzx),
.rst_n(power_on_reset_n & mrst_n & rst_n),
//--------------------
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(pzx_dout),
.oe_n(oe_n_pzx),
//--------------------
.in48kmode(in48kmode),
.play_in(play),
.stop_in(stop),
.jump_in(jump),
.pulse_out(pzx_output),
.playing(pzx_playing),
// -------------------
.sramaddr(pzx_addr),
.sramwe(write_data_pzx),
.sramdin(data_to_pzx),
.sramdout(data_from_pzx)
);
total_memory_register memrep (
.clk(clk28),
.poweron_rst_n(power_on_reset_n),
.in_boot_mode(in_boot_mode),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(memrep_dout),
.oe_n(oe_n_memrep)
);
zxunouart la_uart (
.clk(clk28),
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
.din(cpudout),
.dout(uart_dout),
.oe_n(oe_n_uart),
.uart_tx(uart_tx),
.uart_rx(uart_rx),
.uart_rts(uart_rts)
);
///////////////////////////////////
// AY-3-8912 SOUND
///////////////////////////////////
// BDIR BC2 BC1 MODE
// 0 1 0 inactive
// 0 1 1 read
// 1 1 0 write
// 1 1 1 address
assign bdir = (cpuaddr[15] && cpuaddr[1:0]==2'b01 && !iorq_n && !wr_n)? 1'b1 : 1'b0;
assign bc1 = (cpuaddr[15] && cpuaddr[1:0]==2'b01 && cpuaddr[14] && !iorq_n)? 1'b1 : 1'b0;
turbosound dos_ays (
.clk(clk3d5),
.clkreg(clk28),
.disable_ay(disable_ay),
.disable_turboay(disable_turboay),
.reset_n(rst_n & mrst_n & power_on_reset_n),
.bdir(bdir),
.bc1(bc1),
.din(cpudout),
.dout(ay_dout),
.oe_n(oe_n_ay),
.audio_out_ay1(ay1_audio),
.audio_out_ay2(ay2_audio),
.audio_out_ay1_splitted({ay1_cha, ay1_chb, ay1_chc}),
.audio_out_ay2_splitted({ay2_cha, ay2_chb, ay2_chc})
);
///////////////////////////////////
// SOUND MIXERS
///////////////////////////////////
// 9-bit mixer to generate different audio levels according to input sources
panner_and_mixer audio_mix (
.clk(clk28),
.mrst_n(mrst_n),
.a(cpuaddr[7:0]),
.iorq_n(iorq_n | disable_mixer),
.rd_n(rd_n),
.wr_n(wr_n),
.din(cpudout),
.dout(mixer_dout),
.oe_n(oe_n_mixer),
// Audio sources to mix
.mic(mic),
.spk(spk),
.ear(ear),
.ay1_cha(ay1_cha),
.ay1_chb(ay1_chb),
.ay1_chc(ay1_chc),
.ay2_cha(ay2_cha),
.ay2_chb(ay2_chb),
.ay2_chc(ay2_chc),
.specdrum_left(specdrum_left),
.specdrum_right(specdrum_right),
// PWM output mixed
.output_left(audio_out_left),
.output_right(audio_out_right)
);
endmodule