From 45d50cf420929a8b657f78612b3308935ed6dc77 Mon Sep 17 00:00:00 2001
From: yavor <yavor@dzver.bas.bg>
Date: Wed, 5 Sep 2018 09:40:28 +0300
Subject: [PATCH] Added one bit dac

---
 cores/Oric/source/clkdiv.vhd    | 52 ++++++++++++++++++++++++++
 cores/Oric/source/onebitadc.vhd | 66 +++++++++++++++++++++++++++++++++
 cores/generarlast.sh            |  7 ++++
 3 files changed, 125 insertions(+)
 create mode 100644 cores/Oric/source/clkdiv.vhd
 create mode 100644 cores/Oric/source/onebitadc.vhd
 create mode 100755 cores/generarlast.sh

diff --git a/cores/Oric/source/clkdiv.vhd b/cores/Oric/source/clkdiv.vhd
new file mode 100644
index 0000000..027dfc0
--- /dev/null
+++ b/cores/Oric/source/clkdiv.vhd
@@ -0,0 +1,52 @@
+-- clkdiv.vhd
+-- Description: Clock divider by DIVRATIO (a parameter).
+-- Author: Thientu Ho at FPGAcore.com
+-- Date: 2/28/2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity clkdiv is
+    generic (DIVRATIO : integer := 4);  -- ratio by which to divide the clk: clkout = clk/DIVRATIO. Conditions: DIVRATIO > 1.
+                                        -- if DIVRATIO is an even number, then clkout is 50% duty cycle.
+                                        -- if odd, clkout is greater than 50% duty cycle
+    port (
+        clk     : in std_logic;         -- input clock
+        nreset  : in std_logic;         -- active-low asynchronous global reset
+        --
+        clkout  : out std_logic         -- output clock
+    );
+end entity clkdiv;
+
+architecture RTL of clkdiv is
+signal clkout_i : std_logic;        -- internal clkout signal (can't use clkout directly because sometimes
+                                    -- you need to read present value of clkout, and it's illegal to read
+                                    -- an output port), to be buffered out to clkout port
+begin
+    
+    -- this process implement clock divider by counter:
+    -- The counter counts from 0 to DIVRATIO-1. At midpoint and end point, clkout is toggled.
+    -- For example, if DIVRATIO = 4:
+    -- clkout is toggled at count=1 and count=3, creating a 50% duty cycle clock, whose period equals 4 times
+    -- the input clock period.
+    clkdiv_proc : process (clk, nreset)
+    variable count : integer range 0 to DIVRATIO-1;
+    begin
+        if nreset='0' then          -- initialize power up reset conditions
+            clkout_i <= '0';
+            count := 0;
+        elsif rising_edge(clk) then
+            if count=DIVRATIO/2-1 then      -- toggle at half period
+                clkout_i <= not clkout_i;
+                count := count + 1;
+            elsif count=DIVRATIO-1 then     -- toggle at end 
+                clkout_i <= not clkout_i;
+                count := 0;                 -- reached end of clock period. reset count
+            else
+                count := count + 1;
+            end if;
+        end if;
+    end process;
+
+    clkout <= clkout_i;     -- buffer to output port
+end RTL;
diff --git a/cores/Oric/source/onebitadc.vhd b/cores/Oric/source/onebitadc.vhd
new file mode 100644
index 0000000..a2ab57f
--- /dev/null
+++ b/cores/Oric/source/onebitadc.vhd
@@ -0,0 +1,66 @@
+-- multiplexes led t for X-SP6-X9
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.std_logic_unsigned.all;
+	use ieee.numeric_std.all;
+        use ieee.std_logic_arith.all;
+
+entity XSP6X9_onebit is
+    generic (k : integer := 255);  -- ratio by which to divide the clk: clkout = clk/DIVRATIO.
+    port (
+        nreset  : in std_logic;         -- active-low asynchronous global reset
+	clk  : in  std_logic;
+	input : in  std_logic_vector(7 downto 0);
+	output   : out std_logic;
+        voutput : out std_logic_vector (7 downto 0)
+);
+end;
+
+architecture Implementation of XSP6X9_onebit is
+  signal final: std_logic_vector(15 downto 0);
+  signal sum : std_logic_vector(15 downto 0);
+  signal difference:std_logic_vector (7 downto 0);
+  signal product :std_logic_vector (15 downto 0);
+  signal divided_clock:std_logic;
+begin
+
+  inst_clock_div :entity work.clkdiv
+    generic map (
+      DIVRATIO => 512
+      )
+    port map (
+      nreset => nreset,
+      clk =>clk,
+      clkout => divided_clock
+      );
+
+  
+  change: process(divided_clock, nreset)
+    variable kvec: std_logic_vector(7 downto 0);
+  begin
+    if (nreset = '0') then
+      final <= (others => '1');
+      difference <= (others => '0');
+      product <= (others => '0');
+    else
+      if (rising_edge(divided_clock)) then
+        difference <= input - final(15 downto 8);
+        kvec := conv_std_logic_vector(k, 8);
+        product <= kvec * difference;
+        sum <= sum + product;
+        final <= sum;
+      end if;
+    end if;
+  end process;
+  outputbit: process(divided_clock, nreset)
+  begin
+    if (nreset = '0') then
+      output <= '1';
+    else
+      if (rising_edge(divided_clock)) then
+        output <= not final(15);
+        voutput <= final(15 downto 8);
+      end if;     
+    end if;
+  end process;
+end architecture Implementation;
diff --git a/cores/generarlast.sh b/cores/generarlast.sh
new file mode 100755
index 0000000..c386d80
--- /dev/null
+++ b/cores/generarlast.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+map      -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
+par      -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
+trce     -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
+bitgen   -intstyle ise -f "$machine".ut "$machine".ncd
+bit2bin "$machine".bit COREn."$2"
+cp  "$machine".bit "$machine"."$1".bit