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add changes by gitlab.com/emax73g

This commit is contained in:
antoniovillena 2022-05-31 15:23:43 +02:00
parent a8165d9556
commit 4b49d65e54
2 changed files with 286 additions and 276 deletions
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36
cores/Spectrum/common/ps2_port.v
View File

@ -149,14 +149,14 @@ module ps2_host_to_kb (
); );
`define PULLCLKLOW 3'b000 `define PULLCLKLOW 3'b000
`define PULLDATALOW 3'b001 `define PULLCLKDATALOW 3'b001
`define SENDDATA 3'b010 `define PULLDATALOW 3'b010
`define SENDPARITY 3'b011 `define SENDDATA 3'b011
`define RCVACK 3'b100 `define SENDPARITY 3'b100
`define RCVIDLE 3'b101 `define RCVACK 3'b101
`define SENDFINISHED 3'b110 `define RCVIDLE 3'b110
`define SENDFINISHED 3'b111
reg initial_kb_reset = 1'b1;
reg busy = 1'b0; reg busy = 1'b0;
reg error = 1'b0; reg error = 1'b0;
assign ps2busy = busy; assign ps2busy = busy;
@ -198,16 +198,6 @@ module ps2_host_to_kb (
always @(posedge clk) begin always @(posedge clk) begin
// Carga de rdata desde el exterior // Carga de rdata desde el exterior
`ifdef INITIAL_KB_RESET
if (initial_kb_reset) begin // Reset inicial de teclado para establecer el SET 2
initial_kb_reset <= 1'b0;
rdata <= 8'hFF;
busy <= 1'b1;
error <= 1'b0;
timeoutcnt <= 24'h000000;
state <= `PULLCLKLOW;
end
`endif
if (dataload) begin if (dataload) begin
rdata <= data; rdata <= data;
busy <= 1'b1; busy <= 1'b1;
@ -226,7 +216,13 @@ module ps2_host_to_kb (
case (state) case (state)
`PULLCLKLOW: begin // 280000 cuentas son 10ms para 28 MHz `PULLCLKLOW: begin // 280000 cuentas son 10ms para 28 MHz
if (timeoutcnt >= 24'd280000) begin if (timeoutcnt >= 24'd3360) begin
state <= `PULLCLKDATALOW;
timeoutcnt <= 24'h000000;
end
end
`PULLCLKDATALOW: begin
if (timeoutcnt >= 24'd280) begin
state <= `PULLDATALOW; state <= `PULLDATALOW;
shiftreg <= rdata; shiftreg <= rdata;
cntbits <= 3'd0; cntbits <= 3'd0;
@ -280,10 +276,10 @@ module ps2_host_to_kb (
endcase endcase
end end
assign ps2data_ext = (state == `PULLCLKLOW || state == `PULLDATALOW) ? 1'b0 : assign ps2data_ext = (state == `PULLCLKDATALOW || state == `PULLDATALOW) ? 1'b0 :
(state == `SENDDATA && shiftreg[0] == 1'b0) ? 1'b0 : (state == `SENDDATA && shiftreg[0] == 1'b0) ? 1'b0 :
(state == `SENDPARITY && paritycalculated == 1'b0) ? 1'b0 : // si lo que se va a enviar es un 1 (state == `SENDPARITY && paritycalculated == 1'b0) ? 1'b0 : // si lo que se va a enviar es un 1
1'bZ; // no se manda, sino que se pone la línea a alta impedancia 1'bZ; // no se manda, sino que se pone la línea a alta impedancia
assign ps2clk_ext = (state == `PULLCLKLOW) ? 1'b0 : assign ps2clk_ext = (state == `PULLCLKLOW || state == `PULLCLKDATALOW) ? 1'b0 :
1'bZ; 1'bZ;
endmodule endmodule

14
firmware/firmware.asm
View File

@ -250,6 +250,17 @@ kemp defb $1f, $1e, $1d, $1c, $0d ; Right Left Down Up Enter
start ld bc, chrend-sdtab start ld bc, chrend-sdtab
ldir ldir
wreg scan_code, $f6 ; $f6 = kb set defaults
halt
halt
wreg scan_code, $f0 ; $f0 + 2 = Set scan code set 2
halt
halt
wreg scan_code, $02
ld c, $05 ; 100msec delay
delay1 halt
dec c
jr nz, delay1
IF recovery=0 IF recovery=0
call alto loadch call alto loadch
ld hl, (scanli) ld hl, (scanli)
@ -463,7 +474,10 @@ star16 djnz star18
halt halt
wreg scan_code, $ed ; $ed + 2 = kb set leds + numlock wreg scan_code, $ed ; $ed + 2 = kb set leds + numlock
halt halt
halt
wreg scan_code, $02 wreg scan_code, $02
halt
halt
IF vertical=0 IF vertical=0
ld hl, $0017 ; Si se acaba el temporizador borrar ld hl, $0017 ; Si se acaba el temporizador borrar
ld de, $2001 ; lo de presione Break ld de, $2001 ; lo de presione Break