From 51d895802276bcfec30e250a23cac8fd5ffa10ad Mon Sep 17 00:00:00 2001 From: byrtolet Date: Tue, 20 Nov 2018 16:48:03 +0200 Subject: [PATCH] Made reset work + switch vga/composit work as well --- cores/Oric/source/controller_8dos.vhd | 26 +++--- cores/Oric/source/disk_ii.vhd | 26 +++--- cores/Oric/source/m6522.vhd | 116 +++++++++++++------------- cores/Oric/source/oricatmos.vhd | 60 +++++++++++-- cores/Oric/source/spi_controller.vhd | 46 +++++----- cores/Oric/source/ula.vhd | 22 ++--- 6 files changed, 169 insertions(+), 127 deletions(-) diff --git a/cores/Oric/source/controller_8dos.vhd b/cores/Oric/source/controller_8dos.vhd index 6d0d744..4a6e89d 100644 --- a/cores/Oric/source/controller_8dos.vhd +++ b/cores/Oric/source/controller_8dos.vhd @@ -50,7 +50,7 @@ architecture imp of controller_8dos is signal disk_D_OUT : std_logic_vector(7 downto 0); -- connection between spi_controller & disk_ii - signal IMAGE_NUMBER : unsigned(9 downto 0); + signal IMAGE_NUMBER : unsigned(9 downto 0) := "0000000001"; signal TRACK : unsigned(5 downto 0); signal TRACK_ADDR : unsigned(13 downto 0); signal TRACK_RAM_ADDR : unsigned(13 downto 0); @@ -68,23 +68,19 @@ architecture imp of controller_8dos is begin IMAGE_NUMBER_OUT <= std_logic_vector(IMAGE_NUMBER); - imgnum:process (CLK_24) + imgnum:process (CLK_24, RESETn) constant maxcount:integer := 1000000000; begin if (rising_edge(CLK_24)) then - if (RESETn = '0') then - IMAGE_NUMBER <= "0000000001"; - else - IMAGE_UP_old <= IMAGE_UP_cur; - IMAGE_UP_cur <= IMAGE_UP; - IMAGE_DOWN_old <= IMAGE_DOWN_cur; - IMAGE_DOWN_cur <= IMAGE_DOWN; - if (IMAGE_UP_cur = '0' and IMAGE_UP_old = '1') then - IMAGE_NUMBER <= IMAGE_NUMBER + 1; - end if; - if (IMAGE_DOWN_cur = '0' and IMAGE_DOWN_old = '1') and IMAGE_NUMBER >0 then - IMAGE_NUMBER <= IMAGE_NUMBER - 1; - end if; + IMAGE_UP_old <= IMAGE_UP_cur; + IMAGE_UP_cur <= IMAGE_UP; + IMAGE_DOWN_old <= IMAGE_DOWN_cur; + IMAGE_DOWN_cur <= IMAGE_DOWN; + if (IMAGE_UP_cur = '0' and IMAGE_UP_old = '1') then + IMAGE_NUMBER <= IMAGE_NUMBER + 1; + end if; + if (IMAGE_DOWN_cur = '0' and IMAGE_DOWN_old = '1') and IMAGE_NUMBER >0 then + IMAGE_NUMBER <= IMAGE_NUMBER - 1; end if; end if; end process; diff --git a/cores/Oric/source/disk_ii.vhd b/cores/Oric/source/disk_ii.vhd index 0654e2c..9f89f93 100644 --- a/cores/Oric/source/disk_ii.vhd +++ b/cores/Oric/source/disk_ii.vhd @@ -268,22 +268,20 @@ begin end process; -- Go to the next byte when the disk is accessed or if the counter times out - read_head : process (CLK) + read_head : process (CLK, RESETn) variable byte_delay : unsigned(8 downto 0); -- Accounts for disk spin rate begin - if rising_edge(CLK) then - if RESETn = '0' then - track_byte_addr <= (others => '0'); - byte_delay := (others => '0'); - else - byte_delay := byte_delay - 1; - if (read_disk = '1' and rising_PHI_2 = '1') then --or byte_delay = 0 then - byte_delay := "000000100"; - if track_byte_addr = X"33FE" then - track_byte_addr <= (others => '0'); - else - track_byte_addr <= track_byte_addr + 1; - end if; + if RESETn = '0' then + track_byte_addr <= (others => '0'); + byte_delay := (others => '0'); + elsif rising_edge(CLK) then + byte_delay := byte_delay - 1; + if (read_disk = '1' and rising_PHI_2 = '1') then --or byte_delay = 0 then + byte_delay := "000000100"; + if track_byte_addr = X"33FE" then + track_byte_addr <= (others => '0'); + else + track_byte_addr <= track_byte_addr + 1; end if; end if; end if; diff --git a/cores/Oric/source/m6522.vhd b/cores/Oric/source/m6522.vhd index ad5a8c1..e0a1068 100644 --- a/cores/Oric/source/m6522.vhd +++ b/cores/Oric/source/m6522.vhd @@ -609,32 +609,33 @@ begin --end if; end process; - p_timer1 : process + p_timer1 : process(CLK, RESET_L) begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if t1_load_counter or (t1_reload_counter and phase = "11") then - t1c( 7 downto 0) <= r_t1l_l; - t1c(15 downto 8) <= r_t1l_h; - elsif (phase="11") then - t1c <= t1c - "1"; - end if; + if RESET_L = '0' then + t1c_active <= false; + t1_irq <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if t1_load_counter or (t1_reload_counter and phase = "11") then + t1c( 7 downto 0) <= r_t1l_l; + t1c(15 downto 8) <= r_t1l_h; + elsif (phase="11") then + t1c <= t1c - "1"; + end if; - if t1_load_counter or t1_reload_counter then - t1c_active <= true; - elsif t1c_done then - t1c_active <= false; - end if; - if RESET_L = '0' then - t1c_active <= false; - end if; + if t1_load_counter or t1_reload_counter then + t1c_active <= true; + elsif t1c_done then + t1c_active <= false; + end if; - t1_toggle <= '0'; - if t1c_active and t1c_done then - t1_toggle <= '1'; - t1_irq <= '1'; - elsif RESET_L = '0' or t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then - t1_irq <= '0'; + t1_toggle <= '0'; + if t1c_active and t1c_done then + t1_toggle <= '1'; + t1_irq <= '1'; + elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then + t1_irq <= '0'; + end if; end if; end if; end process; @@ -662,46 +663,47 @@ begin --end if; end process; - p_timer2 : process + p_timer2 : process(CLK, RESET_L) variable ena : boolean; begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if (r_acr(5) = '0') then - ena := true; - else - ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge - end if; - - if t2_load_counter - -- or (t2_reload_counter and phase = "11") - then - -- not sure if t2c_reload should be here. Does timer2 just continue to - -- count down, or is it reloaded ? Reloaded makes more sense if using - -- it to generate a clock for the shift register. - t2c( 7 downto 0) <= r_t2l_l; - t2c(15 downto 8) <= r_t2l_h; - else - if (phase="11") and ena then -- or count mode - t2c <= t2c - "1"; + if RESET_L = '0' then + t2_irq <= '0'; + t2c_active <= false; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if (r_acr(5) = '0') then + ena := true; + else + ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge end if; - end if; - t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); + if t2_load_counter + -- or (t2_reload_counter and phase = "11") + then + -- not sure if t2c_reload should be here. Does timer2 just continue to + -- count down, or is it reloaded ? Reloaded makes more sense if using + -- it to generate a clock for the shift register. + t2c( 7 downto 0) <= r_t2l_l; + t2c(15 downto 8) <= r_t2l_h; + else + if (phase="11") and ena then -- or count mode + t2c <= t2c - "1"; + end if; + end if; - if t2_load_counter then - t2c_active <= true; - elsif t2c_done then - t2c_active <= false; - end if; - if RESET_L = '0' then - t2c_active <= false; - end if; + t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); - if t2c_active and t2c_done then - t2_irq <= '1'; - elsif RESET_L = '0' or t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then - t2_irq <= '0'; + if t2_load_counter then + t2c_active <= true; + elsif t2c_done then + t2c_active <= false; + end if; + + if t2c_active and t2c_done then + t2_irq <= '1'; + elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then + t2_irq <= '0'; + end if; end if; end if; end process; diff --git a/cores/Oric/source/oricatmos.vhd b/cores/Oric/source/oricatmos.vhd index 125ef89..9107b19 100644 --- a/cores/Oric/source/oricatmos.vhd +++ b/cores/Oric/source/oricatmos.vhd @@ -121,6 +121,11 @@ architecture RTL of ORIC is -- Resets signal loc_reset_n : std_logic; --active low + signal I_RESET_db : std_logic; --debounsed reset + signal I_NMI_db : std_logic; -- debounsed reset + signal loc_reset_sig : std_logic; --active low + signal loc_reset_p1 : std_logic; + signal loc_reset_p2 : std_logic; signal cpu_reset_n : std_logic; --active low signal cpu_reset : std_logic; --active low -- Internal clocks @@ -263,8 +268,8 @@ begin -- generate all the system clocks required ----------------------------------------------- - NMI_INT <= I_NMI and not key_end; - RESET_INT <= not I_RESET; + NMI_INT <= I_NMI_db and not key_end; + RESET_INT <= not I_RESET_db; inst_pll_base : PLL_BASE generic map ( @@ -312,7 +317,7 @@ begin LOCKED => pll_locked, -- Active high PLL lock signal CLKFBIN => CLKFB, -- Clock feedback input CLKIN => CLK_50, -- Clock input - RST => RESET_INT -- Asynchronous PLL reset + RST => '0' --RESET_INT -- Asynchronous PLL reset ); @@ -321,12 +326,51 @@ begin clk6 <= clkout5; ------------------------------------------------ + inst_debounce_reset : entity work.debounce + port map ( + clk => clk6, + button => I_RESET, + result => I_RESET_db + ); + inst_debounce_nmi : entity work.debounce + port map ( + clk => clk6, + button => I_NMI, + result => I_NMI_db + ); -- CLK_EXT <= ula_phi2; - + loc_reset_sig <= I_RESET_db and pll_locked and not (key_home and key_end) ; + reset_pr_1: process (clk6) + begin + if (rising_edge(clk6)) then + loc_reset_p1 <= loc_reset_sig; + loc_reset_p2 <= loc_reset_p1; + end if; + end process; + + -- Reset - loc_reset_n <= pll_locked and not (key_home and key_end); - cpu_reset_n <= loc_reset_n;-- and not key_home; + loc_reset_n <= loc_reset_p2 and loc_reset_sig ; + -- real mos needs running clock we start clock with loc_reset + -- and then dealy the cpu reset clock + cpu_delay_reset:process(clk6) + variable a:integer; + begin + if (rising_edge(clk6))then + if (loc_reset_n = '0') then + a:= 0; + cpu_reset_n <= '0'; + elsif(a <6000*50) then + a:= a + 1; + cpu_reset_n <= '0'; + else + cpu_reset_n <= '1'; + end if; + end if; + end process; + + -- cpu_reset_n <= loc_reset_n;-- and not key_home; cpu_reset <= not cpu_reset_n; ------------------------------------------------------------ -- CPU 6502 @@ -457,7 +501,7 @@ begin ------------------------------------------------------------ inst_ula : entity work.ULA port map ( - RESETn => cpu_reset_n, + RESETn => loc_reset_n, CLK => clk24, RW => cpu_rw, @@ -648,7 +692,7 @@ begin inst_key : entity work.keyboard port map( CLK => clk24, - RESETn => loc_reset_n, -- active high reset + RESETn => pll_locked, -- active high reset PS2CLK => PS2CLK1, PS2DATA => PS2DAT1, diff --git a/cores/Oric/source/spi_controller.vhd b/cores/Oric/source/spi_controller.vhd index 6185274..f09731f 100644 --- a/cores/Oric/source/spi_controller.vhd +++ b/cores/Oric/source/spi_controller.vhd @@ -127,7 +127,7 @@ begin -- Implements the combined "SD Card init", "track read" and "command" FSMs. -- TRACK_GOOD <= '1' when current_track = track and current_image = image and write_addr = TRACK_SIZE else '0'; - sd_fsm : process(spi_clk) + sd_fsm : process(spi_clk, RESETn) subtype cmd_t is std_logic_vector(5 downto 0); constant CMD0 : cmd_t := std_logic_vector(to_unsigned(0, 6)); constant CMD1 : cmd_t := std_logic_vector(to_unsigned(1, 6)); @@ -142,27 +142,27 @@ begin variable lba : unsigned(31 downto 0); begin - if rising_edge(spi_clk) then - ram_we <= '0'; - if RESETn = '0' then - state <= POWER_UP; - -- Deliberately out of range - current_track <= (others => '1'); - current_image <= (others => '1'); - sclk_sig <= '0'; - slow_clk <= true; - CS_N <= '1'; - command <= (others => '0'); - argument <= (others => '0'); - crc7 <= (others => '0'); - command_out <= (others => '1'); - counter := TO_UNSIGNED(0, 8); - byte_counter := TO_UNSIGNED(0, BLOCK_BITS); - write_addr <= (others => '0'); - high_capacity <= false; - version <= MMC; - lba := (others => '0'); - else + if RESETn = '0' then + state <= POWER_UP; + -- Deliberately out of range + current_track <= (others => '1'); + current_image <= (others => '1'); + sclk_sig <= '0'; + slow_clk <= true; + CS_N <= '1'; + command <= (others => '0'); + argument <= (others => '0'); + crc7 <= (others => '0'); + command_out <= (others => '1'); + counter := TO_UNSIGNED(0, 8); + byte_counter := TO_UNSIGNED(0, BLOCK_BITS); + write_addr <= (others => '0'); + high_capacity <= false; + version <= MMC; + lba := (others => '0'); + else + if rising_edge(spi_clk) then + ram_we <= '0'; case state is --------------------------------------------------------------------- @@ -476,7 +476,7 @@ begin end if; end if; sclk_sig <= not sclk_sig; - + -- when others => null; end case; end if; diff --git a/cores/Oric/source/ula.vhd b/cores/Oric/source/ula.vhd index 7ecb16e..58649b7 100644 --- a/cores/Oric/source/ula.vhd +++ b/cores/Oric/source/ula.vhd @@ -365,8 +365,10 @@ begin lRELOAD_SEL <= '1' when (lCTR_H >= 49) else '0'; -- Vertical Synchronisation - lVSYNC50n <= '0' when (lCTR_V >= 258) else '1'; -- 50Hz - lVSYNC60n <= '0' when (lCTR_V >= 241) else '1'; -- 60Hz + lVSYNC50n <= '0' when (lCTR_V >= 258) and (lCTR_V <= 259) else '1'; -- 50Hz + lVSYNC60n <= '0' when (lCTR_V >= 241) and (lCTR_V <= 242) else '1'; -- 60Hz + -- lVSYNC50n <= '0' when (lCTR_V >= 258) else '1'; -- 50Hz + -- lVSYNC60n <= '0' when (lCTR_V >= 241) else '1'; -- 60Hz lVSYNCn <= lVSYNC50n when lFREQ_SEL='1' else lVSYNC60n; -- Vertical Blank @@ -436,13 +438,13 @@ begin u_ld_reg: process(CLK_24) begin - if rising_edge(CLK_24) then - if (RESET_INT = '1') then - lREG_INK <= (others=>'1'); - lREG_STYLE <= (others=>'0'); - lREG_PAPER <= (others=>'0'); - lREG_MODE <= (others=>'0'); - elsif (lRELOAD_SEL = '1') then + if (RESET_INT = '1') then + lREG_INK <= (others=>'1'); + lREG_STYLE <= (others=>'0'); + lREG_PAPER <= (others=>'0'); + lREG_MODE <= (others=>'0'); + elsif rising_edge(CLK_24) then + if (lRELOAD_SEL = '1') then lREG_INK <= (others=>'1'); lREG_STYLE <= (others=>'0'); lREG_PAPER <= (others=>'0'); @@ -455,7 +457,7 @@ begin when others => null; end case; end if; - end if; + end if; end process; -- selector bits in mode/style registers