From 53d89bc203fceac3e3489881ead16d9bf582ff33 Mon Sep 17 00:00:00 2001
From: antoniovillena <espineter@yahoo.com>
Date: Tue, 3 May 2016 18:16:17 +0200
Subject: [PATCH] Limpio

---
 cores/Apple2/apple2.xise                | 420 ------------------------
 cores/Apple2/build/APPLE2_TOP.prj       |  15 +
 cores/Apple2/build/APPLE2_TOP.ut        |  30 ++
 cores/Apple2/build/APPLE2_TOP.xst       |  52 +++
 cores/Apple2/make.bat                   |  16 +
 cores/Apple2/source/apple2_zxuno_Ap.ucf |  91 +++++
 cores/Apple2/source/apple2_zxuno_v4.ucf |  91 +++++
 cores/Apple2/source/pines_zxuno_Ap.ucf  |  91 +++++
 cores/Apple2/source/pines_zxuno_v4.ucf  |  91 +++++
 9 files changed, 477 insertions(+), 420 deletions(-)
 delete mode 100644 cores/Apple2/apple2.xise
 create mode 100644 cores/Apple2/build/APPLE2_TOP.prj
 create mode 100644 cores/Apple2/build/APPLE2_TOP.ut
 create mode 100644 cores/Apple2/build/APPLE2_TOP.xst
 create mode 100644 cores/Apple2/make.bat
 create mode 100644 cores/Apple2/source/apple2_zxuno_Ap.ucf
 create mode 100644 cores/Apple2/source/apple2_zxuno_v4.ucf
 create mode 100644 cores/Apple2/source/pines_zxuno_Ap.ucf
 create mode 100644 cores/Apple2/source/pines_zxuno_v4.ucf

diff --git a/cores/Apple2/apple2.xise b/cores/Apple2/apple2.xise
deleted file mode 100644
index 8eb89be..0000000
--- a/cores/Apple2/apple2.xise
+++ /dev/null
@@ -1,420 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="source/apple2.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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-    <file xil_pn:name="source/character_rom.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="source/disk_ii.vhd" xil_pn:type="FILE_VHDL">
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-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="APPLE2_TOP" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="APPLE2_TOP_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="APPLE2_TOP_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="APPLE2_TOP_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="APPLE2_TOP_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="APPLE2_TOP" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="build" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="apple2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-10-31T12:10:04" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="20F74465B8DF45069504FE556347C21D" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-</project>
diff --git a/cores/Apple2/build/APPLE2_TOP.prj b/cores/Apple2/build/APPLE2_TOP.prj
new file mode 100644
index 0000000..c24450c
--- /dev/null
+++ b/cores/Apple2/build/APPLE2_TOP.prj
@@ -0,0 +1,15 @@
+vhdl work "../source/character_rom.vhd"
+vhdl work "../source/video_generator.vhd"
+vhdl work "../source/timing_generator.vhd"
+vhdl work "../source/PS2_Ctrl.vhd"
+vhdl work "../source/main_roms.vhd"
+vhdl work "../source/disk_ii_rom.vhd"
+vhdl work "../source/cpu6502.vhd"
+vhdl work "../source/vga_controller.vhd"
+vhdl work "../source/spi_controller.vhd"
+vhdl work "../source/keyboard.vhd"
+vhdl work "../source/disk_ii.vhd"
+vhdl work "../source/dac.vhd"
+vhdl work "../source/clocks.vhd"
+vhdl work "../source/apple2.vhd"
+vhdl work "../source/apple2_top.vhd"
diff --git a/cores/Apple2/build/APPLE2_TOP.ut b/cores/Apple2/build/APPLE2_TOP.ut
new file mode 100644
index 0000000..dfd4060
--- /dev/null
+++ b/cores/Apple2/build/APPLE2_TOP.ut
@@ -0,0 +1,30 @@
+-w
+-g Binary:no
+-g Compress
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/cores/Apple2/build/APPLE2_TOP.xst b/cores/Apple2/build/APPLE2_TOP.xst
new file mode 100644
index 0000000..5a89d6b
--- /dev/null
+++ b/cores/Apple2/build/APPLE2_TOP.xst
@@ -0,0 +1,52 @@
+set -tmpdir "projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn build\APPLE2_TOP.prj
+-ofn APPLE2_TOP
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top APPLE2_TOP
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/cores/Apple2/make.bat b/cores/Apple2/make.bat
new file mode 100644
index 0000000..f88f5ca
--- /dev/null
+++ b/cores/Apple2/make.bat
@@ -0,0 +1,16 @@
+if not exist projnav.tmp mkdir projnav.tmp
+call xst      -intstyle ise -ifn build/APPLE2_TOP.xst -ofn build/APPLE2_TOP.syr
+call :generar v2
+call :generar v3
+call :generar v4
+call :generar Ap
+goto :eof
+
+:generar
+call ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc source/apple2_zxuno_%1.ucf -p xc6slx9-tqg144-2 build\APPLE2_TOP.ngc build\APPLE2_TOP.ngd
+call map      -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o build\APPLE2_TOP_map.ncd build\APPLE2_TOP.ngd build\APPLE2_TOP.pcf
+call par      -intstyle ise -w -ol high -mt 4 build\APPLE2_TOP_map.ncd build\APPLE2_TOP.ncd build\APPLE2_TOP.pcf
+call trce     -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml build\APPLE2_TOP.twx build\APPLE2_TOP.ncd -o build\APPLE2_TOP.twr build\APPLE2_TOP.pcf
+call bitgen   -intstyle ise -f build\APPLE2_TOP.ut build\APPLE2_TOP.ncd
+copy /y apple2_top.bit Apple2.%1.bit
+:eof
\ No newline at end of file
diff --git a/cores/Apple2/source/apple2_zxuno_Ap.ucf b/cores/Apple2/source/apple2_zxuno_Ap.ucf
new file mode 100644
index 0000000..16ebbb3
--- /dev/null
+++ b/cores/Apple2/source/apple2_zxuno_Ap.ucf
@@ -0,0 +1,91 @@
+# UCF for ZX-UNO
+NET CLOCK50           LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET LED               LOC="P2"   | IOSTANDARD = LVCMOS33;
+
+# Video output  
+NET VGA_R(2)          LOC="P97"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_R(1)          LOC="P95"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_R(0)          LOC="P94"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(2)          LOC="P88"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(1)          LOC="P87"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(0)          LOC="P85"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(2)          LOC="P84"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(1)          LOC="P83"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(0)          LOC="P82"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_HS            LOC="P93"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_VS            LOC="P92"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET "stdn"            LOC="P51"  | IOSTANDARD = LVCMOS33;
+#NET "stdnb"           LOC="P50"  | IOSTANDARD = LVCMOS33;
+                           
+# Sound input/output       
+NET O_AUDIO_L         LOC="P98"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET O_AUDIO_R         LOC="P99"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET PS2_CLK           LOC="P143" | IOSTANDARD = LVCMOS33;
+NET PS2_DAT           LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "mouseclk"        LOC="P57"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET SRAM_ADDR<0>      LOC="P115" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<1>      LOC="P116" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<2>      LOC="P117" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<3>      LOC="P119" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<4>      LOC="P120" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<5>      LOC="P123" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<6>      LOC="P126" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<7>      LOC="P131" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<8>      LOC="P127" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<9>      LOC="P124" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<10>     LOC="P118" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<11>     LOC="P121" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<12>     LOC="P133" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<13>     LOC="P132" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<14>     LOC="P137" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<15>     LOC="P140" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<16>     LOC="P139" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<17>     LOC="P141" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<18>     LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+NET SRAM_DQ<0>        LOC="P114" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<1>        LOC="P112" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<2>        LOC="P111" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<3>        LOC="P105" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<4>        LOC="P104" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<5>        LOC="P102" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<6>        LOC="P101" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ<7>        LOC="P100" | IOSTANDARD = LVCMOS33;
+
+NET SRAM_WE_N         LOC="P134" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET SD_DAT3           LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_CLK            LOC="P80"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_CMD            LOC="P79"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_DAT            LOC="P81"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET JOYSTICK1(3)      LOC="P74"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(2)      LOC="P67"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(1)      LOC="P59"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(0)      LOC="P58"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET BTN2              LOC="P75"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(4)      LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+NET I_RESET           LOC="P51"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET LED2              LOC="P11"  | IOSTANDARD = LVCMOS33;
diff --git a/cores/Apple2/source/apple2_zxuno_v4.ucf b/cores/Apple2/source/apple2_zxuno_v4.ucf
new file mode 100644
index 0000000..b13a49d
--- /dev/null
+++ b/cores/Apple2/source/apple2_zxuno_v4.ucf
@@ -0,0 +1,91 @@
+# UCF for ZX-UNO
+NET CLOCK50           LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET LED               LOC="P11"  | IOSTANDARD = LVCMOS33;
+
+# Video output    
+NET VGA_R(2)          LOC="P81"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_R(1)          LOC="P80"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_R(0)          LOC="P79"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(2)          LOC="P84"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(1)          LOC="P83"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_G(0)          LOC="P82"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(2)          LOC="P93"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(1)          LOC="P92"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_B(0)          LOC="P88"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_HS            LOC="P87"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET VGA_VS            LOC="P85"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET "stdn"            LOC="P66"  | IOSTANDARD = LVCMOS33;
+#NET "stdnb"           LOC="P67"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET O_AUDIO_L         LOC="P10"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET O_AUDIO_R         LOC="P9"   | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET "ear"             LOC="P94" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET PS2_CLK           LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET PS2_DAT           LOC="P98"  | IOSTANDARD = LVCMOS33;
+#NET "mouseclk"        LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET SRAM_ADDR<0>      LOC="P141" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<1>      LOC="P139" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<2>      LOC="P137" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<3>      LOC="P134" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<4>      LOC="P133" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<5>      LOC="P120" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<6>      LOC="P118" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<7>      LOC="P116" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<8>      LOC="P114" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<9>      LOC="P112  | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<10>     LOC="P104" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<11>     LOC="P102" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<12>     LOC="P101" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<13>     LOC="P100" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<14>     LOC="P111" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<15>     LOC="P131" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<16>     LOC="P138" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<17>     LOC="P140" | IOSTANDARD = LVCMOS33;
+NET SRAM_ADDR<18>     LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+NET SRAM_DQ(0)        LOC="P132" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(1)        LOC="P127" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(2)        LOC="P124" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(3)        LOC="P123" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(4)        LOC="P115" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(5)        LOC="P117" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(6)        LOC="P119" | IOSTANDARD = LVCMOS33;
+NET SRAM_DQ(7)        LOC="P126" | IOSTANDARD = LVCMOS33;  
+
+NET SRAM_WE_N         LOC="P121" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET SD_DAT3           LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_CLK            LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_CMD            LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET SD_DAT            LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET JOYSTICK1(3)      LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(2)      LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(1)      LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(0)      LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET BTN2              LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET JOYSTICK1(4)      LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+NET I_RESET           LOC="P51"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+#NET LED2              LOC="P11"  | IOSTANDARD = LVCMOS33;
diff --git a/cores/Apple2/source/pines_zxuno_Ap.ucf b/cores/Apple2/source/pines_zxuno_Ap.ucf
new file mode 100644
index 0000000..de59282
--- /dev/null
+++ b/cores/Apple2/source/pines_zxuno_Ap.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "testled"         LOC="P2"   | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "r<2>"            LOC="P97"  | IOSTANDARD = LVCMOS33;
+NET "r<1>"            LOC="P95"  | IOSTANDARD = LVCMOS33;
+NET "r<0>"            LOC="P94"  | IOSTANDARD = LVCMOS33;
+NET "g<2>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "g<1>"            LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "g<0>"            LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "b<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "b<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "b<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "stdn"            LOC="P51"  | IOSTANDARD = LVCMOS33;
+NET "stdnb"           LOC="P50"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "audio_out_left"  LOC="P98"  | IOSTANDARD = LVCMOS33;
+NET "audio_out_right" LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "clkps2"          LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2"         LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "mouseclk"        LOC="P57"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
+  
+# SRAM  
+NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>"    LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+
+NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "sd_cs_n"         LOC="P78"  | IOSTANDARD = LVCMOS33;
+NET "sd_clk"          LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "sd_mosi"         LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "sd_miso"         LOC="P81"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "joyup"           LOC="P74"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joydown"         LOC="P67"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyleft"         LOC="P59"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyright"        LOC="P58"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyfire"         LOC="P75"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+NET "sysclk"          PERIOD=35 ns;
+
diff --git a/cores/Apple2/source/pines_zxuno_v4.ucf b/cores/Apple2/source/pines_zxuno_v4.ucf
new file mode 100644
index 0000000..747e025
--- /dev/null
+++ b/cores/Apple2/source/pines_zxuno_v4.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "testled"         LOC="P11"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "r<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "r<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "r<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "g<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "g<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "b<2>"            LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "b<1>"            LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "b<0>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "stdn"            LOC="P66"  | IOSTANDARD = LVCMOS33;
+NET "stdnb"           LOC="P67"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "audio_out_left"  LOC="P10"  | IOSTANDARD = LVCMOS33;
+NET "audio_out_right" LOC="P9"   | IOSTANDARD = LVCMOS33;
+NET "ear"             LOC="P94"  | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "clkps2"          LOC="P99"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "mouseclk"        LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET "sram_addr<0>"    LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>"    LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>"    LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>"    LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>"    LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>"    LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>"   LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>"   LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>"   LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>"   LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>"   LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+
+NET "sram_we_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "sd_cs_n"         LOC="P59"  | IOSTANDARD = LVCMOS33;
+NET "sd_clk"          LOC="P75"  | IOSTANDARD = LVCMOS33;
+NET "sd_mosi"         LOC="P74"  | IOSTANDARD = LVCMOS33;
+NET "sd_miso"         LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "joyup"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joydown"         LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyleft"         LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyright"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "joyfire"         LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+NET "sysclk"          PERIOD=35 ns;
+