From 576bad9c8109288ea0cd65a4a83bb781e1090003 Mon Sep 17 00:00:00 2001 From: antoniovillena Date: Sun, 11 Dec 2016 20:01:51 +0100 Subject: [PATCH] =?UTF-8?q?A=C3=B1ado=20ficheros=20que=20faltan?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- cores/curso/ch03/disp_shift.vhd | 52 +++++++++ cores/curso/ch03/fp_adder_test.prj | 4 + cores/curso/ch03/fp_adder_test.ut | 30 ++++++ cores/curso/ch03/fp_adder_test.xst | 53 ++++++++++ cores/curso/ch03/hex_to_sseg_test.ut | 3 +- cores/curso/ch03/list_ch03_16_17_shift.vhd | 39 +++++++ cores/curso/ch03/list_ch03_18_shift_test.vhd | 32 ++++++ cores/curso/ch03/list_ch03_19_fp.vhd | 106 +++++++++++++++++++ cores/curso/ch03/list_ch03_20_fp_test.vhd | 70 ++++++++++++ cores/curso/ch03/make.bat | 15 ++- cores/curso/ch03/shifter_test.prj | 3 + cores/curso/ch03/shifter_test.ut | 30 ++++++ cores/curso/ch03/shifter_test.xst | 53 ++++++++++ cores/curso/ch03/sm_add_test.ut | 3 +- 14 files changed, 484 insertions(+), 9 deletions(-) create mode 100644 cores/curso/ch03/disp_shift.vhd create mode 100644 cores/curso/ch03/fp_adder_test.prj create mode 100644 cores/curso/ch03/fp_adder_test.ut create mode 100644 cores/curso/ch03/fp_adder_test.xst create mode 100644 cores/curso/ch03/list_ch03_16_17_shift.vhd create mode 100644 cores/curso/ch03/list_ch03_18_shift_test.vhd create mode 100644 cores/curso/ch03/list_ch03_19_fp.vhd create mode 100644 cores/curso/ch03/list_ch03_20_fp_test.vhd create mode 100644 cores/curso/ch03/shifter_test.prj create mode 100644 cores/curso/ch03/shifter_test.ut create mode 100644 cores/curso/ch03/shifter_test.xst diff --git a/cores/curso/ch03/disp_shift.vhd b/cores/curso/ch03/disp_shift.vhd new file mode 100644 index 0000000..93024f1 --- /dev/null +++ b/cores/curso/ch03/disp_shift.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +entity disp_shift is + port( + clk, reset: in std_logic; + inp: in std_logic_vector(7 downto 0); + an: out std_logic_vector(3 downto 0); + sseg: out std_logic_vector(7 downto 0) + ); +end disp_shift ; + +architecture arch of disp_shift is + -- refreshing rate around 800 Hz (50MHz/2^16) + constant N: integer:=18; + signal q_reg, q_next: unsigned(N-1 downto 0); + signal sel: std_logic_vector(1 downto 0); +begin + -- register + process(clk,reset) + begin + if reset='1' then + q_reg <= (others=>'0'); + elsif (clk'event and clk='1') then + q_reg <= q_next; + end if; + end process; + + -- next-state logic for the counter + q_next <= q_reg + 1; + + -- 2 MSBs of counter to control 4-to-1 multiplexing + -- and to generate active-low enable signal + sel <= std_logic_vector(q_reg(N-1 downto N-2)); + process(sel,inp) + begin + case sel is + when "00" => + an <= "1110"; + sseg <= not ("000" & inp(0) & '0' & inp(1) & "00"); + when "01" => + an <= "1101"; + sseg <= not ("000" & inp(2) & '0' & inp(3) & "00"); + when "10" => + an <= "1011"; + sseg <= not ("000" & inp(4) & '0' & inp(5) & "00"); + when others => + an <= "0111"; + sseg <= not ("000" & inp(6) & '0' & inp(7) & "00"); + end case; + end process; +end arch; diff --git a/cores/curso/ch03/fp_adder_test.prj b/cores/curso/ch03/fp_adder_test.prj new file mode 100644 index 0000000..23dd76c --- /dev/null +++ b/cores/curso/ch03/fp_adder_test.prj @@ -0,0 +1,4 @@ +vhdl work "list_ch03_19_fp.vhd" +vhdl work "hex_to_sseg.vhd" +vhdl work "disp_mux.vhd" +vhdl work "list_ch03_20_fp_test.vhd" diff --git a/cores/curso/ch03/fp_adder_test.ut b/cores/curso/ch03/fp_adder_test.ut new file mode 100644 index 0000000..a9facca --- /dev/null +++ b/cores/curso/ch03/fp_adder_test.ut @@ -0,0 +1,30 @@ +-w +-g Binary:no +-g Compress +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/cores/curso/ch03/fp_adder_test.xst b/cores/curso/ch03/fp_adder_test.xst new file mode 100644 index 0000000..e917072 --- /dev/null +++ b/cores/curso/ch03/fp_adder_test.xst @@ -0,0 +1,53 @@ +set -tmpdir "projnav.tmp" +set -xsthdpdir "xst" +run +-ifn fp_adder_test.prj +-infer_ramb8 No -loop_iteration_limit 32768 +-ofn fp_adder_test +-ofmt NGC +-p xc6slx9-2-tqg144 +-top fp_adder_test +-opt_mode Speed +-opt_level 2 +-power NO +-uc "timings.xcf" +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints YES +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract NO +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync YES +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/cores/curso/ch03/hex_to_sseg_test.ut b/cores/curso/ch03/hex_to_sseg_test.ut index e72e557..a9facca 100644 --- a/cores/curso/ch03/hex_to_sseg_test.ut +++ b/cores/curso/ch03/hex_to_sseg_test.ut @@ -11,8 +11,7 @@ -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF --g ExtMasterCclk_en:Yes --g ExtMasterCclk_divide:50 +-g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No diff --git a/cores/curso/ch03/list_ch03_16_17_shift.vhd b/cores/curso/ch03/list_ch03_16_17_shift.vhd new file mode 100644 index 0000000..64d28e4 --- /dev/null +++ b/cores/curso/ch03/list_ch03_16_17_shift.vhd @@ -0,0 +1,39 @@ +-- Listing 3.16 +library ieee; +use ieee.std_logic_1164.all; +entity barrel_shifter is + port( + a: in std_logic_vector(7 downto 0); + amt: in std_logic_vector(2 downto 0); + y: out std_logic_vector(7 downto 0) + ); +end barrel_shifter ; + +architecture sel_arch of barrel_shifter is +begin + with amt select + y<= a when "000", + a(0) & a(7 downto 1) when "001", + a(1 downto 0) & a(7 downto 2) when "010", + a(2 downto 0) & a(7 downto 3) when "011", + a(3 downto 0) & a(7 downto 4) when "100", + a(4 downto 0) & a(7 downto 5) when "101", + a(5 downto 0) & a(7 downto 6) when "110", + a(6 downto 0) & a(7) when others; -- 111 +end sel_arch; + + +-- Listing 3.17 +architecture multi_stage_arch of barrel_shifter is + signal s0, s1: std_logic_vector(7 downto 0); +begin + -- stage 0, shift 0 or 1 bit + s0 <= a(0) & a(7 downto 1) when amt(0)='1' else + a; + -- stage 1, shift 0 or 2 bits + s1 <= s0(1 downto 0) & s0(7 downto 2) when amt(1)='1' else + s0; + -- stage 2, shift 0 or 4 bits + y <= s1(3 downto 0) & s1(7 downto 4) when amt(2)='1' else + s1; +end multi_stage_arch ; diff --git a/cores/curso/ch03/list_ch03_18_shift_test.vhd b/cores/curso/ch03/list_ch03_18_shift_test.vhd new file mode 100644 index 0000000..196239b --- /dev/null +++ b/cores/curso/ch03/list_ch03_18_shift_test.vhd @@ -0,0 +1,32 @@ +-- Listing 3.18 +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +entity shifter_test is + port( + clk: in std_logic; + bot: in std_logic_vector(4 downto 0); + sw: in std_logic_vector(7 downto 0); + led: out std_logic_vector(4 downto 0); + an: out std_logic_vector(3 downto 0); + sseg: out std_logic_vector(7 downto 0) + ); +end shifter_test; + +architecture arch of shifter_test is + signal miled: std_logic_vector(7 downto 0); + signal btn : std_logic_vector(2 downto 0); +begin + + btn <= not (bot(4) & bot (2) & bot(0)); + led <= not bot; + + -- instantiate 7-seg LED display time-multiplexing module + disp_unit: entity work.disp_shift + port map( + clk=>clk, reset=>'0', + inp=>miled, an=>an, sseg=>sseg); + + shift_unit: entity work.barrel_shifter(multi_stage_arch) + port map(a=>sw, amt=>btn, y=>miled); +end arch; diff --git a/cores/curso/ch03/list_ch03_19_fp.vhd b/cores/curso/ch03/list_ch03_19_fp.vhd new file mode 100644 index 0000000..5900398 --- /dev/null +++ b/cores/curso/ch03/list_ch03_19_fp.vhd @@ -0,0 +1,106 @@ +-- Listing 3.19 +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +entity fp_adder is + port ( + sign1, sign2: in std_logic; + exp1, exp2: in std_logic_vector(3 downto 0); + frac1, frac2: in std_logic_vector(7 downto 0); + sign_out: out std_logic; + exp_out: out std_logic_vector(3 downto 0); + frac_out: out std_logic_vector(7 downto 0) + ); +end fp_adder ; + +architecture arch of fp_adder is + -- suffix b, s, a, n for + -- big, small, aligned, normalized number + signal signb, signs: std_logic; + signal expb, exps, expn: unsigned(3 downto 0); + signal fracb, fracs, fraca, fracn: unsigned(7 downto 0); + signal sum_norm: unsigned(7 downto 0); + signal exp_diff: unsigned(3 downto 0); + signal sum: unsigned(8 downto 0); --one extra for carry + signal lead0: unsigned(2 downto 0); +begin + -- 1st stage: sort to find the larger number + process (sign1, sign2, exp1, exp2, frac1, frac2) + begin + if (exp1 & frac1) > (exp2 & frac2) then + signb <= sign1; + signs <= sign2; + expb <= unsigned(exp1); + exps <= unsigned(exp2); + fracb <= unsigned(frac1); + fracs <= unsigned(frac2); + else + signb <= sign2; + signs <= sign1; + expb <= unsigned(exp2); + exps <= unsigned(exp1); + fracb <= unsigned(frac2); + fracs <= unsigned(frac1); + end if; + end process; + + -- 2nd stage: align smaller number + exp_diff <= expb - exps; + with exp_diff select + fraca <= + fracs when "0000", + "0" & fracs(7 downto 1) when "0001", + "00" & fracs(7 downto 2) when "0010", + "000" & fracs(7 downto 3) when "0011", + "0000" & fracs(7 downto 4) when "0100", + "00000" & fracs(7 downto 5) when "0101", + "000000" & fracs(7 downto 6) when "0110", + "0000000" & fracs(7) when "0111", + "00000000" when others; + + -- 3rd stage: add/substract + sum <= ('0' & fracb) + ('0' & fraca) when signb=signs else + ('0' & fracb) - ('0' & fraca); + + -- 4th stage: normalize + -- count leading 0s + lead0 <= "000" when (sum(7)='1') else + "001" when (sum(6)='1') else + "010" when (sum(5)='1') else + "011" when (sum(4)='1') else + "100" when (sum(3)='1') else + "101" when (sum(2)='1') else + "110" when (sum(1)='1') else + "111"; + -- shift significand according to leading 0 + with lead0 select + sum_norm <= + sum(7 downto 0) when "000", + sum(6 downto 0) & '0' when "001", + sum(5 downto 0) & "00" when "010", + sum(4 downto 0) & "000" when "011", + sum(3 downto 0) & "0000" when "100", + sum(2 downto 0) & "00000" when "101", + sum(1 downto 0) & "000000" when "110", + sum(0) & "0000000" when others; + + -- normalize with special conditions + process(sum,sum_norm,expb,lead0) + begin + if sum(8)='1' then -- w/ carry out; shift frac to right + expn <= expb + 1; + fracn <= sum(8 downto 1); + elsif (lead0 > expb) then -- too small to normalize; + expn <= (others=>'0'); -- set to 0 + fracn <= (others=>'0'); + else + expn <= expb - lead0; + fracn <= sum_norm; + end if; + end process; + + -- form output + sign_out <= signb; + exp_out <= std_logic_vector(expn); + frac_out <= std_logic_vector(fracn); +end arch; diff --git a/cores/curso/ch03/list_ch03_20_fp_test.vhd b/cores/curso/ch03/list_ch03_20_fp_test.vhd new file mode 100644 index 0000000..024f3d4 --- /dev/null +++ b/cores/curso/ch03/list_ch03_20_fp_test.vhd @@ -0,0 +1,70 @@ +-- Listing 3.20 +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +entity fp_adder_test is + port( + clk: in std_logic; + bot: in std_logic_vector(4 downto 0); + sw: in std_logic_vector(7 downto 0); + led: out std_logic_vector(4 downto 0); + an: out std_logic_vector(3 downto 0); + sseg: out std_logic_vector(7 downto 0) + ); +end fp_adder_test; + +architecture arch of fp_adder_test is + signal btn: std_logic_vector(3 downto 0); + signal sign1, sign2: std_logic; + signal exp1, exp2: std_logic_vector(3 downto 0); + signal frac1, frac2: std_logic_vector(7 downto 0); + signal sign_out: std_logic; + signal exp_out: std_logic_vector(3 downto 0); + signal frac_out: std_logic_vector(7 downto 0); + signal led3, led2, led1, led0: + std_logic_vector(6 downto 0); +begin + + btn <= not bot(3 downto 0); + led <= not bot; + + -- set up the fp adder input signals + sign1 <= '0'; + exp1 <= "1000"; + frac1<= '1' & sw(1) & sw(0) & "10101"; + sign2 <= sw(7); + exp2 <= btn; + frac2 <= '1' & sw(6 downto 0); + + -- instantiate fp adder + fp_add_unit: entity work.fp_adder + port map( + sign1=>sign1, sign2=>sign2, exp1=>exp1, exp2=>exp2, + frac1=>frac1, frac2=>frac2, + sign_out=>sign_out, exp_out=>exp_out, + frac_out=>frac_out + ); + + -- instantiate three instances of hex decoders + -- exponent + sseg_unit_0: entity work.hex_to_sseg + port map(hex=>exp_out, sseg=>led0); + -- 4 LSBs of fraction + sseg_unit_1: entity work.hex_to_sseg + port map(hex=>frac_out(3 downto 0), sseg=>led1); + -- 4 MSBs of fraction + sseg_unit_2: entity work.hex_to_sseg + port map(hex=>frac_out(7 downto 4), sseg=>led2); + -- sign + led3 <= "1111110" when sign_out='1' else -- middle bar + "1111111"; -- blank + + -- instantiate 7-seg LED display time-multiplexing module + disp_unit: entity work.disp_mux + port map( + clk=>clk, reset=>'0', + in0=>led0, in1=>led1, in2=>led2, in3=>led3, + point=>'0', colon=>'1', + an=>an, sseg=>sseg + ); +end arch; diff --git a/cores/curso/ch03/make.bat b/cores/curso/ch03/make.bat index a9e19c1..48be00f 100644 --- a/cores/curso/ch03/make.bat +++ b/cores/curso/ch03/make.bat @@ -1,10 +1,15 @@ -SET machine=hex_to_sseg_test SET speed=2 SET ruta_ucf=ch03 SET ruta_bat=..\..\ -rem call %ruta_bat%genxst.bat -rem call %ruta_bat%generar.bat v4 +call :genbitstream hex_to_sseg_test +call :genbitstream sm_add_test +call :genbitstream shifter_test +call :genbitstream fp_adder_test +goto :eof -SET machine=sm_add_test +:genbitstream +SET machine=%1 call %ruta_bat%genxst.bat -call %ruta_bat%generar.bat v4 +call %ruta_bat%generar.bat v4 ZX1 +copy /y COREn.ZX1 %ruta_bat%.ZX1 +goto :eof diff --git a/cores/curso/ch03/shifter_test.prj b/cores/curso/ch03/shifter_test.prj new file mode 100644 index 0000000..dc17bee --- /dev/null +++ b/cores/curso/ch03/shifter_test.prj @@ -0,0 +1,3 @@ +vhdl work "list_ch03_18_shift_test.vhd" +vhdl work "list_ch03_16_17_shift.vhd" +vhdl work "disp_shift.vhd" diff --git a/cores/curso/ch03/shifter_test.ut b/cores/curso/ch03/shifter_test.ut new file mode 100644 index 0000000..a9facca --- /dev/null +++ b/cores/curso/ch03/shifter_test.ut @@ -0,0 +1,30 @@ +-w +-g Binary:no +-g Compress +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/cores/curso/ch03/shifter_test.xst b/cores/curso/ch03/shifter_test.xst new file mode 100644 index 0000000..242d6ae --- /dev/null +++ b/cores/curso/ch03/shifter_test.xst @@ -0,0 +1,53 @@ +set -tmpdir "projnav.tmp" +set -xsthdpdir "xst" +run +-ifn shifter_test.prj +-infer_ramb8 No -loop_iteration_limit 32768 +-ofn shifter_test +-ofmt NGC +-p xc6slx9-2-tqg144 +-top shifter_test +-opt_mode Speed +-opt_level 2 +-power NO +-uc "timings.xcf" +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints YES +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract NO +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync YES +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/cores/curso/ch03/sm_add_test.ut b/cores/curso/ch03/sm_add_test.ut index e72e557..a9facca 100644 --- a/cores/curso/ch03/sm_add_test.ut +++ b/cores/curso/ch03/sm_add_test.ut @@ -11,8 +11,7 @@ -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF --g ExtMasterCclk_en:Yes --g ExtMasterCclk_divide:50 +-g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No