diff --git a/cores/MasterSystem/all.mem b/cores/MasterSystem/all.mem
index 8a5f75a..2928813 100644
--- a/cores/MasterSystem/all.mem
+++ b/cores/MasterSystem/all.mem
@@ -22,545 +22,553 @@
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+@00002390 C9
 /* http://srecord.sourceforge.net/ */
 @00008400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 @00008410 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/cores/MasterSystem/bootloader/Makefile b/cores/MasterSystem/bootloader/Makefile
index 0f92749..432f99d 100644
--- a/cores/MasterSystem/bootloader/Makefile
+++ b/cores/MasterSystem/bootloader/Makefile
@@ -6,6 +6,7 @@ CFLAGS = +sms #-DDEBUG #-DDEBUG_FAT
 C_FILES=main.c console.c debug.c sd.c fat.c
 OBJECT_FILES=$(C_FILES:%.c=%.o)
 
+#PATH_EMU=/home/ben/prog/JSMS
 PATH_EMU=/home/backup/workspace/JSMS
 EMU=java -cp $(PATH_EMU)/bin/ org.jsms.awt.SwingJsms
 
@@ -22,6 +23,8 @@ font.mem: font.bin
 	srec_cat font.bin -binary -offset 0x8400 -line_length 59 -o font.mem -vmem 8
 
 
+
+
 boot.o: $(OBJECT_FILES)
 	$(LD) $(CFLAGS) $(OBJECT_FILES) -o $@ -m
 
@@ -45,6 +48,8 @@ vram.bin: vram.mem
 	srec_cat vram.mem -vmem -offset -0x8000 -fill 0 0 0x4000 -o vram.bin -binary
 
 
+
+
 clean:
 	rm -f *.o *.opt boot.map zcc_opt.def
 	rm -f *.mem vram.bin boot.sms
diff --git a/cores/MasterSystem/bootloader/all.mem b/cores/MasterSystem/bootloader/all.mem
index 8a5f75a..2928813 100644
--- a/cores/MasterSystem/bootloader/all.mem
+++ b/cores/MasterSystem/bootloader/all.mem
@@ -22,545 +22,553 @@
 @00000140 FF 85 FB 86 FF 87 00 88 00 89 FF 8A 30 3F 08 28
 @00000150 02 22 0A 2A 15 35 1D 3D 17 37 1F 3F 30 03 08 28
 @00000160 02 22 0A 2A 15 35 1D 3D 17 37 1F 3F C9 C9 C5 C5
-@00000170 21 04 80 E5 CD 72 0C C1 21 60 81 E5 CD 72 0C C1
-@00000180 21 0E 82 E5 CD 72 0C C1 21 FF 85 E5 CD 72 0C C1
-@00000190 21 00 87 E5 CD 72 0C C1 21 00 88 E5 CD 72 0C C1
-@000001A0 21 00 89 E5 CD 72 0C C1 21 00 C0 E5 CD 72 0C C1
+@00000170 21 04 80 E5 CD 5A 0C C1 21 60 81 E5 CD 5A 0C C1
+@00000180 21 0E 82 E5 CD 5A 0C C1 21 FF 85 E5 CD 5A 0C C1
+@00000190 21 00 87 E5 CD 5A 0C C1 21 00 88 E5 CD 5A 0C C1
+@000001A0 21 00 89 E5 CD 5A 0C C1 21 00 C0 E5 CD 5A 0C C1
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 /* http://srecord.sourceforge.net/ */
 @00008400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 @00008410 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/cores/MasterSystem/bootloader/fat.c b/cores/MasterSystem/bootloader/fat.c
index 1754cb0..2350405 100644
--- a/cores/MasterSystem/bootloader/fat.c
+++ b/cores/MasterSystem/bootloader/fat.c
@@ -17,7 +17,6 @@ const fat_t *fat 					= 0xc010;
 const UBYTE *fat_buffer				= 0xc100;
 const UBYTE *data_buffer			= 0xc300;
 const file_descr_t *directory_buffer= 0xc500;
-//const BYTE *card_type 				= 0xc700; //q
 
 void fat_init32();
 void fat_init16();
@@ -50,16 +49,17 @@ int fat_init()
 		console_puts("Wrong MBR\n");
 		return FALSE;
 	}
-
 	switch (data_buffer[0x1c2]) {
 	case 0x06:
+	case 0x04:
 		fat->fat32 = FALSE;
 		break;
 	case 0x0b:
+	case 0x0c:	
 		fat->fat32 = TRUE;
 		break;
 	default:
-		console_puts("Unknown filesystem type (FAT16/32 only)\n");
+		console_puts("Unsupported FileSystem (FAT16/32 only)\n");
 		return FALSE;
 	}
 
@@ -70,6 +70,7 @@ int fat_init()
 	debug_puts("\n");
 #endif
 
+
 	if (!sd_load_sector(data_buffer, sector)) {
 		console_puts("Error while loading boot sector\n");
 		return FALSE;
diff --git a/cores/MasterSystem/bootloader/main.c b/cores/MasterSystem/bootloader/main.c
index 100dbe2..3fa56b9 100644
--- a/cores/MasterSystem/bootloader/main.c
+++ b/cores/MasterSystem/bootloader/main.c
@@ -59,16 +59,15 @@ void main()
 
 		i = 0;
 		if (!sd_init()) {
-			console_puts("Could not initialize SD card\n");
+			console_puts("Error initializing SD/MMC card\n");
 		} else {
-	#ifdef DEBUG
+	#ifdef DEBUG2
 			console_puts("SD card initialized\n");
 	#endif
 			if (!fat_init()) {
-				console_puts("could not initialize FAT system\n"); 
-	
+				//console_puts("could not initialize FAT system\n"); //qq
 			} else {
-	#ifdef DEBUG
+	#ifdef DEBUG2
 				console_puts("FAT system initialized\n");
 	#endif
 				i = 1;
@@ -86,8 +85,8 @@ void choose_mode(int sd_ok)
 	console_gotoxy(9,10);
 	if (sd_ok) {
 		pick_and_load_rom();
-	} else {	
-		console_puts("retry SD card");
+	} else {
+		console_puts("retry SD/MMC card");
 	}
 
 	for (;;) {
@@ -98,6 +97,9 @@ void choose_mode(int sd_ok)
 		if (i==1) { console_puts(">"); } else { console_puts("  "); }
 		key = wait_key();
 		switch (key) {
+		case JOY_UP:
+			i = 0;
+			break;
 		case JOY_FIREA:
 		case JOY_FIREB:
 			if (i==0) {
@@ -142,7 +144,7 @@ void pick_and_load_rom()
 				}
 			}
 		cont = 0;
-		}
+		}	
 		if ((key & JOY_DOWN) && (cont%cdiv==0)) {
 			if (current[1].type!=0) {
 				current++;
@@ -247,6 +249,9 @@ void load_rom(file_descr_t *entry)
 			size += 0x200;
 			if ((size)%16384 == 0)
 			   console_puts(".");
+			//console_gotoxy(0,3);
+			//console_print_dword(size);
+			//console_puts(" bytes loaded");
 		}
 	}
 }
@@ -256,6 +261,7 @@ void start_rom()
 	*((UBYTE*)0xfffd) = 0;
 	*((UBYTE*)0xfffe) = 1;
 	*((UBYTE*)0xffff) = 2;
+	//console_puts("booting rom...\n");
 	// any write to $00 when in bootloader mode sets normal mode and reboots the CPU
 	#asm
 	out ($00),a
diff --git a/cores/MasterSystem/bootloader/sd.c b/cores/MasterSystem/bootloader/sd.c
index b40d400..a26f912 100644
--- a/cores/MasterSystem/bootloader/sd.c
+++ b/cores/MasterSystem/bootloader/sd.c
@@ -79,7 +79,6 @@ UBYTE spi_receive_byte()
 }
 
 
-
 UBYTE sd_wait_r1()
 {
 	BYTE r,timeout;
@@ -139,6 +138,24 @@ UBYTE sd_cmd0()
 	return r;
 }
 
+UBYTE sd_cmd1() //MMC
+{
+	BYTE r;
+	spi_delay();
+	sd_wait_ready();
+
+	spi_send_byte(0x41);
+	spi_send_byte(0x00);
+	spi_send_byte(0x00);
+	spi_send_byte(0x00);
+	spi_send_byte(0x00);
+	spi_send_byte(0xFF);
+
+	r = sd_wait_r1();
+
+	return r;
+}
+
 UBYTE sd_cmd8()
 {
 	BYTE r;
@@ -178,6 +195,13 @@ UBYTE sd_acmd41(UBYTE byte0)
 	spi_send_byte(0xff);
 
 	r = sd_wait_r1();
+
+#ifdef DEBUG_CMD
+	console_gotoxy(0,2);
+	console_puts("A41R1 = "); //q debug
+	console_print_byte(r); //q debug
+#endif	
+	
 	if (r>1) {
 	#ifdef DEBUG_SD
 		debug_puts("cmd55 failed:");
@@ -198,6 +222,12 @@ UBYTE sd_acmd41(UBYTE byte0)
 
 	r = sd_wait_r1();
 
+#ifdef DEBUG_CMD
+console_gotoxy(12,2);
+console_puts("A41R2 = "); //q debug
+console_print_byte(r); //q debug
+#endif	
+
 	spi_delay();
 	spi_delay();
 
@@ -224,21 +254,26 @@ UBYTE sd_cmd58()
 
 	r = sd_wait_r1();
 
+#ifdef DEBUG_CMD
+	console_gotoxy(0,3);
+	console_puts("58R1 = "); //q debug
+	console_print_byte(r); //q debug
+#endif
+
 	r58 =  spi_receive_byte();
 
-	if (r58==0xc0) 		// Distingue entre SDHC y SD
+#ifdef DEBUG_CMD	
+	console_puts(" - 58R2 = "); //q debug
+	console_print_byte(r58); //q debug
+	console_puts("\n");
+#endif
+
+	if (r58==0xc0) //Q
 		card_SDHC(1);
 	else
 		card_SDHC(0);
 
-#ifdef DEBUG_SD
-	console_print_byte(r58); //q debug
-	console_puts(" - card_type = ")
-	console_print_byte(card_type[0]); //q debug
-	console_puts("\n")
-#endif	
-
-	spi_delay(); 
+	spi_delay(); // if &0xc0==0xc0 => SDHC
 	spi_delay();
 	spi_delay();
 	spi_delay();
@@ -295,6 +330,7 @@ int sd_init()
 			timeout = timeout-1;
 		}
 
+		// read OCR   //Q MOD for SDHC
 		if (sd_cmd58()!=0) {
 			spi_deassert_cs();
 			return FALSE;
@@ -316,12 +352,15 @@ int sd_init()
 				timeout = timeout-1;
 			}
 		} else {
-			// MM Card : fail
-#ifdef DEBUG_SD
-			debug_puts("MMC\n");
-#endif
-			spi_deassert_cs();
-			return FALSE;
+			// MMC Card : probamos inicializar con CMD1
+		timeout = 0xff;
+			while (sd_cmd1()!=0) {
+				if (timeout==0) {
+					spi_deassert_cs();
+					return FALSE;
+				} 
+			}
+
 		}
 	}
 
@@ -333,6 +372,12 @@ int sd_init()
 /* loads $200 bytes from spi */
 void load_data(UBYTE *target)
 {
+/*
+	int i;
+	for (i=0; i<0x200; i++) {
+		*target++ = spi_receive_byte();
+	}
+*/
 	#asm
 	ld	hl, 2
 	add	hl, sp
@@ -363,7 +408,7 @@ int sd_load_sector(UBYTE* target, DWORD sector)
 	BYTE r;
 	BYTE timeout;
 
-	address = sector<<9; //Q SD no HC = byte address
+	address = sector<<9; //SD no HD = byte address
 	if (card_type[0] == 1)
 		address = sector; //Q SDHC = block addres 
 
diff --git a/cores/MasterSystem/inyectar_bootloader_rgb.bat b/cores/MasterSystem/inyectar_bootloader_rgb.bat
new file mode 100644
index 0000000..bfd80de
--- /dev/null
+++ b/cores/MasterSystem/inyectar_bootloader_rgb.bat
@@ -0,0 +1 @@
+data2mem -bm src\sms_bd.bmm -bt sms_rgb.bit -bd all.mem -o b sms_rgb_final.bit
\ No newline at end of file
diff --git a/cores/MasterSystem/inyectar_bootloader_vga.bat b/cores/MasterSystem/inyectar_bootloader_vga.bat
new file mode 100644
index 0000000..bec5355
--- /dev/null
+++ b/cores/MasterSystem/inyectar_bootloader_vga.bat
@@ -0,0 +1 @@
+data2mem -bm src\sms_bd.bmm -bt sms_vga.bit -bd all.mem -o b sms_vga_final.bit
\ No newline at end of file
diff --git a/cores/MasterSystem/master_system.xise b/cores/MasterSystem/master_system.xise
index 9ee62de..a92743f 100644
--- a/cores/MasterSystem/master_system.xise
+++ b/cores/MasterSystem/master_system.xise
@@ -9,137 +9,125 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="t80/T80.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
-    <file xil_pn:name="t80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="t80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="t80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
-    <file xil_pn:name="t80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="src/psg_noise.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="src/psg_tone.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="src/psg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="src/dac.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="src/io.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="src/spi.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="src/bootloader_rom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="src/ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="src/vdp.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="src/vdp_background.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="src/vdp_sprites.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="src/vdp_sprite_shifter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="src/vdp_vram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/color_encoder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/yuv_table.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="src/vdp_cram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="src/vdp_main.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
-    <file xil_pn:name="t80/T80se.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/sms_tv.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/tv_video.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/vga_video.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/sms_vga.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="T80/T80se.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="src/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+    </file>
+    <file xil_pn:name="src/sms_rgb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="src/rgb_video.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+    </file>
+    <file xil_pn:name="src/sms_vga.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="src/vga_video.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="src/sms.bmm" xil_pn:type="FILE_BMM">
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/clk_wiz_v1_8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="src/sms_zxuno.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="src/uart_tx.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="src/sms_vga_zxuno.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="src/clocks.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
   </files>
 
@@ -152,9 +140,10 @@
     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -176,7 +165,7 @@
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -193,6 +182,7 @@
     <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -213,6 +203,7 @@
     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
@@ -235,7 +226,6 @@
     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -246,16 +236,16 @@
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sms_vga|Behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="src/sms_vga.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sms_vga" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sms_rgb|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="src/sms_rgb.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sms_rgb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -275,7 +265,9 @@
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Selected UCF File" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -286,6 +278,7 @@
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
@@ -323,7 +316,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="sms_vga" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="sms_rgb" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -339,17 +332,16 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="sms_vga_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="sms_vga_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="sms_vga_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="sms_vga_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="sms_rgb_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="sms_rgb_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="sms_rgb_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="sms_rgb_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
@@ -368,7 +360,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="sms_vga" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="sms_rgb" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -381,7 +373,6 @@
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -421,7 +412,7 @@
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target UCF File Name" xil_pn:value="papilio.ucf" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Target UCF File Name" xil_pn:value="src/sms_zxuno.ucf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
@@ -429,6 +420,7 @@
     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -483,7 +475,10 @@
   </properties>
 
   <bindings>
+    <binding xil_pn:location="/sms_rgb" xil_pn:name="src/sms.bmm"/>
     <binding xil_pn:location="/sms_vga" xil_pn:name="src/sms.bmm"/>
+    <binding xil_pn:location="/sms_rgb" xil_pn:name="src/sms_zxuno.ucf"/>
+    <binding xil_pn:location="/sms_vga" xil_pn:name="src/sms_zxuno.ucf"/>
   </bindings>
 
   <libraries/>
diff --git a/cores/MasterSystem/src/clocks.vhd b/cores/MasterSystem/src/clocks.vhd
new file mode 100644
index 0000000..e61b1ce
--- /dev/null
+++ b/cores/MasterSystem/src/clocks.vhd
@@ -0,0 +1,189 @@
+-- file: clk_wiz_v1_8.vhd
+-- 
+-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1    32.024      0.000      50.0      271.037    265.971
+-- CLK_OUT2    16.012      0.000      50.0      322.832    265.971
+-- CLK_OUT3     8.006      0.000      50.0      365.304    265.971
+-- CLK_OUT4    64.048      0.000      50.0      224.987    265.971
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary          50.000            0.010
+-- Generador relojes PLL para el in de 50Mhz del ZX-UNO
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity clock is
+port
+ (-- Clock in ports
+  clk_in           : in     std_logic;
+  -- Clock out ports
+  clk32          : out    std_logic;
+  clk16          : out    std_logic;
+  clk_cpu          : out    std_logic;
+  clk64  : out    std_logic
+ );
+end clock;
+
+architecture behavioral of clock is
+--  attribute CORE_GENERATION_INFO : string;
+--  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v1_8,clk_wiz_v1_8,{component_name=clk_wiz_v1_8,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  -- Unused status signals
+  signal locked_unused    : std_logic;
+
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : IBUFG
+  port map
+   (O => clkin1,
+    I => clk_in);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the PLL primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  pll_base_inst : PLL_BASE
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLK_FEEDBACK         => "CLKFBOUT",
+    COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+    DIVCLK_DIVIDE        => 2,
+    CLKFBOUT_MULT        => 41,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKOUT0_DIVIDE       => 128, --32 = 32Mhz, --128 = 8Mhz
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT1_DIVIDE       => 64,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT2_DIVIDE       => 35, --35 ~33Mhz Z80     --128 = 8mhz    --51 = 20mhz
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT3_DIVIDE       => 16,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKIN_PERIOD         => 20.0,
+    REF_JITTER           => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKOUT0             => clkout0,
+    CLKOUT1             => clkout1,
+    CLKOUT2             => clkout2,
+    CLKOUT3             => clkout3,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    LOCKED              => locked_unused,
+    RST                 => '0',
+    -- Input clock control
+    CLKFBIN             => clkfbout_buf,
+    CLKIN               => clkin1);
+
+  -- Output buffering
+  -------------------------------------
+  clkf_buf : BUFG
+  port map
+   (O => clkfbout_buf,
+    I => clkfbout);
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk32,
+    I   => clkout0);
+
+  clkout2_buf : BUFG
+  port map
+   (O   => clk16,
+    I   => clkout1);
+
+  clkout3_buf : BUFG
+  port map
+   (O   => clk_cpu,
+    I   => clkout2);
+
+  clkout4_buf : BUFG
+  port map
+   (O   => clk64,
+    I   => clkout3);
+
+end behavioral;
diff --git a/cores/MasterSystem/src/psg.vhd b/cores/MasterSystem/src/psg.vhd
index aaae1d6..15fda04 100644
--- a/cores/MasterSystem/src/psg.vhd
+++ b/cores/MasterSystem/src/psg.vhd
@@ -11,7 +11,7 @@ end entity;
 
 architecture rtl of psg is
 
-	signal clk_divide	: unsigned(5 downto 0) := "000000";
+	signal clk_divide	: unsigned(6 downto 0) := "0000000"; --unsigned(5 downto 0) := "000000";
 	signal clk32		: std_logic;
 	signal regn			: std_logic_vector(2 downto 0);
 	signal tone0		: std_logic_vector(9 downto 0):="0000100000";
@@ -82,8 +82,7 @@ begin
 		
 	inst_dac: dac
 	port map (
---		clk		=> clk,
-		clk		=> clk32,
+		clk		=> clk, --clk32
 		input		=> outputs,
 		output	=> output );
 
@@ -93,7 +92,7 @@ begin
 			clk_divide <= clk_divide+1;
 		end if;
 	end process;
-	clk32 <= std_logic(clk_divide(5));
+	clk32 <= std_logic(clk_divide(6)); --5
 
 	process (clk, WR_n)
 	begin
diff --git a/cores/MasterSystem/src/rgb_video.vhd b/cores/MasterSystem/src/rgb_video.vhd
new file mode 100644
index 0000000..1d56560
--- /dev/null
+++ b/cores/MasterSystem/src/rgb_video.vhd
@@ -0,0 +1,136 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:59:35 01/22/2012 
+-- Design Name: 
+-- Module Name:    vdp_timing - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity rgb_video is
+	port (
+		clk16:			in  std_logic;
+		clk8:				in	 std_logic;
+		x: 				out unsigned(8 downto 0);
+		y:					out unsigned(7 downto 0);
+		vblank:			out std_logic;
+		hblank:			out std_logic;
+		color:			in  std_logic_vector(5 downto 0);
+		hsync:			out std_logic;
+		vsync:			out std_logic;
+		red:				out std_logic_vector(1 downto 0);
+		green:			out std_logic_vector(1 downto 0);
+		blue:				out std_logic_vector(1 downto 0));
+end rgb_video;
+
+architecture Behavioral of rgb_video is
+
+	signal hcount:		unsigned (8 downto 0) := (others=>'0');
+	signal vcount:		unsigned (8 downto 0) := (others=>'0');
+	signal visible:	boolean;
+	
+	signal y9:			unsigned (8 downto 0);
+	
+	signal in_vbl:			std_logic;
+	signal screen_sync:	std_logic;
+	signal vbl_sync:		std_logic;
+
+	
+begin
+	
+	process (clk8)
+	begin
+		if rising_edge(clk8) then
+			if hcount=511 then
+				hcount <= (others => '0');
+				if vcount=311 then --PAL = 311 / NTSC = 261
+					vcount <= (others=>'0');
+				else
+					vcount <= vcount + 1;
+				end if;
+			else
+				hcount <= hcount + 1;
+			end if;
+		end if;
+	end process;
+	
+	visible		<= vcount>=35 and vcount<302 and hcount>=91 and hcount<509-38;
+											--PAL = 302, NTSC = 255
+	process (hcount)
+	begin
+		if hcount<38 then
+			screen_sync <= '0';
+		else
+			screen_sync <= '1';
+		end if;
+	end process;
+	
+	in_vbl <= '1' when vcount<9 else '0';
+	
+	x					<= hcount-151;
+	y9					<= vcount-70;  --PAL = -70 , NTSC = -40
+	y					<= y9(7 downto 0);
+	vblank			<= '1' when hcount=0 and vcount=0 else '0';
+	hblank			<= '1' when hcount=0 else '0';
+	
+	process (vcount,hcount)
+	begin
+		if vcount<3 or (vcount>=6 and vcount<9) then
+			-- _^^^^^_^^^^^ : low pulse = 2.35us
+			if hcount<19 or (hcount>=254 and hcount<254+19) then
+				vbl_sync <= '0';
+			else
+				vbl_sync <= '1';
+			end if;
+		else
+			-- ____^^ : high pulse = 4.7us
+			if hcount<(254-38) or (hcount>=254 and hcount<509-38) then
+				vbl_sync <= '0';
+			else
+				vbl_sync <= '1';
+			end if;
+		end if;
+	end process;
+	
+	process (in_vbl,screen_sync,vbl_sync)
+	begin
+		if in_vbl='1' then
+			hsync <= vbl_sync;
+		else
+			hsync <= screen_sync;
+		end if;
+	end process;
+
+vsync <= '1';
+	
+	process (clk16)
+	begin
+		if rising_edge(clk16) then
+			if visible then
+				red	<= color(1 downto 0);
+				green	<= color(3 downto 2);
+				blue	<= color(5 downto 4);
+			else
+				red	<= (others=>'0');
+				green	<= (others=>'0');
+				blue	<= (others=>'0');
+			end if;
+		end if;
+	end process;
+
+end Behavioral;
+
diff --git a/cores/MasterSystem/src/sms_bd.bmm b/cores/MasterSystem/src/sms_bd.bmm
index 154a255..936cb8b 100644
--- a/cores/MasterSystem/src/sms_bd.bmm
+++ b/cores/MasterSystem/src/sms_bd.bmm
@@ -1,6 +1,6 @@
 // BMM LOC annotation file.
 //
-// Release 12.4 - Data2MEM M.81d, build 1.9 Aug 19, 2010
+// Release 14.6 -  P.20131013, build 3.0.10 Apr 3, 2013
 // Copyright (c) 1995-2015 Xilinx, Inc.  All rights reserved.
 
 
@@ -12,7 +12,6 @@
 
 ADDRESS_MAP bootrom PPC405 0
 
-
     ///////////////////////////////////////////////////////////////////////////////
     //
     // Processor 'bootrom' address space 'boot_code' 0x00000000:0x00003FFF (16 KBytes).
@@ -21,14 +20,14 @@ ADDRESS_MAP bootrom PPC405 0
 
     ADDRESS_SPACE boot_code RAMB16 [0x00000000:0x00003FFF]
         BUS_BLOCK
-            system_inst/boot_rom_inst/ram_blocks[7].inst [7:7] PLACED = X1Y30;
-            system_inst/boot_rom_inst/ram_blocks[6].inst [6:6] PLACED = X1Y26;
-            system_inst/boot_rom_inst/ram_blocks[5].inst [5:5] PLACED = X1Y24;
-            system_inst/boot_rom_inst/ram_blocks[4].inst [4:4] PLACED = X1Y16;
-            system_inst/boot_rom_inst/ram_blocks[3].inst [3:3] PLACED = X1Y12;
-            system_inst/boot_rom_inst/ram_blocks[2].inst [2:2] PLACED = X1Y14;
-            system_inst/boot_rom_inst/ram_blocks[1].inst [1:1] PLACED = X1Y10;
-            system_inst/boot_rom_inst/ram_blocks[0].inst [0:0] PLACED = X0Y28;
+            system_inst/boot_rom_inst/ram_blocks[7].inst RAMB16 [7:7] [0:16383] PLACED = X1Y4;
+            system_inst/boot_rom_inst/ram_blocks[6].inst RAMB16 [6:6] [0:16383] PLACED = X1Y6;
+            system_inst/boot_rom_inst/ram_blocks[5].inst RAMB16 [5:5] [0:16383] PLACED = X1Y10;
+            system_inst/boot_rom_inst/ram_blocks[4].inst RAMB16 [4:4] [0:16383] PLACED = X1Y8;
+            system_inst/boot_rom_inst/ram_blocks[3].inst RAMB16 [3:3] [0:16383] PLACED = X1Y12;
+            system_inst/boot_rom_inst/ram_blocks[2].inst RAMB16 [2:2] [0:16383] PLACED = X1Y24;
+            system_inst/boot_rom_inst/ram_blocks[1].inst RAMB16 [1:1] [0:16383] PLACED = X1Y22;
+            system_inst/boot_rom_inst/ram_blocks[0].inst RAMB16 [0:0] [0:16383] PLACED = X1Y26;
         END_BUS_BLOCK;
     END_ADDRESS_SPACE;
 
@@ -41,14 +40,14 @@ ADDRESS_MAP bootrom PPC405 0
 
     ADDRESS_SPACE vram_code RAMB16 [0x00008000:0x0000BFFF]
         BUS_BLOCK
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[7].inst [7:7] PLACED = X0Y16;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[6].inst [6:6] PLACED = X0Y24;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[5].inst [5:5] PLACED = X0Y26;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[4].inst [4:4] PLACED = X0Y22;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[3].inst [3:3] PLACED = X0Y14;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[2].inst [2:2] PLACED = X0Y12;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[1].inst [1:1] PLACED = X0Y18;
-            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[0].inst [0:0] PLACED = X0Y20;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[7].inst RAMB16 [7:7] [0:16383] PLACED = X0Y10;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[6].inst RAMB16 [6:6] [0:16383] PLACED = X0Y12;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[5].inst RAMB16 [5:5] [0:16383] PLACED = X0Y14;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[4].inst RAMB16 [4:4] [0:16383] PLACED = X0Y24;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[3].inst RAMB16 [3:3] [0:16383] PLACED = X0Y22;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[2].inst RAMB16 [2:2] [0:16383] PLACED = X0Y20;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[1].inst RAMB16 [1:1] [0:16383] PLACED = X0Y18;
+            system_inst/vdp_inst/vdp_vram_inst/ram_blocks[0].inst RAMB16 [0:0] [0:16383] PLACED = X0Y16;
         END_BUS_BLOCK;
     END_ADDRESS_SPACE;
 
diff --git a/cores/MasterSystem/src/sms_rgb.vhd b/cores/MasterSystem/src/sms_rgb.vhd
new file mode 100644
index 0000000..b7a0a7a
--- /dev/null
+++ b/cores/MasterSystem/src/sms_rgb.vhd
@@ -0,0 +1,196 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity sms_rgb is
+	port (
+		clk:			in		STD_LOGIC;
+		
+		ram_we_n:	out	STD_LOGIC;
+		ram_a:		out	STD_LOGIC_VECTOR(18 downto 0);
+		ram_d:		inout	STD_LOGIC_VECTOR(7 downto 0); --Q
+
+--		j1_MDsel:	out	STD_LOGIC; --Q
+		j1_up:		in		STD_LOGIC;
+		j1_down:		in		STD_LOGIC;
+		j1_left:		in		STD_LOGIC;
+		j1_right:	in		STD_LOGIC;
+		j1_tl:		in		STD_LOGIC;
+		j1_tr:		inout	STD_LOGIC;
+
+		audio_l:		out	STD_LOGIC;
+		audio_r:		out	STD_LOGIC;
+		
+		red:			out	STD_LOGIC_VECTOR(2 downto 0); --Q
+		green:		out	STD_LOGIC_VECTOR(2 downto 0); --Q
+		blue:			out	STD_LOGIC_VECTOR(2 downto 0); --Q
+		hsync:		out	STD_LOGIC;
+		vsync:		out	STD_LOGIC;
+
+		spi_do:		in		STD_LOGIC;
+		spi_sclk:	out	STD_LOGIC;
+		spi_di:		out	STD_LOGIC;
+		spi_cs_n:	buffer	STD_LOGIC; --Q
+
+		led:			out	STD_LOGIC; --Q
+		
+      NTSC              : out   std_logic; --Q
+      PAL               : out   std_logic --Q		
+		);
+end sms_rgb;
+
+architecture Behavioral of sms_rgb is
+
+	component clock is
+   port (
+		clk_in:		in  std_logic;
+		clk_cpu:		out std_logic;
+		clk16:		out std_logic;
+		clk32:		out std_logic;
+		clk64:		out std_logic);
+	end component;
+
+	component system is
+	port (
+		clk_cpu:		in		STD_LOGIC;
+		clk_vdp:		in		STD_LOGIC;
+		
+		ram_we_n:	out	STD_LOGIC;
+		ram_a:		out	STD_LOGIC_VECTOR(18 downto 0);
+		ram_d:		inout	STD_LOGIC_VECTOR(7 downto 0);
+
+		j1_up:		in		STD_LOGIC;
+		j1_down:		in		STD_LOGIC;
+		j1_left:		in		STD_LOGIC;
+		j1_right:	in		STD_LOGIC;
+		j1_tl:		in		STD_LOGIC;
+		j1_tr:		inout	STD_LOGIC;
+		j2_up:		in		STD_LOGIC;
+		j2_down:		in		STD_LOGIC;
+		j2_left:		in		STD_LOGIC;
+		j2_right:	in		STD_LOGIC;
+		j2_tl:		in		STD_LOGIC;
+		j2_tr:		inout	STD_LOGIC;
+		reset:		in		STD_LOGIC;
+		pause:		in		STD_LOGIC;
+
+		x:				in		UNSIGNED(8 downto 0);
+		y:				in		UNSIGNED(7 downto 0);
+		vblank:		in		STD_LOGIC;
+		hblank:		in		STD_LOGIC;
+		color:		out	STD_LOGIC_VECTOR(5 downto 0);
+		audio:		out	STD_LOGIC;
+
+		spi_do:		in		STD_LOGIC;
+		spi_sclk:	out	STD_LOGIC;
+		spi_di:		out	STD_LOGIC;
+		spi_cs_n:	out	STD_LOGIC
+);
+	end component;
+	
+	component rgb_video is
+	port (
+		clk16:			in  std_logic;
+		clk8:				in  std_logic; --Q
+		x: 				out unsigned(8 downto 0);
+		y:					out unsigned(7 downto 0);
+		vblank:			out std_logic;
+		hblank:			out std_logic;
+		color:			in  std_logic_vector(5 downto 0);
+		hsync:			out std_logic;
+		vsync:			out std_logic;
+		red:				out std_logic_vector(1 downto 0);
+		green:			out std_logic_vector(1 downto 0);
+		blue:				out std_logic_vector(1 downto 0)
+);
+	end component;
+	
+	signal clk_cpu:			std_logic;
+	signal clk16:				std_logic;
+	signal clk8:				std_logic;
+	
+	signal x:					unsigned(8 downto 0);
+	signal y:					unsigned(7 downto 0);
+	signal vblank:				std_logic;
+	signal hblank:				std_logic;
+	signal color:				std_logic_vector(5 downto 0);
+	signal audio:				std_logic;
+	
+	signal j2_tr:				std_logic;
+	
+begin
+
+	clock_inst: clock
+	port map (
+		clk_in		=> clk,
+		clk_cpu		=> clk_cpu,
+		clk16			=> clk16,
+		clk32			=> clk8, --clk32 => open
+		clk64			=> open);
+		
+	video_inst: rgb_video
+	port map (
+		clk16			=> clk16, 
+		clk8			=> clk8, --Q
+		x	 			=> x,
+		y				=> y,
+		vblank		=> vblank,
+		hblank		=> hblank,
+		color			=> color,		
+		hsync			=> hsync,
+		vsync			=> vsync,
+		red			=> red(2 downto 1), --Q
+		green			=> green(2 downto 1), --Q
+		blue			=> blue(2 downto 1) --Q
+	);
+	
+	red(0) <= '0'; --Q
+	green(0) <= '0'; --Q
+	blue(0) <= '0'; --Q
+
+	system_inst: system
+	port map (
+		clk_cpu		=> clk_cpu, --clk_cpu
+		clk_vdp		=> clk8,	--clk16
+		
+		ram_we_n		=> ram_we_n,
+		ram_a			=> ram_a,
+		ram_d			=> ram_d,
+
+		j1_up			=> j1_up,
+		j1_down		=> j1_down,
+		j1_left		=> j1_left,
+		j1_right		=> j1_right,
+		j1_tl			=> j1_tl,
+		j1_tr			=> j1_tr,
+		j2_up			=> '1',
+		j2_down		=> '1',
+		j2_left		=> '1',
+		j2_right		=> '1',
+		j2_tl			=> '1',
+		j2_tr			=> j2_tr,
+		reset			=> '1',
+		pause			=> '1',
+
+		x				=> x,
+		y				=> y,
+		vblank		=> vblank,
+		hblank		=> hblank,
+		color			=> color,
+		audio			=> audio,
+
+		spi_do		=> spi_do,
+		spi_sclk		=> spi_sclk,
+		spi_di		=> spi_di,
+		spi_cs_n		=> spi_cs_n
+		);
+	
+	led <= not spi_cs_n; --Q
+
+	audio_l <= audio;
+	audio_r <= audio;
+	
+	NTSC <= '0';
+	PAL <= '1';	
+	
+end Behavioral;
diff --git a/cores/MasterSystem/src/sms_vga.vhd b/cores/MasterSystem/src/sms_vga.vhd
index b99acce..8f9d9f2 100644
--- a/cores/MasterSystem/src/sms_vga.vhd
+++ b/cores/MasterSystem/src/sms_vga.vhd
@@ -10,7 +10,7 @@ entity sms_vga is
 		ram_a:		out	STD_LOGIC_VECTOR(18 downto 0);
 		ram_d:		inout	STD_LOGIC_VECTOR(7 downto 0); --Q
 
-		j1_MDsel:	out	STD_LOGIC; --Q
+--		j1_MDsel:	out	STD_LOGIC; --Q
 		j1_up:		in		STD_LOGIC;
 		j1_down:		in		STD_LOGIC;
 		j1_left:		in		STD_LOGIC;
@@ -32,8 +32,10 @@ entity sms_vga is
 		spi_di:		out	STD_LOGIC;
 		spi_cs_n:	buffer	STD_LOGIC; --Q
 
-		tx:			out	STD_LOGIC;
-		led:			out	STD_LOGIC --Q
+		led:			out	STD_LOGIC; --Q
+		
+      NTSC              : out   std_logic; --Q
+      PAL               : out   std_logic --Q		
 		);
 end sms_vga;
 
@@ -82,26 +84,24 @@ architecture Behavioral of sms_vga is
 		spi_do:		in		STD_LOGIC;
 		spi_sclk:	out	STD_LOGIC;
 		spi_di:		out	STD_LOGIC;
-		spi_cs_n:	out	STD_LOGIC ;
-
-		tx:			out	STD_LOGIC
+		spi_cs_n:	out	STD_LOGIC
 );
 	end component;
 	
 	component vga_video is
 	port (
 		clk16:			in  std_logic;
-		dither:			in  std_logic;
 		x: 				out unsigned(8 downto 0);
-		y:					out unsigned(7 downto 0);
+		y:				out unsigned(7 downto 0);
 		vblank:			out std_logic;
 		hblank:			out std_logic;
 		color:			in  std_logic_vector(5 downto 0);
 		hsync:			out std_logic;
 		vsync:			out std_logic;
-		red:				out std_logic_vector(1 downto 0);
+		red:			out std_logic_vector(1 downto 0);
 		green:			out std_logic_vector(1 downto 0);
-		blue:				out std_logic_vector(1 downto 0));
+		blue:			out std_logic_vector(1 downto 0)
+);
 	end component;
 	
 	signal clk_cpu:			std_logic;
@@ -120,25 +120,23 @@ begin
 
 	clock_inst: clock
 	port map (
-		clk_in		=> clk,
-		clk_cpu		=> clk_cpu,
+		clk_in			=> clk,
+		clk_cpu			=> clk_cpu,
 		clk16			=> clk16,
-		clk32			=> open,
+		clk32			=> open, 
 		clk64			=> open);
 		
 	video_inst: vga_video
 	port map (
 		clk16			=> clk16, 
-		dither		=> '0', --1
 		x	 			=> x,
 		y				=> y,
-		vblank		=> vblank,
-		hblank		=> hblank,
-		color			=> color,
-		
+		vblank			=> vblank,
+		hblank			=> hblank,
+		color			=> color,		
 		hsync			=> hsync,
 		vsync			=> vsync,
-		red			=> red(2 downto 1), --Q
+		red				=> red(2 downto 1), --Q
 		green			=> green(2 downto 1), --Q
 		blue			=> blue(2 downto 1) --Q
 	);
@@ -149,22 +147,22 @@ begin
 
 	system_inst: system
 	port map (
-		clk_cpu		=> clk_cpu,
-		clk_vdp		=> clk16,
+		clk_cpu		=> clk_cpu, --clk_cpu
+		clk_vdp		=> clk16,	--clk16
 		
 		ram_we_n		=> ram_we_n,
 		ram_a			=> ram_a,
 		ram_d			=> ram_d,
 
 		j1_up			=> j1_up,
-		j1_down		=> j1_down,
-		j1_left		=> j1_left,
+		j1_down			=> j1_down,
+		j1_left			=> j1_left,
 		j1_right		=> j1_right,
 		j1_tl			=> j1_tl,
 		j1_tr			=> j1_tr,
 		j2_up			=> '1',
-		j2_down		=> '1',
-		j2_left		=> '1',
+		j2_down			=> '1',
+		j2_left			=> '1',
 		j2_right		=> '1',
 		j2_tl			=> '1',
 		j2_tr			=> j2_tr,
@@ -173,25 +171,23 @@ begin
 
 		x				=> x,
 		y				=> y,
-		vblank		=> vblank,
-		hblank		=> hblank,
+		vblank			=> vblank,
+		hblank			=> hblank,
 		color			=> color,
 		audio			=> audio,
 
-		spi_do		=> spi_do,
+		spi_do			=> spi_do,
 		spi_sclk		=> spi_sclk,
-		spi_di		=> spi_di,
-		spi_cs_n		=> spi_cs_n,
-
-		tx				=> tx
+		spi_di			=> spi_di,
+		spi_cs_n		=> spi_cs_n
 		);
 	
-	j1_MDsel <= '1'; --Q
-	
 	led <= not spi_cs_n; --Q
 
 	audio_l <= audio;
 	audio_r <= audio;
 	
+	NTSC <= '0';
+	PAL <= '0';	
+	
 end Behavioral;
-
diff --git a/cores/MasterSystem/src/sms_zxuno.ucf b/cores/MasterSystem/src/sms_zxuno.ucf
new file mode 100644
index 0000000..29eb396
--- /dev/null
+++ b/cores/MasterSystem/src/sms_zxuno.ucf
@@ -0,0 +1,69 @@
+#UCF para el ZX-UNO
+
+NET CLK      LOC="P55"  | IOSTANDARD=LVCMOS33 ;               # CLK
+
+NET "led"			LOC="P10" | IOSTANDARD=LVCMOS33;
+
+NET "j1_tr"			LOC="P143"  | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_tl"			LOC="P6"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_right"		LOC="P5"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_left"		LOC="P2"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_down"		LOC="P1"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_up"			LOC="P142"  | IOSTANDARD=LVCMOS33 | PULLUP;
+
+NET "vsync"			LOC="P85"  | IOSTANDARD=LVCMOS33;                                
+NET "hsync"			LOC="P87"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(0)"		LOC="P82"  | IOSTANDARD=LVCMOS33;                                
+NET "red(0)"		LOC="P88"  | IOSTANDARD=LVCMOS33;                               
+NET "blue(0)"		LOC="P79"  | IOSTANDARD=LVCMOS33;                               
+
+NET "green(1)"		LOC="P83"  | IOSTANDARD=LVCMOS33;                                
+NET "red(1)"		LOC="P92"  | IOSTANDARD=LVCMOS33;                                
+NET "blue(1)"		LOC="P80"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(2)"		LOC="P84"  | IOSTANDARD=LVCMOS33;                               
+NET "red(2)"		LOC="P93"  | IOSTANDARD=LVCMOS33;                              
+NET "blue(2)"		LOC="P81"  | IOSTANDARD=LVCMOS33;                                
+                               
+NET "spi_do"		LOC="P78"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B1
+NET "spi_sclk"		LOC="P75"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B2
+NET "spi_di"		LOC="P74"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B3
+NET "spi_cs_n"		LOC="P59"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B4
+
+NET "audio_l"		LOC="P8"   | IOSTANDARD=LVCMOS33;                               
+NET "audio_r"		LOC="P9"   | IOSTANDARD=LVCMOS33;                               
+
+NET ram_a(0)  LOC="P115"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR0
+NET ram_a(1)  LOC="P116"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR1
+NET ram_a(2)  LOC="P117"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR2
+NET ram_a(3)  LOC="P119"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR3
+NET ram_a(4)  LOC="P120"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR4
+NET ram_a(5)  LOC="P123"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR5
+NET ram_a(6)  LOC="P126"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR6
+NET ram_a(7)  LOC="P131"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR7
+NET ram_a(8)  LOC="P127"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR8
+NET ram_a(9)  LOC="P124"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR9
+NET ram_a(10) LOC="P118"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR10
+NET ram_a(11) LOC="P121"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR11
+NET ram_a(12) LOC="P133"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR12
+NET ram_a(13) LOC="P132"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR13
+NET ram_a(14) LOC="P137"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR14
+NET ram_a(15) LOC="P140"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR15
+NET ram_a(16) LOC="P139"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR16
+NET ram_a(17) LOC="P141"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR17
+NET ram_a(18) LOC="P138"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR18
+
+NET ram_d(0)  LOC="P114"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA0
+NET ram_d(1)  LOC="P112"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA1
+NET ram_d(2)  LOC="P111"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA2
+NET ram_d(3)  LOC="P99"    | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA3
+NET ram_d(4)  LOC="P100"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA4
+NET ram_d(5)  LOC="P101"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA5
+NET ram_d(6)  LOC="P102"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA6
+NET ram_d(7)  LOC="P104"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA7
+
+NET ram_WE_n  LOC="P134" | IOSTANDARD=LVCMOS33 | SLEW=FAST;                    # nWE
+
+NET NTSC            LOC = "P67" | IOSTANDARD = LVCMOS33;
+NET PAL             LOC = "P66" | IOSTANDARD = LVCMOS33;
\ No newline at end of file
diff --git a/cores/MasterSystem/src/sms_zxuno_v3.ucf b/cores/MasterSystem/src/sms_zxuno_v3.ucf
new file mode 100644
index 0000000..6389d58
--- /dev/null
+++ b/cores/MasterSystem/src/sms_zxuno_v3.ucf
@@ -0,0 +1,69 @@
+#UCF para el ZX-UNO
+
+NET CLK      LOC="P55"  | IOSTANDARD=LVCMOS33 ;               # CLK
+
+NET "led"			LOC="P10" | IOSTANDARD=LVCMOS33;
+
+NET "j1_tr"			LOC="P39"  | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_tl"			LOC="P2"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_right"		LOC="P7"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_left"		LOC="P6"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_down"		LOC="P5"  	| IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_up"			LOC="P1"  | IOSTANDARD=LVCMOS33 | PULLUP;
+
+NET "vsync"			LOC="P85"  | IOSTANDARD=LVCMOS33;                                
+NET "hsync"			LOC="P87"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(0)"		LOC="P82"  | IOSTANDARD=LVCMOS33;                                
+NET "red(0)"		LOC="P88"  | IOSTANDARD=LVCMOS33;                               
+NET "blue(0)"		LOC="P79"  | IOSTANDARD=LVCMOS33;                               
+
+NET "green(1)"		LOC="P83"  | IOSTANDARD=LVCMOS33;                                
+NET "red(1)"		LOC="P92"  | IOSTANDARD=LVCMOS33;                                
+NET "blue(1)"		LOC="P80"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(2)"		LOC="P84"  | IOSTANDARD=LVCMOS33;                               
+NET "red(2)"		LOC="P93"  | IOSTANDARD=LVCMOS33;                              
+NET "blue(2)"		LOC="P81"  | IOSTANDARD=LVCMOS33;                                
+                               
+NET "spi_do"		LOC="P78"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B1
+NET "spi_sclk"		LOC="P75"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B2
+NET "spi_di"		LOC="P74"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B3
+NET "spi_cs_n"		LOC="P59"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;                                # B4
+
+NET "audio_l"		LOC="P8"   | IOSTANDARD=LVCMOS33;                               
+NET "audio_r"		LOC="P9"   | IOSTANDARD=LVCMOS33;                               
+
+NET ram_a(0)  LOC="P143"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR0
+NET ram_a(1)  LOC="P142"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR1
+NET ram_a(2)  LOC="P141"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR2
+NET ram_a(3)  LOC="P140"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR3
+NET ram_a(4)  LOC="P139"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR4
+NET ram_a(5)  LOC="P104"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR5
+NET ram_a(6)  LOC="P102"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR6
+NET ram_a(7)  LOC="P101"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR7
+NET ram_a(8)  LOC="P100"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR8
+NET ram_a(9)  LOC="P99"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR9
+NET ram_a(10) LOC="P112"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR10
+NET ram_a(11) LOC="P114"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR11
+NET ram_a(12) LOC="P115"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR12
+NET ram_a(13) LOC="P116"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR13
+NET ram_a(14) LOC="P117"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR14
+NET ram_a(15) LOC="P131"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR15
+NET ram_a(16) LOC="P133"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR16
+NET ram_a(17) LOC="P134"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR17
+NET ram_a(18) LOC="P137"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR18
+
+NET ram_d(0)  LOC="P132"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA0
+NET ram_d(1)  LOC="P126"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA1
+NET ram_d(2)  LOC="P123"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA2
+NET ram_d(3)  LOC="P120"    | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA3
+NET ram_d(4)  LOC="P119"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA4
+NET ram_d(5)  LOC="P121"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA5
+NET ram_d(6)  LOC="P124"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA6
+NET ram_d(7)  LOC="P127"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA7
+
+NET ram_WE_n  LOC="P118" | IOSTANDARD=LVCMOS33 | SLEW=FAST;                    # nWE
+
+NET NTSC            LOC = "P67" | IOSTANDARD = LVCMOS33;
+NET PAL             LOC = "P66" | IOSTANDARD = LVCMOS33;
\ No newline at end of file
diff --git a/cores/MasterSystem/src/system.vhd b/cores/MasterSystem/src/system.vhd
index 9bd9910..0374dfc 100644
--- a/cores/MasterSystem/src/system.vhd
+++ b/cores/MasterSystem/src/system.vhd
@@ -38,14 +38,12 @@ entity system is
 		spi_do:		in		STD_LOGIC;
 		spi_sclk:	out	STD_LOGIC;
 		spi_di:		out	STD_LOGIC;
-		spi_cs_n:	out	STD_LOGIC;
-		
-		tx:			out	STD_LOGIC);
+		spi_cs_n:	out	STD_LOGIC
+	);
 end system;
 
 architecture Behavioral of system is
 	
---	component dummy_z80 is
 	component T80se is
 	generic(
 		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
@@ -143,7 +141,6 @@ architecture Behavioral of system is
 		A:					in  STD_LOGIC_VECTOR(13 downto 0);
 		D_out:			out STD_LOGIC_VECTOR(7 downto 0));
 	end component;
-
 	
 	component spi is
 	port (
@@ -160,15 +157,6 @@ architecture Behavioral of system is
 		mosi:				out STD_LOGIC);
 	end component;
 
-	component uart_tx is
-	port (
-		clk:  			in  std_logic;
-		WR_n:				in  std_logic;
-		D_in: 			in  std_logic_vector(7 downto 0);
-		serial_out:		out std_logic;
-		ready:			out std_logic);
-	end component;
-	
 	signal RESET_n:			std_logic;
 	signal RD_n:				std_logic;
 	signal WR_n:				std_logic;
@@ -190,11 +178,9 @@ architecture Behavioral of system is
 	signal io_WR_n:			std_logic;
 	signal io_D_out:			std_logic_vector(7 downto 0);
 	
---	signal ram_RD_n:			std_logic;
 	signal ram_WR_n:			std_logic;
 	signal ram_D_out:			std_logic_vector(7 downto 0);
 	
---	signal rom_RD_n:			std_logic;
 	signal rom_WR_n:			std_logic;
 	signal rom_D_out:			std_logic_vector(7 downto 0);
 	
@@ -202,12 +188,8 @@ architecture Behavioral of system is
 	signal spi_WR_n:			std_logic;
 	signal spi_D_out:			std_logic_vector(7 downto 0);
 	
---	signal boot_rom_RD_n:	std_logic;
 	signal boot_rom_D_out:	std_logic_vector(7 downto 0);
 	
-	signal uart_WR_n:			std_logic;
-	signal uart_D_out:		std_logic_vector(7 downto 0);
-
 	signal reset_counter:	unsigned(3 downto 0) := "1111";
 	signal bootloader:		std_logic := '0';
 	signal irom_D_out:		std_logic_vector(7 downto 0);
@@ -218,7 +200,6 @@ architecture Behavioral of system is
 	signal bank2:				std_logic_vector(4 downto 0); --Q
 begin	
 	
---	z80_inst: dummy_z80
 	z80_inst: T80se
 	port map(
 
@@ -307,7 +288,6 @@ begin
 		A				=> A(13 downto 0),
 		D_out			=> boot_rom_D_out);
 	
---	spi_inst: dummy_spi
 	spi_inst: spi
 	port map (
 		clk			=> clk_cpu,
@@ -321,20 +301,6 @@ begin
 		sclk			=> spi_sclk,
 		miso			=> spi_do,
 		mosi			=> spi_di);
-
-	uart_tx_inst: uart_tx
-	port map (
-		clk			=> clk_cpu,
-		WR_n			=> uart_WR_n,
-		D_in			=> D_in,
-		serial_out	=> tx,
-		ready			=> uart_D_out(0));
-	
-	uart_D_out(7 downto 1) <= (others=>'0');
-	
-	
-	
-	
 	
 	-- glue logic
 
@@ -354,8 +320,6 @@ begin
 
 	spi_WR_n <= bootloader or WR_n when io_n='0' and A(7 downto 5)="110" else '1';
 
-	uart_WR_n<= bootloader or WR_n when io_n='0' and A(7 downto 5)="111" else '1';
-	
 	ram_WR_n <= WR_n when io_n='1' and A(15 downto 14)="11" else '1';
 	
 	rom_WR_n <= bootloader or WR_n when io_n='1' and A(15 downto 14)="10" else '1';
@@ -378,14 +342,14 @@ begin
 	
 	irom_D_out <=	boot_rom_D_out when bootloader='0' and A(15 downto 14)="00" else rom_D_out;
 	
-	process (io_n,A,spi_D_out,uart_D_out,vdp_D_out,vdp_D_out,io_D_out,irom_D_out,irom_D_out,irom_D_out,ram_D_out)
+	process (io_n,A,spi_D_out,vdp_D_out,vdp_D_out,io_D_out,irom_D_out,irom_D_out,irom_D_out,ram_D_out)
 	begin
 		if io_n='0' then
 			case A(7 downto 5) is
 			when "000" =>
 				D_out <= spi_D_out; 
 			when "001" =>
-				D_out <= uart_D_out;
+				D_out <= "00000000";
 			when "110"|"111" =>
 				D_out <= io_D_out;
 			when others =>
@@ -400,7 +364,6 @@ begin
 		end if;
 	end process;
 				
-				
 	-- external ram control
 	
 	process (clk_cpu)
@@ -443,4 +406,3 @@ begin
 	rom_D_out<= ram_d(7 downto 0); --Q
 
 end Behavioral;
-
diff --git a/cores/MasterSystem/src/vga_video.vhd b/cores/MasterSystem/src/vga_video.vhd
index 38a9e08..82ae168 100644
--- a/cores/MasterSystem/src/vga_video.vhd
+++ b/cores/MasterSystem/src/vga_video.vhd
@@ -24,7 +24,6 @@ use IEEE.NUMERIC_STD.ALL;
 entity vga_video is
 	port (
 		clk16:			in  std_logic;
-		dither:			in  std_logic;
 		x: 				out unsigned(8 downto 0);
 		y:					out unsigned(7 downto 0);
 		vblank:			out std_logic;
@@ -44,7 +43,6 @@ architecture Behavioral of vga_video is
 	signal visible:	boolean;
 	
 	signal y9:			unsigned (8 downto 0);
-	signal screen_n:	std_logic_vector (1 downto 0) := (others=>'0');
 	
 begin
 	
@@ -64,7 +62,7 @@ begin
 		end if;
 	end process;
 	
-	x				<= hcount-(91+75);
+	x				<= hcount-(91+62);
 	y9				<= vcount(9 downto 1)-(13+27);
 	y				<= y9(7 downto 0);
 	hblank		<= '1' when hcount=0 and vcount(0 downto 0)=0 else '0';
@@ -76,52 +74,14 @@ begin
 	visible		<= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406;
 	
 	process (clk16)
-	begin
-		if rising_edge(clk16) then
-			if vcount=0 and hcount=0 then
-				case screen_n is
-				when "00"	=> screen_n <= "01";
-				when "01"	=> screen_n <= "11";
-				when "11"	=> screen_n <= "10";
-				when others	=> screen_n <= "00";
-				end case;
-			end if;
-		end if;
-	end process;
-	
-	process (clk16)
-		variable pixel_n: std_logic_vector(1 downto 0);
 	begin
 		if rising_edge(clk16) then
 			if visible then
-				if dither='1' then
-					pixel_n := std_logic_vector(hcount(0 downto 0))&std_logic_vector(vcount(0 downto 0));
-					pixel_n(0) := pixel_n(0) xor screen_n(0);
-					pixel_n(1) := pixel_n(1) xor screen_n(1);
-					case pixel_n is
-					when "00" =>
-						red(1)	<= color(0);
-						green(1)	<= color(2);
-						blue(1)	<= color(4);
-					when "01" | "10" =>
-						red(1)	<= color(1);
-						green(1)	<= color(3);
-						blue(1)	<= color(5);
-					when others =>
-						red(1)	<= color(0) and color(1);
-						green(1)	<= color(2) and color(3);
-						blue(1)	<= color(4) and color(5);
-					end case;
-					red(0)	<= '0';
-					green(0)	<= '0';
-					blue(0)	<= '0';
-				else
-					red	<= color(1 downto 0);
+					red		<= color(1 downto 0);
 					green	<= color(3 downto 2);
 					blue	<= color(5 downto 4);
-				end if;
 			else
-				red	<= (others=>'0');
+				red		<= (others=>'0');
 				green	<= (others=>'0');
 				blue	<= (others=>'0');
 			end if;
@@ -129,4 +89,3 @@ begin
 	end process;
 
 end Behavioral;
-