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Fixed vga & sound via the buzzer. A & D output on leds

This commit is contained in:
byrtolet 2018-08-29 19:48:40 +03:00
parent 00515cd931
commit 64673306fa
6 changed files with 530 additions and 445 deletions
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4
cores/Oric/build/Makefile
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@ -1,5 +1,5 @@
all: all:
./makemy.sh time -p ./makemy.sh |tee out
clean: clean:
rm -rf COREn.ZX1 _impact.cmd _impact.log makemy.sh~ _ngo oric.bgn oric.bit oric_bitgen.xwbt \ rm -rf COREn.ZX1 _impact.cmd _impact.log makemy.sh~ _ngo oric.bgn oric.bit oric_bitgen.xwbt \
oric.bld oric.drc ORIC.lso oric_map.map oric_map.mrp oric_map.ncd oric_map.ngm ORIC_map.xrpt \ oric.bld oric.drc ORIC.lso oric_map.map oric_map.mrp oric_map.ncd oric_map.ngm ORIC_map.xrpt \
@ -7,3 +7,5 @@ clean:
oric_pad.txt oric.par ORIC_par.xrpt oric.pcf oric.ptwx oric_summary.xml oric.syr oric.twr \ oric_pad.txt oric.par ORIC_par.xrpt oric.pcf oric.ptwx oric_summary.xml oric.syr oric.twr \
oric.twx oric.unroutes oric_usage.xml oric.v4.bit oric.xpi ORIC_xst.xrpt out out.my par_usage_statistics.html \ oric.twx oric.unroutes oric_usage.xml oric.v4.bit oric.xpi ORIC_xst.xrpt out out.my par_usage_statistics.html \
projnav.tmp usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb _xmsgs xst projnav.tmp usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb _xmsgs xst
last:
time -p ./makemylast.sh |tee out

4
cores/Oric/build/ORIC.prj
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@ -15,3 +15,7 @@ vhdl work "../source/m6522.vhd"
vhdl work "../source/keyboard/keyboard.vhd" vhdl work "../source/keyboard/keyboard.vhd"
vhdl work "../source/dac.vhd" vhdl work "../source/dac.vhd"
vhdl work "../source/oricatmos.vhd" vhdl work "../source/oricatmos.vhd"
vhdl work "../source/led_multiplex.vhd"
vhdl work "../source/led_output.vhd"
vhdl work "../source/onebitadc.vhd"
vhdl work "../source/clkdiv.vhd"

44
cores/Oric/source/oric_zxuno_my.ucf
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@ -3,22 +3,23 @@ NET "CLK_50" LOC="P126" | IOSTANDARD = LVCMOS25 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS25; #NET "testled" LOC="P10" | IOSTANDARD = LVCMOS25;
# Video output # Video output
NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; #NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
#NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS25; #NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS25;
#NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS25; #NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS25;
# Audio # Audio
NET "AUDIO_OUT" LOC="P94" | IOSTANDARD = LVCMOS25; NET "AUDIO_OUT" LOC="P94" | IOSTANDARD = LVCMOS25;
NET "AUDIO_OUT2" LOC="P8" | IOSTANDARD = LVCMOS25;
NET "K7_TAPEOUT" LOC="P115" | IOSTANDARD = LVCMOS25; NET "K7_TAPEOUT" LOC="P115" | IOSTANDARD = LVCMOS25;
NET "K7_TAPEIN" LOC="P116" | IOSTANDARD = LVCMOS25; NET "K7_TAPEIN" LOC="P116" | IOSTANDARD = LVCMOS25;
@ -49,6 +50,7 @@ NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS25; #NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS25; #NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS25; #NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS25; #NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS25;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS25; #NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS25;
@ -76,6 +78,26 @@ NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS25; #NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS25;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS25; #NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS25;
NET "segment(0)" LOC="P81" | IOSTANDARD = LVCMOS25;
NET "segment(1)" LOC="P80" | IOSTANDARD = LVCMOS25;
NET "segment(2)" LOC="P79" | IOSTANDARD = LVCMOS25;
NET "segment(3)" LOC="P78" | IOSTANDARD = LVCMOS25;
NET "segment(4)" LOC="P75" | IOSTANDARD = LVCMOS25;
NET "segment(5)" LOC="P74" | IOSTANDARD = LVCMOS25;
NET "segment(6)" LOC="P12" | IOSTANDARD = LVCMOS25;
NET "segment(7)" LOC="P14" | IOSTANDARD = LVCMOS25;
NET "position(0)" LOC="P82" | IOSTANDARD = LVCMOS25;
NET "position(1)" LOC="P83" | IOSTANDARD = LVCMOS25;
NET "position(2)" LOC="P84" | IOSTANDARD = LVCMOS25;
NET "position(3)" LOC="P85" | IOSTANDARD = LVCMOS25;
NET "position(4)" LOC="P87" | IOSTANDARD = LVCMOS25;
NET "position(5)" LOC="P88" | IOSTANDARD = LVCMOS25;
NET "position(6)" LOC="P92" | IOSTANDARD = LVCMOS25;
NET "position(7)" LOC="P93" | IOSTANDARD = LVCMOS25;
# JOYSTICK # JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS25 | PULLUP; #NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS25 | PULLUP; #NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS25 | PULLUP;

109
cores/Oric/source/oricatmos.vhd
View File

@ -31,19 +31,21 @@ port (
-- Audio out -- Audio out
AUDIO_OUT : out std_logic; AUDIO_OUT : out std_logic;
-- Audio out 2
AUDIO_OUT2 : out std_logic;
-- VGA out -- VGA out
O_VIDEO_R : inout std_logic_vector(2 downto 0); --Q O_VIDEO_R : out std_logic_vector(2 downto 2); --Q
O_VIDEO_G : inout std_logic_vector(2 downto 0); --Q O_VIDEO_G : out std_logic_vector(2 downto 2); --Q
O_VIDEO_B : inout std_logic_vector(2 downto 0); --Q O_VIDEO_B : out std_logic_vector(2 downto 2); --Q
O_HSYNC : inout std_logic; O_HSYNC : out std_logic;
O_VSYNC : inout std_logic; O_VSYNC : out std_logic;
D_VIDEO_R : out std_logic_vector(2 downto 0); --Q --D_VIDEO_R : out std_logic_vector(2 downto 0); --Q
D_VIDEO_G : out std_logic_vector(2 downto 0); --Q --D_VIDEO_G : out std_logic_vector(2 downto 0); --Q
D_VIDEO_B : out std_logic_vector(2 downto 0); --Q --D_VIDEO_B : out std_logic_vector(2 downto 0); --Q
D_HSYNC : out std_logic; --D_HSYNC : out std_logic;
D_VSYNC : out std_logic; --D_VSYNC : out std_logic;
VIDEO_SYNC : out std_logic; VIDEO_SYNC : out std_logic;
@ -73,7 +75,9 @@ port (
O_PAL : out std_logic; --Q O_PAL : out std_logic; --Q
-- Clk master -- Clk master
CLK_50 : in std_logic -- MASTER CLK CLK_50 : in std_logic; -- MASTER CLK
segment : out std_logic_vector( 7 downto 0);
position : out std_logic_vector( 7 downto 0)
); );
end; end;
@ -100,6 +104,7 @@ architecture RTL of ORIC is
signal CPU_ADDR : std_logic_vector(23 downto 0); signal CPU_ADDR : std_logic_vector(23 downto 0);
signal CPU_DI : std_logic_vector( 7 downto 0); signal CPU_DI : std_logic_vector( 7 downto 0);
signal CPU_DO : std_logic_vector( 7 downto 0); signal CPU_DO : std_logic_vector( 7 downto 0);
signal DATA_BUS_OUT:std_logic_vector(7 downto 0);
signal cpu_rw : std_logic; signal cpu_rw : std_logic;
signal cpu_irq : std_logic; signal cpu_irq : std_logic;
signal ad : std_logic_vector(15 downto 0); signal ad : std_logic_vector(15 downto 0);
@ -128,6 +133,9 @@ architecture RTL of ORIC is
-- PSG -- PSG
signal psg_bdir : std_logic; -- PSG read/write signal psg_bdir : std_logic; -- PSG read/write
signal PSG_OUT : std_logic_vector( 7 downto 0); signal PSG_OUT : std_logic_vector( 7 downto 0);
signal vaudio_out : std_logic_vector(7 downto 0);
-- ULA -- ULA
signal ula_phi2 : std_logic; signal ula_phi2 : std_logic;
@ -174,11 +182,11 @@ begin
-- generate all the system clocks required -- generate all the system clocks required
----------------------------------------------- -----------------------------------------------
D_VIDEO_R <= O_VIDEO_R; --D_VIDEO_R <= O_VIDEO_R;
D_VIDEO_G <= O_VIDEO_G; --D_VIDEO_G <= O_VIDEO_G;
D_VIDEO_B <= O_VIDEO_B; --D_VIDEO_B <= O_VIDEO_B;
D_HSYNC <= O_HSYNC; --D_HSYNC <= O_HSYNC;
D_VSYNC <= O_VSYNC; --D_VSYNC <= O_VSYNC;
NMI_INT <= not I_NMI; NMI_INT <= not I_NMI;
RESET_INT <= not I_RESET; RESET_INT <= not I_RESET;
@ -360,13 +368,13 @@ begin
hC => 24, -- h back porch hC => 24, -- h back porch
hD => 240, -- visible video hD => 240, -- visible video
-- vA => 34, -- v front porch (not used) vA => 40, -- v front porch (not used)
vB => 2, -- v sync vB => 2, -- v sync
vC => 20, -- v back porch vC => 2, -- v back porch
vD => 224, -- visible video vD => 240, -- visible video
hpad => 32, -- H black border hpad => 32, -- H black border
vpad => 32 -- V black border vpad => 0 -- V black border
) )
port map ( port map (
I_VIDEO(15 downto 12) => "0000", I_VIDEO(15 downto 12) => "0000",
@ -419,11 +427,18 @@ begin
O_NTSC <= '0'; O_NTSC <= '0';
O_PAL <= '1'; O_PAL <= '1';
O_HSYNC <= ULA_SYNC; -- rgb output
O_VSYNC <= vs_int; --O_HSYNC <= ULA_SYNC;
O_VIDEO_R <= ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R; --O_VSYNC <= vs_int;
O_VIDEO_G <= ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G; --O_VIDEO_R(2) <= ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
O_VIDEO_B <= ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B; --O_VIDEO_G(2) <= ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
--O_VIDEO_B(2) <= ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
-- vga output
O_HSYNC <= HSync;
O_VSYNC <= VSync;
O_VIDEO_R(2) <= VideoR(3); -- ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
O_VIDEO_G(2) <= VideoG(3); -- ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
O_VIDEO_B(2) <= VideoB(3);-- ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
---- ----
--fQ --fQ
@ -527,13 +542,44 @@ begin
------------------------------------------------------------ ------------------------------------------------------------
-- Sigma Delta DAC -- Sigma Delta DAC
------------------------------------------------------------
inst_dac : entity work.DAC inst_dac : entity work.DAC
port map ( port map (
clk_i => clk24, clk_i => clk24,
resetn => loc_reset_n, resetn => loc_reset_n,
dac_i => PSG_OUT, dac_i => PSG_OUT,
dac_o => AUDIO_OUT dac_o => AUDIO_OUT2
);
-- this is my piezo output
onebit : entity work.XSP6X9_onebit
generic map (k => 21)
port map (
nreset => I_RESET,
clk => clk24,
input => PSG_OUT,
output => AUDIO_OUT,
voutput => vaudio_out
);
--process
--begin
-- wait until rising_edge(clk24);
-- AUDIO_OUT <= PSG_OUT(5);
--end process;
led_display : entity work.XSP6X9_Led_Output
port map (
clk => clk6,
inputs(7 downto 0) => DATA_BUS_OUT,
inputs(23 downto 8) => CPU_ADDR(15 downto 0),
--inputs(11 downto 8) => X"e",
--inputs(15 downto 12) => X"f",
--inputs(19 downto 16) => X"a",
--inputs(23 downto 20) => X"c",
inputs(27 downto 24) => PSG_OUT(3 downto 0),
inputs(31 downto 28) => PSG_OUT(7 downto 4),
segment => segment,
position => position
); );
------------------------------------------------------------ ------------------------------------------------------------
@ -559,6 +605,15 @@ begin
cpu_di <= SRAM_DO; cpu_di <= SRAM_DO;
end if; end if;
end process; end process;
process -- figure out ram
begin
wait until rising_edge(clk24);
if (cpu_rw = '1')then
DATA_BUS_OUT <= CPU_DI;
else
DATA_BUS_OUT <= CPU_DO;
end if;
end process;
------------------------------------------------------------ ------------------------------------------------------------
-- K7 PORT -- K7 PORT

8
cores/Oric/source/scan_converter.vhd
View File

@ -58,7 +58,7 @@ entity VGA_SCANCONV is
hC : integer range 0 to 1023 := 48; -- h back porch hC : integer range 0 to 1023 := 48; -- h back porch
hD : integer range 0 to 1023 := 640; -- visible video hD : integer range 0 to 1023 := 640; -- visible video
-- vA : integer range 0 to 1023 := 16; -- v front porch vA : integer range 0 to 1023 := 16; -- v front porch
vB : integer range 0 to 1023 := 2; -- v sync vB : integer range 0 to 1023 := 2; -- v sync
vC : integer range 0 to 1023 := 33; -- v back porch vC : integer range 0 to 1023 := 33; -- v back porch
vD : integer range 0 to 1023 := 480; -- visible video vD : integer range 0 to 1023 := 480; -- visible video
@ -198,7 +198,7 @@ begin
begin begin
wait until rising_edge(CLK_x2); wait until rising_edge(CLK_x2);
-- V sync timing -- V sync timing
if (vcnt < vB) then if (vcnt < vB+vA) and (vcnt >= vA) then
O_VSYNC <= '0'; O_VSYNC <= '0';
else else
O_VSYNC <= '1'; O_VSYNC <= '1';
@ -210,7 +210,7 @@ begin
begin begin
wait until rising_edge(CLK_x2); wait until rising_edge(CLK_x2);
-- visible video area doubled from the original game -- visible video area doubled from the original game
if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vB + vC + vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vA + vB + vC+vpad)) and (vcnt <= 2*(vA + vB + vC + vD + vpad))) then
hpos_o <= hpos_o + 1; hpos_o <= hpos_o + 1;
else else
hpos_o <= (others => '0'); hpos_o <= (others => '0');
@ -222,7 +222,7 @@ begin
begin begin
wait until rising_edge(CLK_X2); wait until rising_edge(CLK_X2);
-- active video area 640x480 (VGA) after padding with blank borders -- active video area 640x480 (VGA) after padding with blank borders
if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vA + vB + vC)) and (vcnt <= 2*(vA + vB + vC + vD + 2*vpad))) then
O_CMPBLK_N <= '1'; O_CMPBLK_N <= '1';
else else
O_CMPBLK_N <= '0'; O_CMPBLK_N <= '0';

14
cores/generar.sh
View File

@ -1,9 +1,11 @@
#!/bin/bash #!/bin/bash
#call %ruta_bat%mypath #call %ruta_bat%mypath
ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc "$ruta_ucf"_zxuno_"$1".ucf -p xc6slx9-tqg144-"$speed" "$machine".ngc "$machine".ngd ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc "$ruta_ucf"_zxuno_"$1".ucf -p xc6slx9-tqg144-"$speed" "$machine".ngc "$machine".ngd
map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf # map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf # par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
bitgen -intstyle ise -f "$machine".ut "$machine".ncd # trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
bit2bin "$machine".bit COREn."$2" # bitgen -intstyle ise -f "$machine".ut "$machine".ncd
cp "$machine".bit "$machine"."$1".bit # bit2bin "$machine".bit COREn."$2"
# cp "$machine".bit "$machine"."$1".bit
"$ruta_bat"generarlast.sh "$1" "$2"