mirror of https://github.com/zxdos/zxuno.git
Fixed vga & sound via the buzzer. A & D output on leds
This commit is contained in:
byrtolet
parent
00515cd931
commit
64673306fa
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@ -1,5 +1,5 @@
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all:
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./makemy.sh
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time -p ./makemy.sh |tee out
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clean:
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rm -rf COREn.ZX1 _impact.cmd _impact.log makemy.sh~ _ngo oric.bgn oric.bit oric_bitgen.xwbt \
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oric.bld oric.drc ORIC.lso oric_map.map oric_map.mrp oric_map.ncd oric_map.ngm ORIC_map.xrpt \
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@ -7,3 +7,5 @@ clean:
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oric_pad.txt oric.par ORIC_par.xrpt oric.pcf oric.ptwx oric_summary.xml oric.syr oric.twr \
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oric.twx oric.unroutes oric_usage.xml oric.v4.bit oric.xpi ORIC_xst.xrpt out out.my par_usage_statistics.html \
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projnav.tmp usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb _xmsgs xst
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last:
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time -p ./makemylast.sh |tee out
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@ -15,3 +15,7 @@ vhdl work "../source/m6522.vhd"
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vhdl work "../source/keyboard/keyboard.vhd"
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vhdl work "../source/dac.vhd"
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vhdl work "../source/oricatmos.vhd"
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vhdl work "../source/led_multiplex.vhd"
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vhdl work "../source/led_output.vhd"
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vhdl work "../source/onebitadc.vhd"
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vhdl work "../source/clkdiv.vhd"
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@ -3,22 +3,23 @@ NET "CLK_50" LOC="P126" | IOSTANDARD = LVCMOS25 | PERIOD=20.0ns;
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#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS25;
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# Video output
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NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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#NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
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NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 6 | SLEW = SLOW;
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#NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS25;
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#NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS25;
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# Audio
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NET "AUDIO_OUT" LOC="P94" | IOSTANDARD = LVCMOS25;
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NET "AUDIO_OUT2" LOC="P8" | IOSTANDARD = LVCMOS25;
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NET "K7_TAPEOUT" LOC="P115" | IOSTANDARD = LVCMOS25;
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NET "K7_TAPEIN" LOC="P116" | IOSTANDARD = LVCMOS25;
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@ -49,6 +50,7 @@ NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS25;
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@ -76,6 +78,26 @@ NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS25;
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#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS25;
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NET "segment(0)" LOC="P81" | IOSTANDARD = LVCMOS25;
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NET "segment(1)" LOC="P80" | IOSTANDARD = LVCMOS25;
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NET "segment(2)" LOC="P79" | IOSTANDARD = LVCMOS25;
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NET "segment(3)" LOC="P78" | IOSTANDARD = LVCMOS25;
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NET "segment(4)" LOC="P75" | IOSTANDARD = LVCMOS25;
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NET "segment(5)" LOC="P74" | IOSTANDARD = LVCMOS25;
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NET "segment(6)" LOC="P12" | IOSTANDARD = LVCMOS25;
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NET "segment(7)" LOC="P14" | IOSTANDARD = LVCMOS25;
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NET "position(0)" LOC="P82" | IOSTANDARD = LVCMOS25;
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NET "position(1)" LOC="P83" | IOSTANDARD = LVCMOS25;
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NET "position(2)" LOC="P84" | IOSTANDARD = LVCMOS25;
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NET "position(3)" LOC="P85" | IOSTANDARD = LVCMOS25;
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NET "position(4)" LOC="P87" | IOSTANDARD = LVCMOS25;
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NET "position(5)" LOC="P88" | IOSTANDARD = LVCMOS25;
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NET "position(6)" LOC="P92" | IOSTANDARD = LVCMOS25;
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NET "position(7)" LOC="P93" | IOSTANDARD = LVCMOS25;
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# JOYSTICK
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#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS25 | PULLUP;
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@ -31,19 +31,21 @@ port (
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-- Audio out
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AUDIO_OUT : out std_logic;
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-- Audio out 2
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AUDIO_OUT2 : out std_logic;
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-- VGA out
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O_VIDEO_R : inout std_logic_vector(2 downto 0); --Q
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O_VIDEO_G : inout std_logic_vector(2 downto 0); --Q
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O_VIDEO_B : inout std_logic_vector(2 downto 0); --Q
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O_HSYNC : inout std_logic;
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O_VSYNC : inout std_logic;
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O_VIDEO_R : out std_logic_vector(2 downto 2); --Q
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O_VIDEO_G : out std_logic_vector(2 downto 2); --Q
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O_VIDEO_B : out std_logic_vector(2 downto 2); --Q
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O_HSYNC : out std_logic;
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O_VSYNC : out std_logic;
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D_VIDEO_R : out std_logic_vector(2 downto 0); --Q
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D_VIDEO_G : out std_logic_vector(2 downto 0); --Q
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D_VIDEO_B : out std_logic_vector(2 downto 0); --Q
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D_HSYNC : out std_logic;
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D_VSYNC : out std_logic;
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--D_VIDEO_R : out std_logic_vector(2 downto 0); --Q
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--D_VIDEO_G : out std_logic_vector(2 downto 0); --Q
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--D_VIDEO_B : out std_logic_vector(2 downto 0); --Q
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--D_HSYNC : out std_logic;
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--D_VSYNC : out std_logic;
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VIDEO_SYNC : out std_logic;
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@ -73,7 +75,9 @@ port (
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O_PAL : out std_logic; --Q
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-- Clk master
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CLK_50 : in std_logic -- MASTER CLK
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CLK_50 : in std_logic; -- MASTER CLK
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segment : out std_logic_vector( 7 downto 0);
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position : out std_logic_vector( 7 downto 0)
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);
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end;
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@ -100,6 +104,7 @@ architecture RTL of ORIC is
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signal CPU_ADDR : std_logic_vector(23 downto 0);
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signal CPU_DI : std_logic_vector( 7 downto 0);
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signal CPU_DO : std_logic_vector( 7 downto 0);
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signal DATA_BUS_OUT:std_logic_vector(7 downto 0);
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signal cpu_rw : std_logic;
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signal cpu_irq : std_logic;
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signal ad : std_logic_vector(15 downto 0);
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@ -128,6 +133,9 @@ architecture RTL of ORIC is
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-- PSG
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signal psg_bdir : std_logic; -- PSG read/write
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signal PSG_OUT : std_logic_vector( 7 downto 0);
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signal vaudio_out : std_logic_vector(7 downto 0);
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-- ULA
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signal ula_phi2 : std_logic;
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@ -174,11 +182,11 @@ begin
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-- generate all the system clocks required
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-----------------------------------------------
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D_VIDEO_R <= O_VIDEO_R;
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D_VIDEO_G <= O_VIDEO_G;
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D_VIDEO_B <= O_VIDEO_B;
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D_HSYNC <= O_HSYNC;
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D_VSYNC <= O_VSYNC;
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--D_VIDEO_R <= O_VIDEO_R;
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--D_VIDEO_G <= O_VIDEO_G;
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--D_VIDEO_B <= O_VIDEO_B;
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--D_HSYNC <= O_HSYNC;
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--D_VSYNC <= O_VSYNC;
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NMI_INT <= not I_NMI;
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RESET_INT <= not I_RESET;
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@ -360,13 +368,13 @@ begin
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hC => 24, -- h back porch
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hD => 240, -- visible video
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-- vA => 34, -- v front porch (not used)
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vA => 40, -- v front porch (not used)
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vB => 2, -- v sync
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vC => 20, -- v back porch
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vD => 224, -- visible video
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vC => 2, -- v back porch
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vD => 240, -- visible video
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hpad => 32, -- H black border
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vpad => 32 -- V black border
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vpad => 0 -- V black border
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)
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port map (
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I_VIDEO(15 downto 12) => "0000",
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@ -419,11 +427,18 @@ begin
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O_NTSC <= '0';
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O_PAL <= '1';
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O_HSYNC <= ULA_SYNC;
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O_VSYNC <= vs_int;
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O_VIDEO_R <= ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R;
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O_VIDEO_G <= ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G;
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O_VIDEO_B <= ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B;
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-- rgb output
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--O_HSYNC <= ULA_SYNC;
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--O_VSYNC <= vs_int;
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--O_VIDEO_R(2) <= ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
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--O_VIDEO_G(2) <= ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
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--O_VIDEO_B(2) <= ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
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-- vga output
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O_HSYNC <= HSync;
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O_VSYNC <= VSync;
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O_VIDEO_R(2) <= VideoR(3); -- ULA_VIDEO_R;-- & ULA_VIDEO_R & ULA_VIDEO_R;
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O_VIDEO_G(2) <= VideoG(3); -- ULA_VIDEO_G;-- & ULA_VIDEO_G & ULA_VIDEO_G;
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O_VIDEO_B(2) <= VideoB(3);-- ULA_VIDEO_B;-- & ULA_VIDEO_B & ULA_VIDEO_B;
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----
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--fQ
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@ -527,13 +542,44 @@ begin
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------------------------------------------------------------
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-- Sigma Delta DAC
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------------------------------------------------------------
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inst_dac : entity work.DAC
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port map (
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clk_i => clk24,
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resetn => loc_reset_n,
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dac_i => PSG_OUT,
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dac_o => AUDIO_OUT
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dac_o => AUDIO_OUT2
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);
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-- this is my piezo output
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onebit : entity work.XSP6X9_onebit
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generic map (k => 21)
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port map (
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nreset => I_RESET,
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clk => clk24,
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input => PSG_OUT,
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output => AUDIO_OUT,
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voutput => vaudio_out
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);
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--process
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--begin
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-- wait until rising_edge(clk24);
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-- AUDIO_OUT <= PSG_OUT(5);
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--end process;
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led_display : entity work.XSP6X9_Led_Output
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port map (
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clk => clk6,
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inputs(7 downto 0) => DATA_BUS_OUT,
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inputs(23 downto 8) => CPU_ADDR(15 downto 0),
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--inputs(11 downto 8) => X"e",
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--inputs(15 downto 12) => X"f",
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--inputs(19 downto 16) => X"a",
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--inputs(23 downto 20) => X"c",
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inputs(27 downto 24) => PSG_OUT(3 downto 0),
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inputs(31 downto 28) => PSG_OUT(7 downto 4),
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segment => segment,
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position => position
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);
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------------------------------------------------------------
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@ -559,6 +605,15 @@ begin
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cpu_di <= SRAM_DO;
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end if;
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end process;
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process -- figure out ram
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begin
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wait until rising_edge(clk24);
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if (cpu_rw = '1')then
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DATA_BUS_OUT <= CPU_DI;
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else
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DATA_BUS_OUT <= CPU_DO;
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end if;
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end process;
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------------------------------------------------------------
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-- K7 PORT
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@ -58,7 +58,7 @@ entity VGA_SCANCONV is
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hC : integer range 0 to 1023 := 48; -- h back porch
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hD : integer range 0 to 1023 := 640; -- visible video
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-- vA : integer range 0 to 1023 := 16; -- v front porch
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vA : integer range 0 to 1023 := 16; -- v front porch
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vB : integer range 0 to 1023 := 2; -- v sync
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vC : integer range 0 to 1023 := 33; -- v back porch
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vD : integer range 0 to 1023 := 480; -- visible video
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@ -198,7 +198,7 @@ begin
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begin
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wait until rising_edge(CLK_x2);
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-- V sync timing
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if (vcnt < vB) then
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if (vcnt < vB+vA) and (vcnt >= vA) then
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O_VSYNC <= '0';
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else
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O_VSYNC <= '1';
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@ -210,7 +210,7 @@ begin
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begin
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wait until rising_edge(CLK_x2);
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-- visible video area doubled from the original game
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if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vB + vC + vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then
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if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vA + vB + vC+vpad)) and (vcnt <= 2*(vA + vB + vC + vD + vpad))) then
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hpos_o <= hpos_o + 1;
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else
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hpos_o <= (others => '0');
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@ -222,7 +222,7 @@ begin
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begin
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wait until rising_edge(CLK_X2);
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-- active video area 640x480 (VGA) after padding with blank borders
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if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then
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if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vA + vB + vC)) and (vcnt <= 2*(vA + vB + vC + vD + 2*vpad))) then
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O_CMPBLK_N <= '1';
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else
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O_CMPBLK_N <= '0';
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@ -1,9 +1,11 @@
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#!/bin/bash
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#call %ruta_bat%mypath
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ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc "$ruta_ucf"_zxuno_"$1".ucf -p xc6slx9-tqg144-"$speed" "$machine".ngc "$machine".ngd
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map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
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par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
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trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
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bitgen -intstyle ise -f "$machine".ut "$machine".ncd
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bit2bin "$machine".bit COREn."$2"
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cp "$machine".bit "$machine"."$1".bit
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# map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
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# par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
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# trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
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# bitgen -intstyle ise -f "$machine".ut "$machine".ncd
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# bit2bin "$machine".bit COREn."$2"
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# cp "$machine".bit "$machine"."$1".bit
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"$ruta_bat"generarlast.sh "$1" "$2"
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|
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Reference in New Issue