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Actualizo zxpp04

This commit is contained in:
antoniovillena 2016-08-23 22:32:50 +02:00
parent adc419fe22
commit 68d9698a66
14 changed files with 1104 additions and 17 deletions
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3
cores/KypSpectrum/ipcore_dir/hiram.ngc Normal file
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file hiram.vhd when simulating
-- the core, hiram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY hiram IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END hiram;
ARCHITECTURE hiram_a OF hiram IS
-- synthesis translate_off
COMPONENT wrapped_hiram
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_hiram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32768,
c_read_depth_b => 32768,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32768,
c_write_depth_b => 32768,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_hiram
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END hiram_a;

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cores/KypSpectrum/ipcore_dir/loram.ngc
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file loram.vhd when simulating
-- the core, loram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY loram IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END loram;
ARCHITECTURE loram_a OF loram IS
-- synthesis translate_off
COMPONENT wrapped_loram
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_loram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_loram
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END loram_a;

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cores/KypSpectrum/ipcore_dir/rom.ngc
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "FF",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
ena => ena,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;

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-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mapa_es is
constant KEY_RELEASED : std_logic_vector(7 downto 0) := X"f0";
constant KEY_EXTENDED : std_logic_vector(7 downto 0) := X"e0";
constant KEY_ESC : std_logic_vector(7 downto 0) := X"76";
constant KEY_F1 : std_logic_vector(7 downto 0) := X"05";
constant KEY_F2 : std_logic_vector(7 downto 0) := X"06";
constant KEY_F3 : std_logic_vector(7 downto 0) := X"04";
constant KEY_F4 : std_logic_vector(7 downto 0) := X"0C";
constant KEY_F5 : std_logic_vector(7 downto 0) := X"03";
constant KEY_F6 : std_logic_vector(7 downto 0) := X"0B";
constant KEY_F7 : std_logic_vector(7 downto 0) := X"83";
constant KEY_F8 : std_logic_vector(7 downto 0) := X"0A";
constant KEY_F9 : std_logic_vector(7 downto 0) := X"01";
constant KEY_F10 : std_logic_vector(7 downto 0) := X"09";
constant KEY_F11 : std_logic_vector(7 downto 0) := X"78";
constant KEY_F12 : std_logic_vector(7 downto 0) := X"07";
constant KEY_BL : std_logic_vector(7 downto 0) := X"0E";
constant KEY_1 : std_logic_vector(7 downto 0) := X"16";
constant KEY_2 : std_logic_vector(7 downto 0) := X"1E";
constant KEY_3 : std_logic_vector(7 downto 0) := X"26";
constant KEY_4 : std_logic_vector(7 downto 0) := X"25";
constant KEY_5 : std_logic_vector(7 downto 0) := X"2E";
constant KEY_6 : std_logic_vector(7 downto 0) := X"36";
constant KEY_7 : std_logic_vector(7 downto 0) := X"3D";
constant KEY_8 : std_logic_vector(7 downto 0) := X"3E";
constant KEY_9 : std_logic_vector(7 downto 0) := X"46";
constant KEY_0 : std_logic_vector(7 downto 0) := X"45";
constant KEY_APOS : std_logic_vector(7 downto 0) := X"4E";
constant KEY_AEXC : std_logic_vector(7 downto 0) := X"55";
constant KEY_BKSP : std_logic_vector(7 downto 0) := X"66";
constant KEY_TAB : std_logic_vector(7 downto 0) := X"0D";
constant KEY_Q : std_logic_vector(7 downto 0) := X"15";
constant KEY_W : std_logic_vector(7 downto 0) := X"1D";
constant KEY_E : std_logic_vector(7 downto 0) := X"24";
constant KEY_R : std_logic_vector(7 downto 0) := X"2D";
constant KEY_T : std_logic_vector(7 downto 0) := X"2C";
constant KEY_Y : std_logic_vector(7 downto 0) := X"35";
constant KEY_U : std_logic_vector(7 downto 0) := X"3C";
constant KEY_I : std_logic_vector(7 downto 0) := X"43";
constant KEY_O : std_logic_vector(7 downto 0) := X"44";
constant KEY_P : std_logic_vector(7 downto 0) := X"4D";
constant KEY_CORCHA : std_logic_vector(7 downto 0) := X"54";
constant KEY_CORCHC : std_logic_vector(7 downto 0) := X"5B";
constant KEY_ENTER : std_logic_vector(7 downto 0) := X"5A";
constant KEY_CPSLK : std_logic_vector(7 downto 0) := X"58";
constant KEY_A : std_logic_vector(7 downto 0) := X"1C";
constant KEY_S : std_logic_vector(7 downto 0) := X"1B";
constant KEY_D : std_logic_vector(7 downto 0) := X"23";
constant KEY_F : std_logic_vector(7 downto 0) := X"2B";
constant KEY_G : std_logic_vector(7 downto 0) := X"34";
constant KEY_H : std_logic_vector(7 downto 0) := X"33";
constant KEY_J : std_logic_vector(7 downto 0) := X"3B";
constant KEY_K : std_logic_vector(7 downto 0) := X"42";
constant KEY_L : std_logic_vector(7 downto 0) := X"4B";
constant KEY_NT : std_logic_vector(7 downto 0) := X"4C";
constant KEY_LLAVA : std_logic_vector(7 downto 0) := X"52";
constant KEY_LLAVC : std_logic_vector(7 downto 0) := X"5D";
constant KEY_LSHIFT : std_logic_vector(7 downto 0) := X"12";
constant KEY_LT : std_logic_vector(7 downto 0) := X"61";
constant KEY_Z : std_logic_vector(7 downto 0) := X"1A";
constant KEY_X : std_logic_vector(7 downto 0) := X"22";
constant KEY_C : std_logic_vector(7 downto 0) := X"21";
constant KEY_V : std_logic_vector(7 downto 0) := X"2A";
constant KEY_B : std_logic_vector(7 downto 0) := X"32";
constant KEY_N : std_logic_vector(7 downto 0) := X"31";
constant KEY_M : std_logic_vector(7 downto 0) := X"3A";
constant KEY_COMA : std_logic_vector(7 downto 0) := X"41";
constant KEY_PUNTO : std_logic_vector(7 downto 0) := X"49";
constant KEY_MENOS : std_logic_vector(7 downto 0) := X"4A";
constant KEY_RSHIFT : std_logic_vector(7 downto 0) := X"59";
constant KEY_CTRLI : std_logic_vector(7 downto 0) := X"14";
constant KEY_ALTI : std_logic_vector(7 downto 0) := X"11";
constant KEY_SPACE : std_logic_vector(7 downto 0) := X"29";
constant KEY_KP0 : std_logic_vector(7 downto 0) := X"70";
constant KEY_KP1 : std_logic_vector(7 downto 0) := X"69";
constant KEY_KP2 : std_logic_vector(7 downto 0) := X"72";
constant KEY_KP3 : std_logic_vector(7 downto 0) := X"7A";
constant KEY_KP4 : std_logic_vector(7 downto 0) := X"6B";
constant KEY_KP5 : std_logic_vector(7 downto 0) := X"73";
constant KEY_KP6 : std_logic_vector(7 downto 0) := X"74";
constant KEY_KP7 : std_logic_vector(7 downto 0) := X"6C";
constant KEY_KP8 : std_logic_vector(7 downto 0) := X"75";
constant KEY_KP9 : std_logic_vector(7 downto 0) := X"7D";
constant KEY_KPPUNTO : std_logic_vector(7 downto 0) := X"71";
constant KEY_KPMAS : std_logic_vector(7 downto 0) := X"79";
constant KEY_KPMENOS : std_logic_vector(7 downto 0) := X"7B";
constant KEY_KPASTER : std_logic_vector(7 downto 0) := X"7C";
constant KEY_BLKNUM : std_logic_vector(7 downto 0) := X"77";
constant KEY_BLKSCR : std_logic_vector(7 downto 0) := X"7E";
-- Teclas con E0 + scancode
constant KEY_WAKEUP : std_logic_vector(7 downto 0) := X"5E";
constant KEY_SLEEP : std_logic_vector(7 downto 0) := X"3F";
constant KEY_POWER : std_logic_vector(7 downto 0) := X"37";
constant KEY_INS : std_logic_vector(7 downto 0) := X"70";
constant KEY_SUP : std_logic_vector(7 downto 0) := X"71";
constant KEY_HOME : std_logic_vector(7 downto 0) := X"6C";
constant KEY_END : std_logic_vector(7 downto 0) := X"69";
constant KEY_PGU : std_logic_vector(7 downto 0) := X"7D";
constant KEY_PGD : std_logic_vector(7 downto 0) := X"7A";
constant KEY_UP : std_logic_vector(7 downto 0) := X"75";
constant KEY_DOWN : std_logic_vector(7 downto 0) := X"72";
constant KEY_LEFT : std_logic_vector(7 downto 0) := X"6B";
constant KEY_RIGHT : std_logic_vector(7 downto 0) := X"74";
constant KEY_CTRLD : std_logic_vector(7 downto 0) := X"14";
constant KEY_ALTGR : std_logic_vector(7 downto 0) := X"11";
constant KEY_KPENTER : std_logic_vector(7 downto 0) := X"5A";
constant KEY_KPSLASH : std_logic_vector(7 downto 0) := X"4A";
constant KEY_PRTSCR : std_logic_vector(7 downto 0) := X"7C";
end package mapa_es;
package body mapa_es is
end package body mapa_es;

356
cores/KypSpectrum/keyboard.zxuno.vhd Normal file
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@ -0,0 +1,356 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mapa_es.all;
entity keyboard is
port
(
clock : in std_logic;
ps2c : in std_logic;
ps2d : in std_logic;
rows : in std_logic_vector(7 downto 0);
cols : out std_logic_vector(4 downto 0)
);
end;
architecture behavioral of keyboard is
type key_matrix is array (7 downto 0) of std_logic_vector(4 downto 0);
signal keys : key_matrix;
signal pressed : std_logic;
-- signal isctrl : std_logic;
signal isshift : std_logic;
-- signal isalt : std_logic;
signal isextend : std_logic;
signal lastclk : std_logic_vector(4 downto 0);
signal bit_count : unsigned (3 downto 0);
signal shiftreg : std_logic_vector(8 downto 0);
signal parity : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
-- rst <= '1';
-- nmi <= '1';
-- mrst <= '1';
lastclk <= lastclk(3 downto 0) & ps2c;
if lastclk = "11100" and ps2c = '0' then -- detector de flanco de bajada de PS2CLK
if bit_count = 0 then
parity <= '0';
if ps2d = '0' then bit_count <= bit_count+1; end if;
else
if bit_count < 10 then
bit_count <= bit_count+1;
shiftreg <= ps2d&shiftreg(8 downto 1);
parity <= parity xor ps2d;
elsif ps2d = '1' then
bit_count <= (others => '0');
if parity = '1' then -- nueva pulsacion completa en shiftreg.
pressed <= '1';
-- scancode <= shiftreg(7 downto 0);
if isextend = '1' and shiftreg(7 downto 0) = KEY_RELEASED then isextend <= '1'; else isextend <= '0'; end if; -- procesar la secuencia E0 F0 key
case shiftreg(7 downto 0) is -- detectar secuencias especiales: tecla soltada y tecla extendida
when KEY_RELEASED => pressed <= '0';
when KEY_EXTENDED => isextend <= '1';
when others =>
end case;
if isextend='0' then -- teclas no extendidas
case shiftreg(7 downto 0) is
when KEY_LSHIFT |
KEY_RSHIFT => isshift <= pressed;
-- when KEY_ALTI => isalt <= pressed;
-- joy(4) <= pressed; -- dato entregado por el joystick
when KEY_CTRLI => keys(0)(0) <= pressed; -- Ctrl izquierdo: (CAPS SHIFT)
-- isctrl <= pressed;
-- joy(4) <= pressed; -- dato entregado por el joystick
when KEY_Z => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(0)(1) <= pressed; -- Z
when KEY_X => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(0)(2) <= pressed; -- X
when KEY_C => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(0)(3) <= pressed; -- C
when KEY_V => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(0)(4) <= pressed; -- V
when KEY_A => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(1)(0) <= pressed; -- A
when KEY_S => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(1)(1) <= pressed; -- S
when KEY_D => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(1)(2) <= pressed; -- D
when KEY_F => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(1)(3) <= pressed; -- F
when KEY_G => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(1)(4) <= pressed; -- G
when KEY_Q => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(2)(0) <= pressed; -- Q
when KEY_W => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(2)(1) <= pressed; -- W
when KEY_E => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(2)(2) <= pressed; -- E
when KEY_R => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(2)(3) <= pressed; -- R
when KEY_T => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(2)(4) <= pressed; -- T
when KEY_1 => if isshift='0' then
keys(3)(0) <= pressed; -- 1
else
keys(7)(1) <= pressed;
keys(3)(0) <= pressed; -- !
end if;
when KEY_2 => if isshift='0' then
keys(3)(1) <= pressed; -- 2
else
keys(7)(1) <= pressed;
keys(5)(0) <= pressed; -- "
end if;
when KEY_3 => if isshift='0' then
keys(3)(2) <= pressed; -- 3
else
keys(7)(1) <= pressed;
keys(3)(2) <= pressed; -- #
end if;
when KEY_4 => if isshift='0' then
keys(3)(3) <= pressed; -- 4
else
keys(7)(1) <= pressed;
keys(3)(3) <= pressed; -- $
end if;
when KEY_5 => if isshift='0' then
keys(3)(4) <= pressed; -- 5
else
keys(7)(1) <= pressed;
keys(3)(4) <= pressed; -- $
end if;
when KEY_0 => if isshift='0' then
keys(4)(0) <= pressed; -- 0
else
keys(7)(1) <= pressed;
keys(6)(1) <= pressed; -- =
end if;
when KEY_9 => if isshift='0' then
keys(4)(1) <= pressed; -- 9
else
keys(7)(1) <= pressed;
keys(4)(1) <= pressed; -- )
end if;
when KEY_8 => if isshift='0' then
keys(4)(2) <= pressed; -- 8
else
keys(7)(1) <= pressed;
keys(4)(2) <= pressed; -- (
end if;
when KEY_7 => if isshift='0' then
keys(4)(3) <= pressed; -- 7
else
keys(7)(1) <= pressed;
keys(0)(4) <= pressed; -- /
end if;
when KEY_6 => if isshift='0' then
keys(4)(4) <= pressed; -- 6
else
keys(7)(1) <= pressed;
keys(4)(4) <= pressed; -- &
end if;
when KEY_P => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(5)(0) <= pressed; -- P
when KEY_O => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(5)(1) <= pressed; -- O
when KEY_I => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(5)(2) <= pressed; -- I
when KEY_U => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(5)(3) <= pressed; -- U
when KEY_Y => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(5)(4) <= pressed; -- Y
when KEY_ENTER => keys(6)(0) <= pressed; -- ENTER
when KEY_L => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(6)(1) <= pressed; -- L
when KEY_K => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(6)(2) <= pressed; -- K
when KEY_J => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(6)(3) <= pressed; -- J
when KEY_H => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(6)(4) <= pressed; -- H
when KEY_SPACE => keys(7)(0) <= pressed; -- SPACE
when KEY_M => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(7)(2) <= pressed; -- M
when KEY_N => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(7)(3) <= pressed; -- N
when KEY_B => if isshift='1' then
keys(0)(0) <= pressed;
end if;
keys(7)(4) <= pressed; -- B
when KEY_BKSP => keys(0)(0) <= pressed; -- Backspace (Caps 0)
keys(4)(0) <= pressed;
-- if isctrl='1' and isalt='1' then
-- mrst <= '0';
-- end if;
when KEY_CPSLK => keys(0)(0) <= pressed; -- Caps lock (Caps 2)
keys(3)(1) <= pressed;
when KEY_ESC => keys(0)(0) <= pressed; -- Break (Caps Space)
keys(7)(0) <= pressed;
when KEY_F2 => keys(0)(0) <= pressed;
keys(3)(0) <= pressed; -- EDIT
when KEY_BL => keys(7)(1) <= pressed;
keys(1)(2) <= pressed; -- usado con EXT, da \
when KEY_APOS => keys(7)(1) <= pressed;
if isshift='0' then
keys(4)(3) <= pressed; -- apostrofe '
else
keys(0)(3) <= pressed; -- tecla ?
end if;
when KEY_TAB => keys(0)(0) <= pressed;
keys(7)(1) <= pressed; -- modo extendido
when KEY_CORCHA => keys(7)(1) <= pressed;
keys(6)(4) <= pressed; -- simbolo ^
when KEY_CORCHC => keys(7)(1) <= pressed;
if isshift='0' then
keys(6)(2) <= pressed; -- simbolo +
else
keys(7)(4) <= pressed; -- simbolo *
end if;
when KEY_LLAVA => keys(7)(1) <= pressed;
keys(1)(3) <= pressed; -- llave abierta, con EXT
when KEY_LLAVC => keys(7)(1) <= pressed;
keys(5)(0) <= pressed; -- copyright
when KEY_LT => keys(7)(1) <= pressed;
if isshift='0' then
keys(2)(3) <= pressed; -- símbolo <
else
keys(2)(4) <= pressed; -- símbolo >
end if;
when KEY_COMA => keys(7)(1) <= pressed;
if isshift='0' then
keys(7)(3) <= pressed; -- símbolo ,
else
keys(5)(1) <= pressed; -- símbolo ;
end if;
when KEY_PUNTO => keys(7)(1) <= pressed;
if isshift='0' then
keys(7)(2) <= pressed; -- símbolo .
else
keys(0)(1) <= pressed; -- símbolo :
end if;
when KEY_MENOS => keys(7)(1) <= pressed;
if isshift='0' then
keys(6)(3) <= pressed; -- símbolo -
else
keys(4)(0) <= pressed; -- tecla _ (guion bajo)
end if;
-- when KEY_F5 => if isctrl='1' and isalt='1' then
-- nmi <= '0'; -- NMI
-- end if;
-- when KEY_KPPUNTO => if isctrl='1' and isalt='1' then
-- rst <= '0'; -- reset al hacer ctrl-alt-supr
-- end if;
-- when KEY_KP4 => joy(1) <= pressed; -- dato entregado por el joystick: izquierda
-- when KEY_KP6 => joy(0) <= pressed; -- dato entregado por el joystick: derecha
-- when KEY_KP8 => joy(3) <= pressed; -- dato entregado por el joystick: arriba
-- when KEY_KP5 => joy(2) <= pressed; -- dato entregado por el joystick: abajo
when others=> null;
end case;
else -- process extended keys
case shiftreg(7 downto 0) is
when KEY_CTRLD => keys(7)(1) <= pressed; -- Ctrl derecho -> symbol shift
-- isctrl <= pressed;
-- joy(4) <= pressed; -- dato entregado por el joystick
-- when KEY_ALTGR => keys(0)(0) <= pressed;
-- keys(4)(1) <= pressed; -- Modo gráfico
-- isalt <= '1';
-- joy(4) <= pressed; -- dato entregado por el joystick
when KEY_LEFT => keys(0)(0) <= pressed; -- Left (Caps 5)
keys(3)(4) <= pressed;
when KEY_DOWN => keys(0)(0) <= pressed; -- Down (Caps 6)
keys(4)(4) <= pressed;
when KEY_UP => keys(0)(0) <= pressed; -- Up (Caps 7)
keys(4)(3) <= pressed;
when KEY_RIGHT => keys(0)(0) <= pressed; -- Right (Caps 8)
keys(4)(2) <= pressed;
-- when KEY_SUP => if isctrl='1' and isalt='1' then
-- rst <= '0'; -- reset al hacer ctrl-alt-supr
-- end if;
when others => null;
end case;
end if;
end if;
else
bit_count <= (others => '0');
end if;
end if;
end if;
end if;
end process;
process(keys, rows)
variable tmp: std_logic;
begin
for i in 0 to 4 loop
tmp := '0';
for j in 0 to 7 loop tmp := tmp or (keys(j)(i) and not rows(j)); end loop;
cols(i) <= not tmp;
end loop;
end process;
end;

40
cores/KypSpectrum/mixer.vhd Normal file
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@ -0,0 +1,40 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mixer is
port
(
clock : in std_logic;
speaker : in std_logic;
ear : in std_logic;
mic : in std_logic;
l : out std_logic;
r : out std_logic
);
end;
architecture behavioral of mixer is
signal mix : std_logic;
begin
l <= mix;
r <= mix;
process(clock)
variable count : std_logic_vector(4 downto 0) := (others => '0');
begin
if rising_edge(clock) then
count := count+1;
case count is
when "00000" => mix <= speaker;
when "01000" => mix <= ear;
when "10000" => mix <= speaker;
when "11000" => mix <= mic;
when others => mix <= '0';
end case;
end if;
end process;
end;

21
cores/KypSpectrum/papilio_zxuno_Pa.ucf
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@ -26,9 +26,26 @@ CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;
NET netRST LOC="P85" | IOSTANDARD=LVTTL | PULLDOWN; # A11
NET netNMI LOC="P59" | IOSTANDARD=LVTTL | PULLDOWN; # B11
NET netCLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
NET netRST LOC="P85" | IOSTANDARD=LVTTL | PULLDOWN; # A11
NET netNMI LOC="P95" | IOSTANDARD=LVTTL | PULLDOWN; # B9 -- SW(2)
NET ps2CLK LOC="P115" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C1
NET ps2DAT LOC="P114" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C0
NET joyBTN(0) LOC="P123" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C8 -- JOYSTICK A1
NET joyBTN(1) LOC="P126" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C10 -- JOYSTICK A2
NET joyBTN(2) LOC="P127" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C11 -- JOYSTICK A3
NET joyBTN(3) LOC="P132" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C13 -- JOYSTICK A4
NET joyBTN(4) LOC="P124" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # C9 -- JOYSTICK A6
# joy+5 # -- JOYSTICK A7
NET joyGND LOC="P131" | IOSTANDARD=LVTTL; # C12 -- JOYSTICK A8
NET audioL LOC="P98" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A14
NET audioR LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # A15
NET audioEAR LOC="P57" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B12 -- JOYSTICK B1
NET audioGND LOC="P48" | IOSTANDARD=LVTTL; # C12 -- JOYSTICK B8
# audio+5 # -- JOYSTICK B7
NET videoV LOC="P116" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2
NET videoH LOC="P117" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C3

20
cores/KypSpectrum/ula.vhd
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@ -14,6 +14,10 @@ entity ula is
di : in std_logic_vector( 7 downto 0);
do : out std_logic_vector( 7 downto 0);
int : out std_logic;
ear : in std_logic;
mic : out std_logic;
speaker : out std_logic;
keycols : in std_logic_vector( 4 downto 0);
va : out std_logic_vector(12 downto 0);
vd : in std_logic_vector( 7 downto 0);
hs : out std_logic;
@ -27,6 +31,9 @@ architecture behavioral of ula is
signal clock : std_logic;
signal portFF : std_logic_vector(2 downto 0);
signal rows : std_logic_vector(7 downto 0);
signal cols : std_logic_vector(4 downto 0);
begin
Uvga: entity work.vga port map
@ -47,6 +54,17 @@ begin
);
clock4 <= clock;
portFF <= di(2 downto 0) when rising_edge(clock) and iorq = '0' and wr = '0' and a0 = '0';
process(clock)
begin
if rising_edge(clock) then
if iorq = '0' and rd = '0' and a0 = '0' then do <= '0'&ear&'0'&keycols; end if;
if iorq = '0' and wr = '0' and a0 = '0' then
portFF <= di(2 downto 0);
mic <= di(3);
speaker <= di(4);
end if;
end if;
end process;
end;

6
cores/KypSpectrum/zxpp.prj
View File

@ -1,12 +1,16 @@
vhdl work "ipcore_dir/rom.vhd"
vhdl work "ipcore_dir/loram.vhd"
vhdl work "ipcore_dir/rom.vhd"
vhdl work "ipcore_dir/hiram.vhd"
verilog work "tv80_reg.v"
verilog work "tv80_mcode.v"
verilog work "tv80_alu.v"
vhdl work "video.vhd"
vhdl work "vga.vhd"
verilog work "tv80_core.v"
vhdl work "keyboard.es.vhd"
vhdl work "ula.vhd"
verilog work "tv80n.v"
vhdl work "mixer.vhd"
vhdl work "keyboard.zxuno.vhd"
vhdl work "clock.vhd"
vhdl work "zxpp.vhd"

92
cores/KypSpectrum/zxpp.vhd
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@ -4,9 +4,20 @@ library ieee;
entity zxpp is
port
(
netCLK : in std_logic;
netRST : in std_logic;
netNMI : in std_logic;
netCLK : in std_logic;
--
ps2CLK : inout std_logic;
ps2DAT : inout std_logic;
--
joyBTN : in std_logic_vector(4 downto 0);
joyGND : out std_logic;
--
audioL : out std_logic;
audioR : out std_logic;
audioEAR : in std_logic;
audioGND : out std_logic;
--
videoV : out std_logic;
videoH : out std_logic;
@ -21,23 +32,39 @@ architecture structural of zxpp is
signal clock25 : std_logic;
signal clock14 : std_logic;
signal clock4 : std_logic;
--
signal reset : std_logic;
signal nmi : std_logic;
signal int : std_logic;
signal mreq : std_logic;
signal iorq : std_logic;
signal mreq : std_logic;
signal m1 : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal a : std_logic_vector(15 downto 0);
signal d : std_logic_vector( 7 downto 0);
signal dcpu : std_logic_vector( 7 downto 0);
--
signal ear : std_logic;
signal mic : std_logic;
signal speaker : std_logic;
signal keycols : std_logic_vector( 4 downto 0);
signal va : std_logic_vector(12 downto 0);
signal vd : std_logic_vector( 7 downto 0);
signal dula : std_logic_vector( 7 downto 0);
signal dcpu : std_logic_vector( 7 downto 0);
--
signal erom : std_logic;
signal drom : std_logic_vector( 7 downto 0);
signal dloram : std_logic_vector( 7 downto 0);
--
signal eloram : std_logic;
signal wloram : std_logic;
signal dloram : std_logic_vector( 7 downto 0);
--
signal ehiram : std_logic;
signal whiram : std_logic;
signal dhiram : std_logic_vector( 7 downto 0);
--
signal kempston : std_logic_vector( 7 downto 0);
begin
@ -61,6 +88,10 @@ begin
int => int,
va => va,
vd => vd,
keycols => keycols,
ear => audioEAR,
mic => mic,
speaker => speaker,
hs => videoH,
vs => videoV,
rgb(11 downto 8) => videoR,
@ -77,10 +108,10 @@ begin
busrq_n => '1',
mreq_n => mreq,
iorq_n => iorq,
rfsh_n => open,
rd_n => rd,
wr_n => wr,
m1_n => m1,
rfsh_n => open,
halt_n => open,
busak_n => open,
a => a,
@ -90,12 +121,14 @@ begin
Urom: entity work.rom port map
(
clka => clock4,
ena => erom,
addra => a(13 downto 0),
douta => drom
);
Uloram: entity work.loram port map
(
clka => clock4,
ena => eloram,
wea(0) => wloram,
addra => a(13 downto 0),
dina => dcpu,
@ -107,15 +140,54 @@ begin
dinb => (others => '0'),
doutb => vd
);
Uhiram: entity work.hiram port map
(
clka => clock4,
ena => ehiram,
wea(0) => whiram,
addra => a(14 downto 0),
dina => dcpu,
douta => dhiram
);
Ukeyboard: entity work.keyboard port map
(
clock => clock4,
ps2c => ps2CLK,
ps2d => ps2DAT,
rows => a(15 downto 8),
cols => keycols
);
Umixer: entity work.mixer port map
(
clock => clock4,
speaker => speaker,
ear => audioEAR,
mic => mic,
l => audioL,
r => audioR
);
reset <= not netRST;
nmi <= not netNMI;
wloram <= '1' when mreq = '0' and wr = '0' and a(15 downto 14) = "01" else '0';
erom <= '1' when mreq = '0' and a(15 downto 14) = "00" else '0';
d <= dula when iorq = '0' and rd = '0' and a(0) = '0'
else drom when mreq = '0' and rd = '0' and a(15 downto 14) = "00"
else dloram when mreq = '0' and rd = '0' and a(15 downto 14) = "01"
else (others => '1');
eloram <= '1' when mreq = '0' and a(15 downto 14) = "01" else '0';
wloram <= not wr;
ehiram <= '1' when mreq = '0' and a(15) = '1' else '0';
whiram <= not wr;
d <= dula when iorq = '0' and rd = '0' and a(0) = '0'
else kempston when iorq = '0' and rd = '0' and a(7 downto 5) = "000"
else drom when erom = '1' and rd = '0'
else dloram when eloram = '1' and rd = '0'
else dhiram when ehiram = '1' and rd = '0'
else (others => '1');
audioGND <= '0';
joyGND <= '0';
kempston <= not ("111"&joyBTN(4)&joyBTN(0)&joyBTN(1)&joyBTN(2)&joyBTN(3));
end;

2
cores/KypSpectrum/zxpp.xst
View File

@ -1,4 +1,4 @@
set -tmpdir "projnav.tmp"
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn zxpp.prj