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Intercambio puertos de joystick

This commit is contained in:
antoniovillena 2021-09-01 10:24:37 +02:00
parent 0b68724110
commit 70e2193293
19 changed files with 1343 additions and 1224 deletions
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BIN
cores/MasterSystem/CORE6.ZX1
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Binary file not shown.

61
cores/MasterSystem/sms.prj
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@ -1,31 +1,30 @@
vhdl work "src/vdp_sprite_shifter.vhd"
vhdl work "T80/T80_Reg.vhd"
vhdl work "T80/T80_Pack.vhd"
vhdl work "T80/T80_MCode.vhd"
vhdl work "T80/T80_ALU.vhd"
vhdl work "src/vdp_vram_fill.vhd"
vhdl work "src/vdp_sprites.vhd"
vhdl work "src/vdp_background.vhd"
vhdl work "T80/T80.vhd"
vhdl work "src/vdp_vram.vhd"
vhdl work "src/vdp_main.vhd"
vhdl work "src/vdp_cram.vhd"
vhdl work "src/psg_tone.vhd"
vhdl work "src/psg_noise.vhd"
vhdl work "src/keyb/ps2_intf.vhd"
vhdl work "src/dac.vhd"
vhdl work "T80/T80se.vhd"
vhdl work "src/vdp.vhd"
vhdl work "src/spi.vhd"
vhdl work "src/ram.vhd"
vhdl work "src/psg.vhd"
verilog work "src/multiboot_v4.v"
vhdl work "src/keyb/keyboard.vhd"
vhdl work "src/io.vhd"
vhdl work "src/bootrom_fill.vhd"
vhdl work "src/vga_video.vhd"
vhdl work "src/system.vhd"
vhdl work "src/rgb_video.vhd"
vhdl work "src/dvi-d/dvid.vhd"
vhdl work "src/clocks.vhd"
vhdl work "src/sms.vhd"
vhdl work "src/vdp_sprite_shifter.vhd"
vhdl work "T80/T80_Reg.vhd"
vhdl work "T80/T80_Pack.vhd"
vhdl work "T80/T80_MCode.vhd"
vhdl work "T80/T80_ALU.vhd"
vhdl work "src/vdp_vram_fill.vhd"
vhdl work "src/vdp_sprites.vhd"
vhdl work "src/vdp_background.vhd"
vhdl work "T80/T80.vhd"
vhdl work "src/vdp_vram.vhd"
vhdl work "src/vdp_main.vhd"
vhdl work "src/vdp_cram.vhd"
vhdl work "src/psg_tone.vhd"
vhdl work "src/psg_noise.vhd"
vhdl work "src/keyb/ps2_intf.vhd"
vhdl work "src/dac.vhd"
vhdl work "T80/T80se.vhd"
vhdl work "src/vdp.vhd"
verilog work "src/sprom.v"
vhdl work "src/spi.vhd"
vhdl work "src/ram.vhd"
vhdl work "src/psg.vhd"
verilog work "src/multiboot_v4.v"
vhdl work "src/keyb/keyboard.vhd"
vhdl work "src/io.vhd"
vhdl work "src/vga_video.vhd"
vhdl work "src/system.vhd"
vhdl work "src/rgb_video.vhd"
vhdl work "src/clocks.vhd"
vhdl work "src/sms.vhd"

63
cores/MasterSystem/sms.ut
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@ -1,32 +1,31 @@
-w
-g DebugBitstream:No
-g Compress
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:Yes
-g ExtMasterCclk_divide:50
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:Yes
-g ExtMasterCclk_divide:50
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

104
cores/MasterSystem/sms.xst
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@ -1,52 +1,52 @@
set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn sms.prj
-ofn sms
-ofmt NGC
-p xc6slx9-3-tqg144
-top sms
-opt_mode Speed
-opt_level 1
-power NO
-iuc YES
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn sms.prj
-ofn sms
-ofmt NGC
-p xc6slx9-2-tqg144
-top sms
-opt_mode Speed
-opt_level 1
-power NO
-iuc YES
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

52
cores/MasterSystem/src/bootrom_fill.vhd
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@ -1,24 +1,24 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
entity boot_rom is
use std.textio.all;
entity boot_rom0 is
generic (
ADDR_WIDTH : integer := 14;
DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
RD_n : in std_logic;
A : in std_logic_vector(13 downto 0);
D_out : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of boot_rom is
);
port (
clk : in std_logic;
RD_n : in std_logic;
A : in std_logic_vector(13 downto 0);
D_out : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of boot_rom0 is
constant MEM_DEPTH : integer := 2**ADDR_WIDTH;
type mem_type is array (0 to MEM_DEPTH-1) of signed(DATA_WIDTH-1 downto 0);
@ -41,12 +41,12 @@ architecture RTL of boot_rom is
begin
p_rom : process
begin
wait until rising_edge(clk);
if (RD_n = '0') then --1
D_out <= std_logic_vector(mem(to_integer(unsigned(A))));
end if;
end process;
end RTL;
p_rom : process
begin
wait until rising_edge(clk);
if (RD_n = '0') then --1
D_out <= std_logic_vector(mem(to_integer(unsigned(A))));
end if;
end process;
end RTL;

285
cores/MasterSystem/src/clocks.vhd
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@ -1,133 +1,152 @@
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 50.000 0.010
-- Generador relojes PLL para el in de 50Mhz del ZX-UNO
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
clk_in : in std_logic;
sel_pclock : in std_logic;
-- Clock out ports
clk8 : out std_logic;
clk16 : out std_logic;
clk_cpu : out std_logic;
clk32 : out std_logic;
pclock : out std_logic
);
end clock;
architecture behavioral of clock is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clk_in);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 100, --25 = 32Mhz, --100 = 8Mhz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 50, --50 = 16MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 27, --27 ~29.5Mhz Z80 --100 = 8mhz --50 = 16mhz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 25, --25 = 32Mhz for HDMI clock
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.0,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk8,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk16,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk_cpu,
I => clkout2);
clkout4_buf : BUFG
port map
(O => clk32,
I => clkout3);
pclock_sel : BUFGMUX --muxer del relojes 16 / 8 para el pixel clock del scandoubler on/off
port map
(O => pclock,
I0 => clkout0, --el de 8
I1 => clkout1, --el de 16
S => sel_pclock);
end behavioral;
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 50.000 0.010
-- Generador relojes PLL para el in de 50Mhz del ZX-UNO
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
clk_in : in std_logic;
sel_pclock : in std_logic;
sel_cpu : in std_logic;
-- Clock out ports
clk8 : out std_logic;
clk16 : out std_logic;
clk_cpu : out std_logic;
-- clk32 : out std_logic;
pclock : out std_logic;
cpu_pclock : out std_logic
);
end clock;
architecture behavioral of clock is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clk357 : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clk_in);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 100, --25 = 32Mhz, --100 = 8Mhz --1120 = 7,12Mhz (/2 = 3,57)
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 50, --50 = 16MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 25, --27 ~29.5Mhz Z80 --100 = 8mhz --50 = 16mhz --32 = 25Mhz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DIVIDE => 112, --25 = 32Mhz for HDMI clock
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.0,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk8,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk16,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk_cpu,
I => clkout2);
-- clkout4_buf : BUFG
-- port map
-- (O => clk32,
-- I => clkout3);
pclock_sel : BUFGMUX --muxer del relojes 16 / 8 para el pixel clock del scandoubler on/off
port map
(O => pclock,
I0 => clkout0, --el de 8
I1 => clkout1, --el de 16
S => sel_pclock);
pclock_sel_cpu : BUFGMUX --muxer del relojes 32 / 8 para el cambio de cpu (32 = loader/SD)
port map
(O => cpu_pclock,
I0 => clkout1,
I1 => clkout2, --el de 32
S => sel_cpu);
-- process (clkout3)
-- begin
-- if rising_edge(clkout3) then
-- clk357 <= not clk357;
-- end if;
-- end process;
end behavioral;

2
cores/MasterSystem/src/io.vhd
View File

@ -74,7 +74,7 @@ begin
D_out(6) <= '0';
end if;
D_out(5) <= '1';
D_out(4) <= RESET; --Q
D_out(4) <= RESET; --Q
-- D_out(4) <= '1';
-- 4=j2_tr
if ctrl(2)='0' then

124
cores/MasterSystem/src/keyb/keyboard.vhd
View File

@ -11,9 +11,9 @@ port (
CLOCK : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
resetKey : out std_logic;
resetKey : out std_logic;
MRESET : out std_logic;
scanSW : out std_logic_vector(7 downto 0)
scanSW : out std_logic_vector(9 downto 0)
);
end entity;
@ -34,7 +34,7 @@ port(
-- so must be latched externally if required
DATA : out std_logic_vector(7 downto 0);
VALID : out std_logic
-- ;ERROR : out std_logic
-- ;ERROR : out std_logic
);
end component;
@ -45,14 +45,16 @@ signal keyb_valid : std_logic;
-- Internal signals
signal release : std_logic;
--signal extended : std_logic;
signal nRESET : std_logic;
-- controles
signal CTRL : std_logic;
signal ALT : std_logic;
signal PAUSE: std_logic := '0';
signal VIDEO: std_logic := '0';
--signal extended : std_logic;
signal nRESET : std_logic;
-- controles
signal CTRL : std_logic;
signal ALT : std_logic;
signal PAUSE: std_logic := '0';
signal VIDEO: std_logic := '0';
signal SCANL: std_logic := '0';
signal VFREQ: std_logic := '0';
begin
@ -87,48 +89,66 @@ begin
-- Decode scan codes
case keyb_data is
--Master reset
when X"66" =>
if (CTRL = '1' and ALT = '1') then
MRESET <= not release;
end if;
when X"14" => CTRL <= not release;
--Master reset
when X"66" =>
if (CTRL = '1' and ALT = '1') then
MRESET <= not release;
end if;
when X"14" => CTRL <= not release;
when X"11" => ALT <= not release;
when X"07" => resetKey <= not release; -- F12 reset/menu
when X"75" => scanSW(0) <= not release; --up + q
when X"15" => scanSW(0) <= not release;
when X"72" => scanSW(1) <= not release; --down + a
when X"1C" => scanSW(1) <= not release;
when X"6B" => scanSW(2) <= not release; --left + o
when X"44" => scanSW(2) <= not release;
when X"74" => scanSW(3) <= not release; --right + p
when X"4D" => scanSW(3) <= not release;
when X"1A" => scanSW(4) <= not release; --bl = z, enter, space
when X"5A" => scanSW(4) <= not release;
when X"29" => scanSW(4) <= not release;
when X"22" => scanSW(5) <= not release; --br = x, L-win
when X"1F" => scanSW(5) <= not release;
when X"7E" => -- scrolLock RGB/VGA
if (VIDEO = '0' and release = '0') then
scanSW(6) <= '1';
VIDEO <= '1';
elsif (VIDEO = '1' and release = '0') then
scanSW(6) <= '0';
VIDEO <= '0';
end if;
when X"E1" => -- pause
if (PAUSE = '0') then
scanSW(7) <= '1';
PAUSE <= '1';
else
scanSW(7) <= '0';
PAUSE <= '0';
end if;
when X"07" => resetKey <= not release; -- F12 reset/menu
when X"75" => scanSW(0) <= not release; --up + q
when X"15" => scanSW(0) <= not release;
when X"72" => scanSW(1) <= not release; --down + a
when X"1C" => scanSW(1) <= not release;
when X"6B" => scanSW(2) <= not release; --left + o
when X"44" => scanSW(2) <= not release;
when X"74" => scanSW(3) <= not release; --right + p
when X"4D" => scanSW(3) <= not release;
when X"1A" => scanSW(4) <= not release; --bl = z, enter, space
when X"5A" => scanSW(4) <= not release;
when X"29" => scanSW(4) <= not release;
when X"22" => scanSW(5) <= not release; --br = x, L-win
when X"1F" => scanSW(5) <= not release;
when X"7E" => -- scrolLock RGB/VGA
if (VIDEO = '0' and release = '0') then
scanSW(6) <= '1';
VIDEO <= '1';
elsif (VIDEO = '1' and release = '0') then
scanSW(6) <= '0';
VIDEO <= '0';
end if;
when X"E1" => -- pause
if (PAUSE = '0') then
scanSW(7) <= '1';
PAUSE <= '1';
else
scanSW(7) <= '0';
PAUSE <= '0';
end if;
when X"7B" => -- scanlines ("-" numpad)
if (SCANL = '0' and release = '0') then
scanSW(8) <= '1';
SCANL <= '1';
elsif (SCANL = '1' and release = '0') then
scanSW(8) <= '0';
SCANL <= '0';
end if;
when X"7C" => -- vertical freq 50/60Hz ("*" numpad)
if (VFREQ = '0' and release = '0') then
scanSW(9) <= '1';
VFREQ <= '1';
elsif (VFREQ = '1' and release = '0') then
scanSW(9) <= '0';
VFREQ <= '0';
end if;
when others => null;
end case;
@ -137,7 +157,7 @@ begin
end if;
end if;
end process;
nRESET <= '1';
nRESET <= '1';
end architecture;

2
cores/MasterSystem/src/keyb/ps2_intf.vhd
View File

@ -34,7 +34,7 @@
--
-- PS/2 interface (input only)
-- Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com
-- Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

2
cores/MasterSystem/src/psg.vhd
View File

@ -82,7 +82,7 @@ begin
inst_dac: dac
port map (
clk => clk, --clk32
clk => clk, --clk32
input => outputs,
output => output );

45
cores/MasterSystem/src/rgb_video.vhd
View File

@ -4,7 +4,7 @@ use IEEE.NUMERIC_STD.ALL;
entity rgb_video is
port (
clk16: in std_logic;
clk16: in std_logic;
clk8: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
@ -15,8 +15,8 @@ entity rgb_video is
vsync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 0)
-- ; blank: out std_logic
blue: out std_logic_vector(2 downto 0);
vfreq: in std_logic
);
end rgb_video;
@ -26,21 +26,31 @@ architecture Behavioral of rgb_video is
signal vcount: unsigned (8 downto 0) := (others=>'0');
signal visible: boolean;
signal y9: unsigned (8 downto 0);
signal y9: unsigned (8 downto 0);
signal in_vbl: std_logic;
signal screen_sync: std_logic;
signal vbl_sync: std_logic;
signal vbl_sync: std_logic;
signal hcount_max: integer range 0 to 1023;
signal vcount_max: integer range 0 to 1023;
signal ypos: integer range 0 to 64;
signal vis_vc: integer range 0 to 512;
begin
begin
hcount_max <= 511 when vfreq = '0' else 507;
vcount_max <= 311 when vfreq = '0' else 261;
ypos <= 70 when vfreq = '0' else 40;
vis_vc <= 302 when vfreq = '0' else 255;
process (clk8)
begin
if rising_edge(clk8) then
if hcount=511 then
if hcount=hcount_max then --511 PAL / 507 NTSC
hcount <= (others => '0');
if vcount=311 then --PAL = 311 / NTSC = 261
if vcount=vcount_max then --PAL = 311 / NTSC = 261
vcount <= (others=>'0');
else
vcount <= vcount + 1;
@ -51,8 +61,9 @@ begin
end if;
end process;
visible <= vcount>=35 and vcount<302 and hcount>=91 and hcount<509-38;
--PAL = 302, NTSC = 255
-- visible <= vcount>=35 and vcount<302 and hcount>=91 and hcount<509-38;
visible <= vcount>=35 and vcount<vis_vc and hcount>=91 and hcount<509-38;
--PAL = 302, NTSC = 255
process (hcount)
begin
if hcount<38 then
@ -65,7 +76,7 @@ begin
in_vbl <= '1' when vcount<9 else '0';
x <= hcount-151;
y9 <= vcount-70; --PAL = -70 , NTSC = -40
y9 <= vcount-ypos; --PAL = -70 , NTSC = -40
y <= y9(7 downto 0);
vblank <= '1' when hcount=0 and vcount=0 else '0';
hblank <= '1' when hcount=0 else '0';
@ -97,21 +108,21 @@ begin
hsync <= screen_sync;
end if;
end process;
vsync <= '1';
process (clk16)
process (clk8) --clk16
begin
if rising_edge(clk16) then
if rising_edge(clk8) then --clk16
if visible then
red <= color(1 downto 0) & color(1); --Q & color;
green <= color(3 downto 2) & color(3); --Q & color;
blue <= color(5 downto 4) & color(4); --Q & color;
blue <= color(5 downto 4) & color(4); --Q & color;
-- blank <= '0';
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
blue <= (others=>'0');
-- blank <= '1';
end if;
end if;

463
cores/MasterSystem/src/sms.vhd
View File

@ -1,22 +1,34 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sms is
port (
clk: in STD_LOGIC;
sram_we_n: out STD_LOGIC;
sram_a: out STD_LOGIC_VECTOR(18 downto 0);
sram_a: out STD_LOGIC_VECTOR(20 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
-- j1_MDsel: out STD_LOGIC; --Q
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: inout STD_LOGIC;
j1_tr: inout STD_LOGIC;
j1_fire3: out STD_LOGIC;
j2_up: in STD_LOGIC;
j2_down: in STD_LOGIC;
j2_left: in STD_LOGIC;
j2_right: in STD_LOGIC;
j2_tl: in STD_LOGIC;
j2_tr: inout STD_LOGIC;
SW1: in STD_LOGIC;
SW2: in STD_LOGIC;
audio_l: out STD_LOGIC;
audio_r: out STD_LOGIC;
@ -27,169 +39,107 @@ entity sms is
hsync: buffer STD_LOGIC;
vsync: buffer STD_LOGIC;
dred: out STD_LOGIC_VECTOR(2 downto 0);
dgreen: out STD_LOGIC_VECTOR(2 downto 0);
dblue: out STD_LOGIC_VECTOR(2 downto 0);
dhsync: out STD_LOGIC;
dvsync: out STD_LOGIC;
spi_do: in STD_LOGIC;
spi_sclk: out STD_LOGIC;
spi_di: out STD_LOGIC;
spi_cs_n: buffer STD_LOGIC;
led: out STD_LOGIC;
led: out STD_LOGIC;
ps2_clk: in std_logic;
ps2_data: in std_logic;
NTSC: out std_logic; --Q
PAL: out std_logic --Q
ps2_data: in std_logic;
NTSC: out std_logic;
PAL: out std_logic
-- ;hdmi_out_p: out std_logic_vector(3 downto 0);
-- hdmi_out_n: out std_logic_vector(3 downto 0)
);
end sms;
architecture Behavioral of sms is
architecture Behavioral of sms is
-- Cambiar segun tipo de placa/opción joysticks
-- JoyType: 0 = un Joy. 1 = dos Joys
constant JoyType : integer := 1;
component clock is
port (
clk_in: in std_logic;
sel_pclock: in std_logic;
clk_cpu: out std_logic;
clk16: out std_logic;
clk8: out std_logic;
clk32: out std_logic;
pclock: out std_logic);
end component;
component system is
port (
clk_cpu: in STD_LOGIC;
clk_vdp: in STD_LOGIC;
ram_we_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0);
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: inout STD_LOGIC;
j2_up: in STD_LOGIC;
j2_down: in STD_LOGIC;
j2_left: in STD_LOGIC;
j2_right: in STD_LOGIC;
j2_tl: in STD_LOGIC;
j2_tr: inout STD_LOGIC;
reset: in STD_LOGIC;
-- pause: in STD_LOGIC;
x: in UNSIGNED(8 downto 0);
y: in UNSIGNED(7 downto 0);
-- vblank: in STD_LOGIC;
-- hblank: in STD_LOGIC;
color: out STD_LOGIC_VECTOR(5 downto 0);
audio: out STD_LOGIC;
ps2_clk: in std_logic;
ps2_data: in std_logic;
scanSW: out std_logic;
spi_do: in STD_LOGIC;
spi_sclk: out STD_LOGIC;
spi_di: out STD_LOGIC;
spi_cs_n: buffer STD_LOGIC
);
end component;
component rgb_video is
port (
clk16: in std_logic;
clk8: in std_logic; --Q
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
vblank: out std_logic;
hblank: out std_logic;
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 0)
-- ; blank: out std_logic
);
end component;
signal clk_cpu: std_logic;
signal clk16: std_logic;
signal clk8: std_logic;
signal clk32: std_logic;
signal sel_pclock: std_logic;
signal blank: std_logic;
-- signal blankr: std_logic;
signal clk16: std_logic;
signal clk8: std_logic;
signal clk32: std_logic;
signal cpu_pclock: std_logic;
signal sel_pclock: std_logic;
signal sel_cpu: std_logic;
signal blank: std_logic;
-- signal blankr: std_logic;
signal x: unsigned(8 downto 0);
signal y: unsigned(7 downto 0);
signal vblank: std_logic;
signal hblank: std_logic;
signal color: std_logic_vector(5 downto 0);
signal audio: std_logic;
signal vga_hsync: std_logic;
signal vga_vsync: std_logic;
signal vga_red: std_logic_vector(2 downto 0);
signal vga_green: std_logic_vector(2 downto 0);
signal vga_blue: std_logic_vector(2 downto 0);
signal vga_x: unsigned(8 downto 0);
signal vga_y: unsigned(7 downto 0);
signal vga_vblank: std_logic;
signal vga_hblank: std_logic;
signal rgb_hsync: std_logic;
signal rgb_vsync: std_logic;
signal rgb_red: std_logic_vector(2 downto 0);
signal rgb_green: std_logic_vector(2 downto 0);
signal rgb_blue: std_logic_vector(2 downto 0);
signal rgb_x: unsigned(8 downto 0);
signal rgb_y: unsigned(7 downto 0);
signal rgb_vblank: std_logic;
signal rgb_hblank: std_logic;
signal rgb_clk: std_logic;
signal scanSWk: std_logic;
signal scanSW: std_logic;
signal j2_tr: std_logic;
signal c0, c1, c2 : std_logic_vector(9 downto 0); --hdmi
signal poweron_reset: unsigned(7 downto 0) := "00000000";
signal scandoubler_ctrl: std_logic_vector(1 downto 0);
signal ram_we_n: std_logic;
signal ram_a: std_logic_vector(18 downto 0);
signal audio: std_logic;
signal vga_hsync: std_logic;
signal vga_vsync: std_logic;
signal vga_red: std_logic_vector(2 downto 0);
signal vga_green: std_logic_vector(2 downto 0);
signal vga_blue: std_logic_vector(2 downto 0);
signal vga_x: unsigned(8 downto 0);
signal vga_y: unsigned(7 downto 0);
signal vga_vblank: std_logic;
signal vga_hblank: std_logic;
signal rgb_hsync: std_logic;
signal rgb_vsync: std_logic;
signal rgb_red: std_logic_vector(2 downto 0);
signal rgb_green: std_logic_vector(2 downto 0);
signal rgb_blue: std_logic_vector(2 downto 0);
signal rgb_x: unsigned(8 downto 0);
signal rgb_y: unsigned(7 downto 0);
signal rgb_vblank: std_logic;
signal rgb_hblank: std_logic;
signal rgb_clk: std_logic;
signal scanSWk: std_logic;
signal scanSW: std_logic;
signal scanL: std_logic;
signal vfreQ: std_logic;
signal poweron_reset: unsigned(7 downto 0) := "00000000";
signal scandoubler_ctrl: std_logic_vector(1 downto 0);
signal ram_we_n: std_logic;
signal ram_a: std_logic_vector(19 downto 0);
signal joy1: std_logic_vector(5 downto 0);
signal joy2: std_logic_vector(5 downto 0);
signal joy_mux: std_logic_vector(16 downto 0);
signal j1_f3: std_logic;
signal ePause: std_logic;
signal eReset: std_logic;
signal pwon: std_logic;
begin
clock_inst: clock
clock_inst: entity work.clock
port map (
clk_in => clk,
sel_pclock => sel_pclock,
clk_cpu => clk_cpu,
clk16 => clk16,
clk8 => clk8, --clk32 => open
clk32 => clk32,
pclock => rgb_clk);
video_inst: rgb_video
clk_in => clk,
sel_pclock => sel_pclock,
sel_cpu => sel_cpu,
clk8 => clk8,
clk16 => clk16,
clk_cpu => clk32,
pclock => rgb_clk,
cpu_pclock => cpu_pclock
);
video_inst: entity work.rgb_video
port map (
clk16 => clk16,
clk8 => clk8, --Q
clk8 => clk8, --Q
x => rgb_x,
y => rgb_y,
vblank => rgb_vblank,
@ -199,120 +149,171 @@ begin
vsync => rgb_vsync,
red => rgb_red,
green => rgb_green,
blue => rgb_blue
-- ,blank => blankr
);
blue => rgb_blue,
vfreq => vfreQ
);
video_vga_inst: entity work.vga_video --vga
port map (
clk16 => clk16,
x => vga_x,
y => vga_y,
vblank => vga_vblank,
hblank => vga_hblank,
-- vblank => vga_vblank,
-- hblank => vga_hblank,
color => color,
hsync => vga_hsync,
vsync => vga_vsync,
red => vga_red,
green => vga_green,
blue => vga_blue,
blank => blank
blue => vga_blue,
blank => blank,
scanlines => scandoubler_ctrl(1) xor scanL,
vfreq => vfreQ
);
system_inst: system
JT1 : if (JoyType = 1) generate
j1_fire3 <= j1_f3;
process (j1_f3)
begin
if j1_f3 = '0' then
joy2 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
else
joy1 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
end if;
end process;
process (clk32)
begin
if rising_edge(clk32) then
j1_f3 <= joy_mux(16);
joy_mux <= joy_mux + 1;
end if;
end process;
ePause <= '1';
eReset <= '1';
end generate JT1;
JT0 : if (JoyType = 0) generate
joy1 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
joy2 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
ePause <= '1';
eReset <= '1';
j1_fire3 <= '0';
end generate JT0;
system_inst: entity work.system
port map (
clk_cpu => clk_cpu, --clk_cpu
clk_vdp => rgb_clk, --clk8 = rgb --clk16 = vga
clk_cpu => cpu_pclock, --cpu_pclock, --clk_cpu
clk_vdp => rgb_clk, --rgb_clk, --clk8 = rgb --clk16 = vga
clk32 => clk32,
ram_we_n => ram_we_n,
ram_a => ram_a,
ram_d => ram_d,
j1_up => j1_up,
j1_down => j1_down,
j1_left => j1_left,
j1_right => j1_right,
j1_tl => j1_tl,
j1_tr => j1_tr,
j2_up => '1',
j2_down => '1',
j2_left => '1',
j2_right => '1',
j2_tl => '1',
j2_tr => j2_tr,
reset => '1',
-- pause => '1',
j1_up => joy1(5), --j1_up,
j1_down => joy1(4), --j1_down,
j1_left => joy1(3), --j1_left,
j1_right => joy1(2), --j1_right,
j1_tl => joy1(1), --j1_tl,
j1_tr => joy1(0), --j1_tr,
j2_up => joy2(5), --'1',
j2_down => joy2(4), --'1',
j2_left => joy2(3), --'1',
j2_right => joy2(2), --'1',
j2_tl => joy2(1), --'1',
j2_tr => joy2(0), --j2_tr,
reset => eReset,
pause => ePause,
x => x,
y => y,
-- vblank => vblank,
-- hblank => hblank,
color => color,
audio => audio,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
scanSW => scanSWk,
audio => audio,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
scanSW => scanSWk,
scanL => scanL,
vfreQ => vfreQ,
spi_do => spi_do,
spi_sclk => spi_sclk,
spi_di => spi_di,
spi_cs_n => spi_cs_n
);
dred <= red;
dgreen <= green;
dblue <= blue;
dhsync <= hsync;
dvsync <= vsync;
led <= not spi_cs_n; --Q
-- led <= scandoubler_ctrl(0); --debug scandblctrl reg.
spi_cs_n => spi_cs_n,
sel_cpu => sel_cpu
);
led <= not spi_cs_n; --Q
-- led <= scandoubler_ctrl(0); --debug scandblctrl reg.
audio_l <= audio;
audio_r <= audio;
audio_r <= audio;
NTSC <= vfreQ;
PAL <= not vfreQ;
---- scandlbctrl register detection for video mode initialization at start ----
process (clk32)
begin
if rising_edge(clk32) then
if (poweron_reset < 90) then
scandoubler_ctrl <= ram_d(1 downto 0);
end if;
if poweron_reset < 254 then
poweron_reset <= poweron_reset + 1;
end if;
end if;
end process;
sram_a(20) <= '0';
sram_a(19 downto 0) <= "00001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
pwon <= '1' when poweron_reset < 254 else '0';
-------------------------------------------------------------------------------
vsync <= vga_vsync when scanSW='1' else '1';
hsync <= vga_hsync when scanSW='1' else rgb_hsync;
red <= vga_red when scanSW='1' else rgb_red;
green <= vga_green when scanSW='1' else rgb_green;
blue <= vga_blue when scanSW='1' else rgb_blue;
-- vblank <= vga_vblank when scanSW='1' else rgb_vblank;
-- hblank <= vga_hblank when scanSW='1' else rgb_hblank;
x <= vga_x when scanSW='1' else rgb_x;
y <= vga_y when scanSW='1' else rgb_y;
sel_pclock <= '1' when scanSW='1' else '0';
-- scanSW <= '1' when scanSWk = '1' else '0';
scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
--HDMI
--Inst_MinimalDVID_encoder: entity work.MinimalDVID_encoder PORT MAP(
-- clk => clk32,
-- blank => blank,
-- hsync => hsync,
-- vsync => vsync,
-- red => red,
-- green => green,
-- blue => blue,
-- hdmi_p => hdmi_out_p,
-- hdmi_n => hdmi_out_n
-- );
NTSC <= '0';
PAL <= '1';
---- scandlbctrl register detection for video mode initialization at start ----
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if (poweron_reset < 126) then
scandoubler_ctrl <= ram_d(1 downto 0);
end if;
if poweron_reset < 254 then
poweron_reset <= poweron_reset + 1;
end if;
end if;
end process;
sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
-------------------------------------------------------------------------------
vsync <= vga_vsync when scanSW='1' else '1';
hsync <= vga_hsync when scanSW='1' else rgb_hsync;
red <= vga_red when scanSW='1' else rgb_red;
green <= vga_green when scanSW='1' else rgb_green;
blue <= vga_blue when scanSW='1' else rgb_blue;
-- vblank <= vga_vblank when scanSW='1' else rgb_vblank;
-- hblank <= vga_hblank when scanSW='1' else rgb_hblank;
x <= vga_x when scanSW='1' else rgb_x;
y <= vga_y when scanSW='1' else rgb_y;
sel_pclock <= '1' when scanSW='1' else '0';
-- scanSW <= '1' when scanSWk = '1' else '0';
scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
end Behavioral;

175
cores/MasterSystem/src/sms_zxuno_v4.ucf
View File

@ -1,100 +1,101 @@
#UCF para el ZX-UNO v4
NET "CLK" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
NET "led" LOC="P11" | IOSTANDARD = LVCMOS33;
NET "CLK" PERIOD=20 ns;
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
# Video output
NET "red(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "NTSC" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "PAL" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "led" LOC="P11" | IOSTANDARD=LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "j1_tr" LOC="P8" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
###JoySplitter AV optional J16
NET "j1_fire3" LOC="P39" | IOSTANDARD=LVCMOS33;
##--##
# Keyboard and mouse
NET "ps2_clk" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ps2_data" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
###Jamma addon / MFH 2M##
NET "j2_up" LOC="P26" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j2_down" LOC="P30" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j2_left" LOC="P34" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j2_right" LOC="P41" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j2_tl" LOC="P47" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j2_tr" LOC="P46" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "SW1" LOC="P56" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "SW2" LOC="P15" | IOSTANDARD=LVCMOS33 | PULLUP;
## -- ##
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
# SRAM
NET "sram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "ram_d<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "ram_d<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "ram_d<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "audio_l" LOC="P10" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET "sram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
NET "sram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
NET "sram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "ram_d<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "ram_d<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "ram_d<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
NET dred(2) LOC="P51" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dred(1) LOC="P50" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dred(0) LOC="P47" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dgreen(2) LOC="P40" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dgreen(1) LOC="P35" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dgreen(0) LOC="P33" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dblue(2) LOC="P23" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dblue(1) LOC="P17" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dblue(0) LOC="P24" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dhsync LOC="P57" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET dvsync LOC="P58" | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
NET "NTSC" LOC="P66" | IOSTANDARD=LVCMOS33;
NET "PAL" LOC="P67" | IOSTANDARD=LVCMOS33;
NET "ps2_data" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "ps2_clk" LOC="P99" | IOSTANDARD=LVCMOS33 | PULLUP;
#NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
#NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";

1040
cores/MasterSystem/src/system.vhd
View File

File diff suppressed because it is too large Load Diff

32
cores/MasterSystem/src/vdp.vhd
View File

@ -15,7 +15,7 @@ entity vdp is
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
-- vblank: std_logic;
-- hblank: std_logic;
-- hblank: std_logic;
RST_vram: in std_logic;
color: out std_logic_vector (5 downto 0));
end vdp;
@ -59,8 +59,8 @@ architecture Behavioral of vdp is
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
; RST_vram: in std_logic
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
; RST_vram: in std_logic
);
end component;
@ -73,8 +73,8 @@ architecture Behavioral of vdp is
vdp_clk: in STD_LOGIC;
vdp_A: in std_logic_vector(4 downto 0);
vdp_D: out std_logic_vector(5 downto 0));
end component;
end component;
-- helper bits
signal data_write: std_logic;
signal address_ff: std_logic := '0';
@ -91,7 +91,7 @@ architecture Behavioral of vdp is
signal vram_vdp_A: std_logic_vector(13 downto 0);
signal vram_vdp_D: std_logic_vector(7 downto 0);
signal cram_vdp_A: std_logic_vector(4 downto 0);
signal cram_vdp_D: std_logic_vector(5 downto 0);
signal cram_vdp_D: std_logic_vector(5 downto 0);
-- control bits
signal display_on: std_logic := '1';
@ -116,7 +116,7 @@ architecture Behavioral of vdp is
signal irq_counter: unsigned(4 downto 0) := (others=>'0');
signal hbl_counter: unsigned(7 downto 0) := (others=>'0');
signal vbl_irq: std_logic;
signal hbl_irq: std_logic;
signal hbl_irq: std_logic;
signal vbi_done: std_logic := '0';
begin
@ -156,8 +156,8 @@ begin
cpu_D_out => vram_cpu_D_out,
vdp_clk => vdp_clk,
vdp_A => vram_vdp_A,
vdp_D_out => vram_vdp_D
,RST_vram => RST_vram
vdp_D_out => vram_vdp_D
,RST_vram => RST_vram
);
vdp_cram_inst: vdp_cram
@ -168,8 +168,8 @@ begin
cpu_D => D_in(5 downto 0),
vdp_clk => vdp_clk,
vdp_A => cram_vdp_A,
vdp_D => cram_vdp_D);
vdp_D => cram_vdp_D);
data_write <= not WR_n and not A(0);
cram_cpu_WE <= data_write when to_cram else '0';
@ -223,7 +223,7 @@ begin
when "010" =>
-- D_out <= (others=>'0');
-- when "011" =>
-- D_out <= std_logic_vector(y);
-- D_out <= std_logic_vector(y);
D_out <= std_logic_vector(y);
when "011" =>
D_out <= std_logic_vector(x(7 downto 0));
@ -257,8 +257,8 @@ begin
-- vbl_irq <= '0';
-- end if;
-- end if;
-- end process;
-- end process;
process (vdp_clk) --q
begin
if rising_edge(vdp_clk) then
@ -275,8 +275,8 @@ begin
vbl_irq <= '0';
end if;
end if;
end process;
end process;
--
process (vdp_clk)

2
cores/MasterSystem/src/vdp_main.vhd
View File

@ -110,7 +110,7 @@ begin
vram_D => vram_D,
color => spr_color);
process (x, y, bg_priority, spr_color, bg_color, overscan)
process (x, y, bg_priority, spr_color, bg_color, overscan, mask_column0)
variable spr_active : boolean;
variable bg_active : boolean;
begin

48
cores/MasterSystem/src/vdp_vram.vhd
View File

@ -13,14 +13,14 @@ entity vdp_vram is
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
;RST_vram: in std_logic
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
;RST_vram: in std_logic
);
end vdp_vram;
architecture Behavioral of vdp_vram is
--Q --vram_fill
architecture Behavioral of vdp_vram is
--Q --vram_fill
component vdp_vram_fill is
port (
cpu_clk: in STD_LOGIC;
@ -30,16 +30,16 @@ architecture Behavioral of vdp_vram is
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
signal fcpu_D_in: std_logic_vector (7 downto 0);
signal scpu_D_out: std_logic_vector (7 downto 0);
signal svdp_D_out: std_logic_vector (7 downto 0);
signal fcpu_D_out: std_logic_vector (7 downto 0);
signal fvdp_D_out: std_logic_vector (7 downto 0);
signal fcpu_WE: std_logic;
end component;
signal fcpu_D_in: std_logic_vector (7 downto 0);
signal scpu_D_out: std_logic_vector (7 downto 0);
signal svdp_D_out: std_logic_vector (7 downto 0);
signal fcpu_D_out: std_logic_vector (7 downto 0);
signal fvdp_D_out: std_logic_vector (7 downto 0);
signal fcpu_WE: std_logic;
begin
ram_blocks:
@ -58,15 +58,15 @@ begin
CLKB => not vdp_clk,
ADDRB => vdp_A,
DIB => "0",
-- DOB => s_D_out(b downto b),
-- DOB => s_D_out(b downto b),
DOB => svdp_D_out(b downto b),
ENB => '1',
SSRB => '0',
WEB => '0'
);
end generate;
--Q --vram_fill
end generate;
--Q --vram_fill
vdp_vram_fill_inst: vdp_vram_fill
port map(
cpu_clk => cpu_clk,
@ -76,11 +76,11 @@ begin
cpu_D_out => fcpu_D_out,
vdp_clk => vdp_clk,
vdp_A => vdp_A,
vdp_D_out => fvdp_D_out
);
vdp_D_out <= fvdp_D_out when RST_vram='1' else svdp_D_out;
cpu_D_out <= fcpu_D_out when RST_vram='1' else scpu_D_out;
fcpu_WE <= cpu_WE when RST_vram='1' else '0';
vdp_D_out => fvdp_D_out
);
vdp_D_out <= fvdp_D_out when RST_vram='1' else svdp_D_out;
cpu_D_out <= fcpu_D_out when RST_vram='1' else scpu_D_out;
fcpu_WE <= cpu_WE when RST_vram='1' else '0';
end Behavioral;

2
cores/MasterSystem/src/vdp_vram_fill.vhd
View File

@ -13,7 +13,7 @@ entity vdp_vram_fill is
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
vdp_clk : in STD_LOGIC;
vdp_A : in STD_LOGIC_VECTOR (13 downto 0);
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
);
end vdp_vram_fill;

65
cores/MasterSystem/src/vga_video.vhd
View File

@ -14,8 +14,10 @@ entity vga_video is
vsync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 0)
; blank: out std_logic
blue: out std_logic_vector(2 downto 0);
blank: out std_logic;
scanlines: in std_logic;
vfreq: in std_logic
);
end vga_video;
@ -25,16 +27,24 @@ architecture Behavioral of vga_video is
signal vcount: unsigned (9 downto 0) := (others=>'0');
signal visible: boolean;
signal y9: unsigned (8 downto 0);
signal y9: unsigned (8 downto 0);
signal hcount_max: integer range 0 to 1023;
signal vcount_max: integer range 0 to 1023;
signal ypos: integer range 0 to 64;
begin
begin
hcount_max <= 511 when vfreq = '0' else 507;
vcount_max <= 622 when vfreq = '0' else 522;
ypos <= 55 when vfreq = '0' else 27;
process (clk16)
begin
if rising_edge(clk16) then
if hcount=511 then --507 = 60Hz , 511 = 50Hz
if hcount=hcount_max then --507 = 60Hz , 511 = 50Hz
hcount <= (others => '0');
if vcount=622 then --523 = 60Hz, 623 = 50Hz --622
if vcount=vcount_max then --523 = 60Hz, 623 = 50Hz --622
vcount <= (others=>'0');
else
vcount <= vcount + 1;
@ -46,8 +56,9 @@ begin
end process;
x <= hcount-(91+60); --62
-- y9 <= vcount(9 downto 1)-(13+27); --60Hz
y9 <= vcount(9 downto 1)-(13+55);
-- y9 <= vcount(9 downto 1)-(13+27); --60Hz
-- y9 <= vcount(9 downto 1)-(13+55); --50Hz
y9 <= vcount(9 downto 1)-(13+ypos); --var
y <= y9(7 downto 0);
hblank <= '1' when hcount=0 and vcount(0 downto 0)=0 else '0';
vblank <= '1' when hcount=0 and vcount=0 else '0';
@ -55,31 +66,41 @@ begin
hsync <= '0' when hcount<61 else '1';
vsync <= '0' when vcount<2 else '1';
-- visible <= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406; --60Hz
visible <= vcount>=35 and vcount<35+580 and hcount>=91 and hcount<91+406; --50Hz
-- visible <= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406; --60Hz
-- visible <= vcount>=35 and vcount<35+580 and hcount>=91 and hcount<91+406; --50Hz
visible <= vcount>=35 and vcount<35+vcount_max-42 and hcount>=91 and hcount<91+406; --var
process (clk16)
begin
if rising_edge(clk16) then
if visible then
red <= color(1 downto 0) & color(0); --Q & color
green <= color(3 downto 2) & color(2); --Q & color
blue <= color(5 downto 4) & color(4); --Q & color
-- red <= color(1 downto 0) & '0';
-- green <= color(3 downto 2) & '0';
-- blue <= color(5 downto 4) & '0';
blank <= '0';
if scanlines = '1' then --scanlines
if (vcount mod 2) = 0 then
red <= '0' & color(1 downto 0);
green <= '0' & color(3 downto 2);
blue <= '0' & color(5 downto 4);
else
red <= color(1 downto 0) & color(0);
green <= color(3 downto 2) & color(2);
blue <= color(5 downto 4) & color(4);
end if;
else
red <= color(1 downto 0) & color(0);
green <= color(3 downto 2) & color(2);
blue <= color(5 downto 4) & color(4);
end if;
blank <= '0';
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
blue <= (others=>'0');
blank <= '1';
end if;
end if;
end if;
end process;
end Behavioral;