Intercambio puertos de joystick

cores/MasterSystem/sms.prj

@@ -16,16 +16,15 @@ vhdl work "src/keyb/ps2_intf.vhd"
 vhdl work "src/dac.vhd"
 vhdl work "T80/T80se.vhd"
 vhdl work "src/vdp.vhd"
+verilog work "src/sprom.v"
 vhdl work "src/spi.vhd"
 vhdl work "src/ram.vhd"
 vhdl work "src/psg.vhd"
 verilog work "src/multiboot_v4.v"
 vhdl work "src/keyb/keyboard.vhd"
 vhdl work "src/io.vhd"
-vhdl work "src/bootrom_fill.vhd"
 vhdl work "src/vga_video.vhd"
 vhdl work "src/system.vhd"
 vhdl work "src/rgb_video.vhd"
-vhdl work "src/dvi-d/dvid.vhd"
 vhdl work "src/clocks.vhd"
 vhdl work "src/sms.vhd"

cores/MasterSystem/sms.ut

@@ -1,6 +1,5 @@
 -w
 -g DebugBitstream:No
--g Compress
 -g Binary:no
 -g CRC:Enable
 -g Reset_on_err:No

cores/MasterSystem/sms.xst

@@ -1,10 +1,10 @@
-set -tmpdir "projnav.tmp"
+set -tmpdir "xst/projnav.tmp"
 set -xsthdpdir "xst"
 run
 -ifn sms.prj
 -ofn sms
 -ofmt NGC
--p xc6slx9-3-tqg144
+-p xc6slx9-2-tqg144
 -top sms
 -opt_mode Speed
 -opt_level 1

cores/MasterSystem/src/bootrom_fill.vhd

@@ -4,7 +4,7 @@ library ieee;
   use ieee.numeric_std.all;
   use std.textio.all;
 
-entity boot_rom is
+entity boot_rom0 is
   generic (
         ADDR_WIDTH       : integer := 14;
         DATA_WIDTH       : integer := 8
@@ -17,7 +17,7 @@ entity boot_rom is
     );
 end;
 
-architecture RTL of boot_rom is
+architecture RTL of boot_rom0 is
 
    constant MEM_DEPTH : integer := 2**ADDR_WIDTH;
 

cores/MasterSystem/src/clocks.vhd

@@ -18,12 +18,14 @@ port
  (-- Clock in ports
   clk_in           : in     std_logic;
   sel_pclock : in std_logic;
+  sel_cpu : in std_logic;
   -- Clock out ports
   clk8          : out    std_logic;
   clk16          : out    std_logic;
   clk_cpu          : out    std_logic;
-  clk32  : out    std_logic;
-  pclock : out std_logic
+--  clk32  : out    std_logic;
+  pclock : out std_logic;
+  cpu_pclock : out std_logic
  );
 end clock;
 
@@ -42,6 +44,8 @@ architecture behavioral of clock is
   -- Unused status signals
   signal locked_unused    : std_logic;
   
+  signal clk357 : std_logic;
+
 begin
 
   -- Input buffering
@@ -66,18 +70,18 @@ begin
     DIVCLK_DIVIDE        => 1,
     CLKFBOUT_MULT        => 16,
     CLKFBOUT_PHASE       => 0.000,
-    CLKOUT0_DIVIDE       => 100, --25 = 32Mhz, --100 = 8Mhz
+    CLKOUT0_DIVIDE       => 100, --25 = 32Mhz, --100 = 8Mhz --1120 = 7,12Mhz (/2 = 3,57)
     CLKOUT0_PHASE        => 0.000,
     CLKOUT0_DUTY_CYCLE   => 0.500,
     CLKOUT1_DIVIDE       => 50, --50 = 16MHz
     CLKOUT1_PHASE        => 0.000,
     CLKOUT1_DUTY_CYCLE   => 0.500,
-    CLKOUT2_DIVIDE       => 27, --27 ~29.5Mhz Z80     --100 = 8mhz    --50 = 16mhz
+    CLKOUT2_DIVIDE       => 25, --27 ~29.5Mhz Z80     --100 = 8mhz    --50 = 16mhz   --32 = 25Mhz
     CLKOUT2_PHASE        => 0.000,
     CLKOUT2_DUTY_CYCLE   => 0.500,
-    CLKOUT3_DIVIDE       => 25, --25 = 32Mhz for HDMI clock
-    CLKOUT3_PHASE        => 0.000,
-    CLKOUT3_DUTY_CYCLE   => 0.500,
+--    CLKOUT3_DIVIDE       => 112, --25 = 32Mhz for HDMI clock
+--    CLKOUT3_PHASE        => 0.000,
+--    CLKOUT3_DUTY_CYCLE   => 0.500,
     CLKIN_PERIOD         => 20.0,
     REF_JITTER           => 0.010)
   port map
@@ -118,10 +122,10 @@ begin
    (O   => clk_cpu,
     I   => clkout2);
 
-  clkout4_buf : BUFG
-  port map
-   (O   => clk32,
-    I   => clkout3);
+--  clkout4_buf : BUFG
+--  port map
+--   (O   => clk32,
+--    I   => clkout3);
 	 
 	pclock_sel : BUFGMUX --muxer del relojes 16 / 8 para el pixel clock del scandoubler on/off
 	port map
@@ -130,4 +134,19 @@ begin
 	 I1 => clkout1, --el de 16
 	 S => sel_pclock);
 	 
+	 
+	pclock_sel_cpu : BUFGMUX --muxer del relojes 32 / 8 para el cambio de cpu (32 = loader/SD)
+	port map
+	(O => cpu_pclock,
+	 I0 => clkout1, 
+	 I1 => clkout2, --el de 32
+	 S => sel_cpu);	 
+
+--	process (clkout3)
+--	 begin
+--		if rising_edge(clkout3) then
+--			clk357 <= not clk357;
+--		end if;
+--	end process;
+
 end behavioral;

cores/MasterSystem/src/keyb/keyboard.vhd

@@ -13,7 +13,7 @@ port (
 	PS2_DATA	:	in		std_logic;
 	resetKey	:	out	std_logic;
 	MRESET	:  out	std_logic;
-   scanSW	:	out	std_logic_vector(7 downto 0)
+   scanSW	:	out	std_logic_vector(9 downto 0)
 	);
 end entity;
 
@@ -53,6 +53,8 @@ signal CTRL	: std_logic;
 signal ALT	: std_logic;
 signal PAUSE: std_logic := '0';
 signal VIDEO: std_logic := '0';
+signal SCANL: std_logic := '0';
+signal VFREQ: std_logic := '0';
 
 begin
 
@@ -130,6 +132,24 @@ begin
 								PAUSE <= '0';
 							end if;
 							
+					when X"7B" => 									 -- scanlines ("-" numpad)
+							if (SCANL = '0' and release = '0') then
+								scanSW(8) <= '1';
+								SCANL <= '1';
+							elsif (SCANL = '1' and release = '0') then
+								scanSW(8) <= '0';
+								SCANL <= '0';
+							end if;			
+							
+					when X"7C" => 									 -- vertical freq 50/60Hz ("*" numpad)
+							if (VFREQ = '0' and release = '0') then
+								scanSW(9) <= '1';
+								VFREQ <= '1';
+							elsif (VFREQ = '1' and release = '0') then
+								scanSW(9) <= '0';
+								VFREQ <= '0';
+							end if;									
+								
 					when others => null;
 					end case;
 					

cores/MasterSystem/src/rgb_video.vhd

@@ -15,8 +15,8 @@ entity rgb_video is
 		vsync:			out std_logic;
 		red:				out std_logic_vector(2 downto 0);
 		green:			out std_logic_vector(2 downto 0);
-		blue:				out std_logic_vector(2 downto 0)
---		; blank:			out std_logic
+		blue:				out std_logic_vector(2 downto 0);
+		vfreq:			in	 std_logic
 		);
 end rgb_video;
 
@@ -32,15 +32,25 @@ architecture Behavioral of rgb_video is
 	signal screen_sync:	std_logic;
 	signal vbl_sync:		std_logic;
 	
+	signal hcount_max: integer range 0 to 1023;
+	signal vcount_max: integer range 0 to 1023;
+	signal ypos:		 integer range 0 to 64;
+	signal vis_vc:		 integer range 0 to 512;
+
 	
 begin
 
+	hcount_max <= 511 when vfreq = '0' else 507;
+	vcount_max <= 311 when vfreq = '0' else 261;
+	ypos <= 70 when vfreq = '0' else 40;
+	vis_vc <= 302 when vfreq = '0' else 255;
+	
 	process (clk8)
 	begin
 		if rising_edge(clk8) then
-			if hcount=511 then
+			if hcount=hcount_max then --511 PAL / 507 NTSC
 				hcount <= (others => '0');
-				if vcount=311 then --PAL = 311 / NTSC = 261
+				if vcount=vcount_max then --PAL = 311 / NTSC = 261
 					vcount <= (others=>'0');
 				else
 					vcount <= vcount + 1;
@@ -51,7 +61,8 @@ begin
 		end if;
 	end process;
 	
-	visible		<= vcount>=35 and vcount<302 and hcount>=91 and hcount<509-38;
+--	visible		<= vcount>=35 and vcount<302 and hcount>=91 and hcount<509-38;
+	visible		<= vcount>=35 and vcount<vis_vc and hcount>=91 and hcount<509-38;
 											--PAL = 302, NTSC = 255
 	process (hcount)
 	begin
@@ -65,7 +76,7 @@ begin
 	in_vbl <= '1' when vcount<9 else '0';
 	
 	x					<= hcount-151;
-	y9					<= vcount-70;  --PAL = -70 , NTSC = -40
+	y9					<= vcount-ypos;  --PAL = -70 , NTSC = -40
 	y					<= y9(7 downto 0);
 	vblank			<= '1' when hcount=0 and vcount=0 else '0';
 	hblank			<= '1' when hcount=0 else '0';
@@ -100,9 +111,9 @@ begin
 
 vsync <= '1';
 	
-	process (clk16)
+	process (clk8) --clk16
 	begin
-		if rising_edge(clk16) then
+		if rising_edge(clk8) then --clk16
 			if visible then
 				red	<= color(1 downto 0) & color(1);  --Q & color;
 				green	<= color(3 downto 2) & color(3);  --Q & color;

cores/MasterSystem/src/sms.vhd

@@ -1,22 +1,34 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
 
 entity sms is
 	port (
 		clk:			in			STD_LOGIC;
 		
 		sram_we_n:	out		STD_LOGIC;
-		sram_a:		out		STD_LOGIC_VECTOR(18 downto 0);
+		sram_a:		out		STD_LOGIC_VECTOR(20 downto 0);
 		ram_d:		inout		STD_LOGIC_VECTOR(7 downto 0); --Q
 
---		j1_MDsel:	out		STD_LOGIC; --Q
 		j1_up:		in			STD_LOGIC;
 		j1_down:		in			STD_LOGIC;
 		j1_left:		in			STD_LOGIC;
 		j1_right:	in			STD_LOGIC;
 		j1_tl:		in			STD_LOGIC;
 		j1_tr:		inout		STD_LOGIC;
+		j1_fire3:	out		STD_LOGIC;
+		
+		j2_up:		in			STD_LOGIC;
+		j2_down:		in			STD_LOGIC;
+		j2_left:		in			STD_LOGIC;
+		j2_right:	in			STD_LOGIC;
+		j2_tl:		in			STD_LOGIC;
+		j2_tr:		inout		STD_LOGIC;	
+
+		SW1:			in			STD_LOGIC;
+		SW2:			in			STD_LOGIC;		
 
 		audio_l:		out		STD_LOGIC;
 		audio_r:		out		STD_LOGIC;
@@ -27,12 +39,6 @@ entity sms is
 		hsync:		buffer	STD_LOGIC;
 		vsync:		buffer	STD_LOGIC;
 
-		dred:			out	STD_LOGIC_VECTOR(2 downto 0);
-		dgreen:		out	STD_LOGIC_VECTOR(2 downto 0); 
-		dblue:			out	STD_LOGIC_VECTOR(2 downto 0);
-		dhsync:		out	STD_LOGIC;
-		dvsync:		out	STD_LOGIC;
-
 		spi_do:		in			STD_LOGIC;
 		spi_sclk:	out		STD_LOGIC;
 		spi_di:		out		STD_LOGIC;
@@ -43,93 +49,28 @@ entity sms is
       ps2_clk: 	in    	std_logic;
       ps2_data:	in    	std_logic;		
 		
-      NTSC: 		out   	std_logic; --Q
-      PAL: 			out   	std_logic --Q	
+      NTSC: 		out   	std_logic; 
+      PAL: 			out   	std_logic	
 
+--	   ;hdmi_out_p: out   	std_logic_vector(3 downto 0);
+--	   hdmi_out_n: out   	std_logic_vector(3 downto 0)	
 		);
 end sms;
 
 architecture Behavioral of sms is
 
-	component clock is
-   port (
-		clk_in:		in  std_logic;
-		sel_pclock: in  std_logic;
-		clk_cpu:		out std_logic;
-		clk16:		out std_logic;
-		clk8:			out std_logic;
-		clk32:		out std_logic;
-		pclock:		out std_logic);
-	end component;
-
-	component system is
-	port (
-		clk_cpu:		in		STD_LOGIC;
-		clk_vdp:		in		STD_LOGIC;
-		
-		ram_we_n:	out	STD_LOGIC;
-		ram_a:		out	STD_LOGIC_VECTOR(18 downto 0);
-		ram_d:		inout	STD_LOGIC_VECTOR(7 downto 0);
-
-		j1_up:		in		STD_LOGIC;
-		j1_down:		in		STD_LOGIC;
-		j1_left:		in		STD_LOGIC;
-		j1_right:	in		STD_LOGIC;
-		j1_tl:		in		STD_LOGIC;
-		j1_tr:		inout	STD_LOGIC;
-		j2_up:		in		STD_LOGIC;
-		j2_down:		in		STD_LOGIC;
-		j2_left:		in		STD_LOGIC;
-		j2_right:	in		STD_LOGIC;
-		j2_tl:		in		STD_LOGIC;
-		j2_tr:		inout	STD_LOGIC;
-		reset:		in		STD_LOGIC;
---		pause:		in		STD_LOGIC;
-
-		x:				in		UNSIGNED(8 downto 0);
-		y:				in		UNSIGNED(7 downto 0);
---		vblank:		in		STD_LOGIC;
---		hblank:		in		STD_LOGIC;
-		color:		out	STD_LOGIC_VECTOR(5 downto 0);
-		audio:		out	STD_LOGIC;
-		
-      ps2_clk: 	in    std_logic;
-      ps2_data: 	in    std_logic;	
-
-		scanSW:		out	std_logic;
-
-		spi_do:		in		STD_LOGIC;
-		spi_sclk:	out	STD_LOGIC;
-		spi_di:		out	STD_LOGIC;
-		spi_cs_n:	buffer	STD_LOGIC
-);
-	end component;
-	
-	component rgb_video is
-	port (
-		clk16:		in  	std_logic;
-		clk8:			in  	std_logic; --Q
-		x: 			out 	unsigned(8 downto 0);
-		y:				out 	unsigned(7 downto 0);
-		vblank:		out 	std_logic;
-		hblank:		out 	std_logic;
-		color:		in  	std_logic_vector(5 downto 0);
-		hsync:		out 	std_logic;
-		vsync:		out 	std_logic;
-		red:			out 	std_logic_vector(2 downto 0);
-		green:		out 	std_logic_vector(2 downto 0);
-		blue:			out 	std_logic_vector(2 downto 0)
---		; blank:		out 	std_logic
-);
-	end component;
-	
+-- Cambiar segun tipo de placa/opción joysticks
+-- JoyType: 0 = un Joy. 1 = dos Joys
+constant JoyType : integer := 1; 
 
 	signal clk_cpu:		std_logic;
 	signal clk16:			std_logic;
 	signal clk8:			std_logic;
 	signal clk32:			std_logic;
+	signal cpu_pclock:	std_logic;
 	
 	signal sel_pclock:	std_logic;
+	signal sel_cpu:	std_logic;
 	signal blank:			std_logic;
 --	signal blankr:			std_logic;
 	
@@ -164,29 +105,38 @@ architecture Behavioral of sms is
 	
 	signal scanSWk:		std_logic;
 	signal scanSW:			std_logic;
-	
-	signal j2_tr:			std_logic;
-	
-	signal c0, c1, c2 : 	std_logic_vector(9 downto 0);	--hdmi
+	signal scanL:			std_logic;
+	signal vfreQ:			std_logic;
 	
 	signal poweron_reset:	unsigned(7 downto 0) := "00000000";
 	signal scandoubler_ctrl: std_logic_vector(1 downto 0);
 	signal ram_we_n: std_logic;
-	signal ram_a:	std_logic_vector(18 downto 0);
+	signal ram_a:	std_logic_vector(19 downto 0);
+	
+	signal joy1:  std_logic_vector(5 downto 0);
+	signal joy2:  std_logic_vector(5 downto 0);
+	signal joy_mux:  std_logic_vector(16 downto 0);
+	signal j1_f3: std_logic;
+	signal ePause: std_logic;
+	signal eReset: std_logic;
+	
+	signal pwon: std_logic;
 	
 begin
 
-	clock_inst: clock
+	clock_inst: entity work.clock
 	port map (
 		clk_in		=> clk,
 		sel_pclock  => sel_pclock,
-		clk_cpu		=> clk_cpu,
+		sel_cpu  	=> sel_cpu,
+		clk8			=> clk8,
 		clk16			=> clk16,
-		clk8			=> clk8, --clk32 => open
-		clk32			=> clk32,
-		pclock		=> rgb_clk);
+		clk_cpu		=> clk32,		
+		pclock		=> rgb_clk,
+		cpu_pclock		=> cpu_pclock
+		);
 		
-	video_inst: rgb_video
+	video_inst: entity work.rgb_video
 	port map (
 		clk16			=> clk16, 
 		clk8			=> clk8, --Q
@@ -199,8 +149,8 @@ begin
 		vsync			=> rgb_vsync,
 		red			=> rgb_red, 
 		green			=> rgb_green, 
-		blue			=> rgb_blue 
---		,blank		=> blankr
+		blue			=> rgb_blue, 
+		vfreq			=> vfreQ
 	);
 	
 	video_vga_inst: entity work.vga_video --vga
@@ -208,40 +158,79 @@ begin
 		clk16			=> clk16, 
 		x	 			=> vga_x,
 		y				=> vga_y,
-		vblank		=> vga_vblank,
-		hblank		=> vga_hblank,
+--		vblank		=> vga_vblank,
+--		hblank		=> vga_hblank,
 		color			=> color,		
 		hsync			=> vga_hsync,
 		vsync			=> vga_vsync,
 		red			=> vga_red, 
 		green			=> vga_green, 
 		blue			=> vga_blue, 
-		blank			=> blank
+		blank			=> blank,
+		scanlines	=> scandoubler_ctrl(1) xor scanL,
+		vfreq			=> vfreQ
 	);	
 
-	system_inst: system
+
+JT1 : if (JoyType = 1) generate	
+	j1_fire3 <= j1_f3;
+
+	process (j1_f3)
+	begin		
+			if j1_f3 = '0' then
+				joy2 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
+			else
+				joy1 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
+			end if;	
+	end process;
+	
+	process (clk32)
+	begin
+		if rising_edge(clk32) then			
+			j1_f3 <= joy_mux(16);
+			joy_mux <= joy_mux + 1;
+		end if;
+	end process;	
+
+	ePause <= '1';
+	eReset <= '1';
+	
+end generate JT1;
+	
+
+JT0 : if (JoyType = 0) generate	
+	joy1 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
+	joy2 <= j1_up & j1_down & j1_left & j1_right & j1_tl & j1_tr;
+	ePause <= '1';
+	eReset <= '1';	
+	j1_fire3 <= '0';		
+end generate JT0;			
+
+		
+	system_inst: entity work.system
 	port map (
-		clk_cpu		=> clk_cpu, --clk_cpu
-		clk_vdp		=> rgb_clk,	--clk8 = rgb  --clk16 = vga
+		clk_cpu		=> cpu_pclock,	--cpu_pclock, --clk_cpu
+		clk_vdp		=> rgb_clk,	--rgb_clk, --clk8 = rgb  --clk16 = vga
+		clk32			=> clk32,
 		
 		ram_we_n		=> ram_we_n,
 		ram_a			=> ram_a,
 		ram_d			=> ram_d,
 
-		j1_up			=> j1_up,
-		j1_down		=> j1_down,
-		j1_left		=> j1_left,
-		j1_right		=> j1_right,
-		j1_tl			=> j1_tl,
-		j1_tr			=> j1_tr,
-		j2_up			=> '1',
-		j2_down		=> '1',
-		j2_left		=> '1',
-		j2_right		=> '1',
-		j2_tl			=> '1',
-		j2_tr			=> j2_tr,
-		reset			=> '1',
---		pause			=> '1',
+		j1_up			=> joy1(5), --j1_up,
+		j1_down		=> joy1(4), --j1_down,
+		j1_left		=> joy1(3), --j1_left,
+		j1_right		=> joy1(2), --j1_right,
+		j1_tl			=> joy1(1), --j1_tl,
+		j1_tr			=> joy1(0), --j1_tr,
+		j2_up			=> joy2(5), --'1',
+		j2_down		=> joy2(4), --'1',
+		j2_left		=> joy2(3), --'1',
+		j2_right		=> joy2(2), --'1',
+		j2_tl			=> joy2(1), --'1',
+		j2_tr			=> joy2(0), --j2_tr,
+		reset			=> eReset,
+		pause			=> ePause,
 
 		x				=> x,
 		y				=> y,
@@ -254,35 +243,31 @@ begin
 		ps2_data		=> ps2_data,
 		
 		scanSW		=> scanSWk,
+		scanL			=> scanL,
+		vfreQ			=> vfreQ,
 
 		spi_do		=> spi_do,
 		spi_sclk		=> spi_sclk,
 		spi_di		=> spi_di,
-		spi_cs_n		=> spi_cs_n
+		spi_cs_n		=> spi_cs_n,
+		sel_cpu		=> sel_cpu
 		);
 		
-  
-  dred <= red;
-  dgreen <= green;
-  dblue <= blue;
-  dhsync <= hsync;
-  dvsync <= vsync;
-
 	led <= not spi_cs_n; --Q
 --	led <= scandoubler_ctrl(0); --debug scandblctrl reg.
 
 	audio_l <= audio;
 	audio_r <= audio;
 	
-	NTSC <= '0';
-	PAL <= '1';	
+	NTSC <= vfreQ;
+	PAL <= not vfreQ;	
 	
 	---- scandlbctrl register detection for video mode initialization at start ----
 	
-	process (clk_cpu)
+	process (clk32)
 	begin
-		if rising_edge(clk_cpu) then
-        if (poweron_reset < 126) then
+		if rising_edge(clk32) then
+        if (poweron_reset < 90) then
             scandoubler_ctrl <= ram_d(1 downto 0);
 		  end if;
 		  if poweron_reset < 254 then
@@ -291,9 +276,10 @@ begin
 		end if;
 	end process;
 	
-
-	sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
+	sram_a(20) <= '0';
+	sram_a(19 downto 0) <= "00001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
 	sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
+	pwon <= '1' when poweron_reset < 254 else '0';
 	
 	-------------------------------------------------------------------------------
 	
@@ -315,4 +301,19 @@ begin
 	scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
 
 
+--HDMI
+
+--Inst_MinimalDVID_encoder: entity work.MinimalDVID_encoder PORT MAP(
+--      clk    => clk32,
+--      blank  => blank,
+--      hsync  => hsync,
+--      vsync  => vsync,
+--      red    => red,
+--      green  => green,
+--      blue   => blue,
+--      hdmi_p => hdmi_out_p,
+--      hdmi_n => hdmi_out_n
+--   );
+      		
+	
 end Behavioral;

cores/MasterSystem/src/sms_zxuno_v4.ucf

@@ -1,34 +1,57 @@
 #UCF para el ZX-UNO v4
-NET "CLK"             LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
+
+NET "CLK"	 		PERIOD=20 ns;
+NET "CLK"     		LOC="P55"  | IOSTANDARD=LVCMOS33; 
+
 NET "led"			LOC="P11"  | IOSTANDARD=LVCMOS33;
 
-# Video output
-NET "red(2)"          LOC="P81"  | IOSTANDARD = LVCMOS33;                                
-NET "red(1)"          LOC="P80"  | IOSTANDARD = LVCMOS33;                                
-NET "red(0)"          LOC="P79"  | IOSTANDARD = LVCMOS33;                               
-NET "green(2)"        LOC="P84"  | IOSTANDARD = LVCMOS33;                               
-NET "green(1)"        LOC="P83"  | IOSTANDARD = LVCMOS33;                                
-NET "green(0)"        LOC="P82"  | IOSTANDARD = LVCMOS33;                                
-NET "blue(2)"         LOC="P93"  | IOSTANDARD = LVCMOS33;                              
-NET "blue(1)"         LOC="P92"  | IOSTANDARD = LVCMOS33;                                
-NET "blue(0)"         LOC="P88"  | IOSTANDARD = LVCMOS33;                               
-NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;                                
-NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;                                
-NET "NTSC"            LOC="P66"  | IOSTANDARD = LVCMOS33;
-NET "PAL"             LOC="P67"  | IOSTANDARD = LVCMOS33;
+NET "j1_tr"			LOC="P8"   | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_tl"			LOC="P2"   | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_right"		LOC="P7"   | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_left"		LOC="P6"   | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_down"		LOC="P5"   | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j1_up"			LOC="P1"   | IOSTANDARD=LVCMOS33 | PULLUP;
+
+###JoySplitter AV optional J16
+NET "j1_fire3"		LOC="P39"   | IOSTANDARD=LVCMOS33;
+##--##
+
+
+###Jamma addon / MFH 2M##
+NET "j2_up"   	LOC="P26" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j2_down"  LOC="P30" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j2_left"  LOC="P34" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j2_right" LOC="P41" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j2_tl"   	LOC="P47" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "j2_tr"  	LOC="P46" | IOSTANDARD=LVCMOS33 | PULLUP;
+
+NET "SW1"  	 LOC="P56" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "SW2"  	 LOC="P15" | IOSTANDARD=LVCMOS33 | PULLUP;
+## -- ##
+
+NET "vsync"			LOC="P85"  | IOSTANDARD=LVCMOS33;                                
+NET "hsync"			LOC="P87"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(0)"		LOC="P82"  | IOSTANDARD=LVCMOS33;                                
+NET "blue(0)"		LOC="P88"  | IOSTANDARD=LVCMOS33;                               
+NET "red(0)"		LOC="P79"  | IOSTANDARD=LVCMOS33;                               
+
+NET "green(1)"		LOC="P83"  | IOSTANDARD=LVCMOS33;                                
+NET "blue(1)"		LOC="P92"  | IOSTANDARD=LVCMOS33;                                
+NET "red(1)"		LOC="P80"  | IOSTANDARD=LVCMOS33;                                
+
+NET "green(2)"		LOC="P84"  | IOSTANDARD=LVCMOS33;                               
+NET "blue(2)"		LOC="P93"  | IOSTANDARD=LVCMOS33;                              
+NET "red(2)"		LOC="P81"  | IOSTANDARD=LVCMOS33;                                
+                               
+NET "spi_do"		LOC="P78"  | IOSTANDARD=LVCMOS33;
+NET "spi_sclk"		LOC="P75"  | IOSTANDARD=LVCMOS33;
+NET "spi_di"		LOC="P74"  | IOSTANDARD=LVCMOS33;
+NET "spi_cs_n"		LOC="P59"  | IOSTANDARD=LVCMOS33;
 
-# Sound input/output
 NET "audio_l"		LOC="P10"  | IOSTANDARD=LVCMOS33;                               
 NET "audio_r"		LOC="P9"   | IOSTANDARD=LVCMOS33;                               
 
-
-# Keyboard and mouse
-NET "ps2_clk"         LOC="P99"  | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "ps2_data"        LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
-
-
-
-# SRAM
 NET "sram_a<0>"  LOC="P141" | IOSTANDARD = LVCMOS33;
 NET "sram_a<1>"  LOC="P139" | IOSTANDARD = LVCMOS33;
 NET "sram_a<2>"  LOC="P137" | IOSTANDARD = LVCMOS33;
@@ -48,8 +71,8 @@ NET "sram_a<15>"      LOC="P131" | IOSTANDARD = LVCMOS33;
 NET "sram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
 NET "sram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
 NET "sram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "sram_a<19>"      LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_a<20>"      LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
 
 NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
 NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
@@ -62,39 +85,17 @@ NET "ram_d<7>"        LOC="P126" | IOSTANDARD = LVCMOS33;
 
 NET "sram_WE_n" 	 LOC="P121" | IOSTANDARD = LVCMOS33;
 
+NET "NTSC"         LOC="P66"  | IOSTANDARD=LVCMOS33;
+NET "PAL"          LOC="P67"  | IOSTANDARD=LVCMOS33;
 
+NET "ps2_data"     LOC="P98"  | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "ps2_clk"      LOC="P99"  | IOSTANDARD=LVCMOS33 | PULLUP;
 
-
-
-
-
-
-
-# SD/MMC
-NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33;
-NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33;
-NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33;
-NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33;
-
-# JOYSTICK
-NET "j1_up"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "j1_down"         LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "j1_left"         LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "j1_right"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "j1_tl"           LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "j1_tr"           LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
-
-
-
-
-NET dred(2)           LOC="P51"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dred(1)           LOC="P50"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dred(0)           LOC="P47"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dgreen(2)         LOC="P40"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dgreen(1)         LOC="P35"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dgreen(0)         LOC="P33"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dblue(2)          LOC="P23"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dblue(1)          LOC="P17"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dblue(0)          LOC="P24"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dhsync            LOC="P57"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
-NET dvsync            LOC="P58"  | IOSTANDARD = LVCMOS33 | DRIVE=2 | SLEW=SLOW;
+#NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
+#NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";

cores/MasterSystem/src/system.vhd

@@ -1,5 +1,6 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
 use work.all;
@@ -8,9 +9,10 @@ entity system is
 	port (
 		clk_cpu:		in		STD_LOGIC;
 		clk_vdp:		in		STD_LOGIC;
+		clk32:		in		STD_LOGIC;
 		
 		ram_we_n:	out	STD_LOGIC;
-		ram_a:		out	STD_LOGIC_VECTOR(18 downto 0);
+		ram_a:		out	STD_LOGIC_VECTOR(19 downto 0);
 		ram_d:		inout	STD_LOGIC_VECTOR(7 downto 0); --Q
 
 		j1_up:		in		STD_LOGIC;
@@ -26,7 +28,7 @@ entity system is
 		j2_tl:		in		STD_LOGIC;
 		j2_tr:		inout	STD_LOGIC;
 		reset:		in		STD_LOGIC;
---		pause:		in		STD_LOGIC;
+		pause:		in		STD_LOGIC;
 
 		x:				in		UNSIGNED(8 downto 0);
 		y:				in		UNSIGNED(7 downto 0);
@@ -39,16 +41,20 @@ entity system is
       ps2_data: 	in    std_logic;	
 
 		scanSW:		out	std_logic;
+		scanL:		out	std_logic;
+		vfreQ:		out	std_logic;
 
 		spi_do:		in		STD_LOGIC;
 		spi_sclk:	out	STD_LOGIC;
 		spi_di:		out	STD_LOGIC;
-		spi_cs_n:	buffer	STD_LOGIC
+		spi_cs_n:	buffer	STD_LOGIC;
+		sel_cpu:		out	std_logic
 	);
 end system;
 
 architecture Behavioral of system is
 
+	
 	component T80se is
 	generic(
 		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
@@ -107,6 +113,7 @@ architecture Behavioral of system is
 		output:			out STD_LOGIC);
 	end component;
 	
+	
 	component io is
    port (
 		clk:				in		STD_LOGIC;
@@ -163,6 +170,13 @@ architecture Behavioral of system is
 		mosi:				out STD_LOGIC);
 	end component;
 	
+    component multiboot is
+     port (
+		clk_icap:				in  STD_LOGIC;
+		REBOOT:				in  STD_LOGIC
+		);
+	end component;	
+
 	signal RESET_n:			std_logic;
 	signal resetKey:			std_logic;
 	signal MRESET:				std_logic;
@@ -175,9 +189,11 @@ architecture Behavioral of system is
 	signal p1_right:		 	STD_LOGIC; --3
 	signal p1_tl:			 	STD_LOGIC; --4
 	signal p1_tr:				STD_LOGIC; --5
-	signal ctrl_keys:			std_logic_vector(7 downto 0);
+	signal ctrl_keys:			std_logic_vector(9 downto 0);
 	signal Kpause:				std_logic := '1';
 	
+	signal p2_tr:				STD_LOGIC; 
+	
 	signal RD_n:				std_logic;
 	signal WR_n:				std_logic;
 	signal IRQ_n:				std_logic;
@@ -218,10 +234,14 @@ architecture Behavioral of system is
 	--reset vram
 	signal RST_vram:			std_logic;
 
-	signal bank0:				std_logic_vector(4 downto 0);
-	signal bank1:				std_logic_vector(4 downto 0); 
-	signal bank2:				std_logic_vector(4 downto 0); 
+	signal bank0:				std_logic_vector(5 downto 0);
+	signal bank1:				std_logic_vector(5 downto 0); 
+	signal bank2:				std_logic_vector(5 downto 0); 
 	
+	signal downloading : std_logic:='0';
+	
+	signal A_TOP: integer:=18;
+	signal B_TOP: integer:=4;
 	
 begin	
 	
@@ -271,11 +291,12 @@ begin
 		
 	psg_inst: psg
 	port map (
-		clk			=> clk_cpu,
+		clk			=> clk32, --clk_cpu
 		WR_n			=> psg_WR_n,
 		D_in			=> D_in,
 		output		=> audio);
 		
+			
 	io_inst: io
    port map (
 		clk			=> clk_cpu,
@@ -295,7 +316,7 @@ begin
 		J2_left		=> j2_left,
 		J2_right		=> j2_right,
 		J2_tl			=> j2_tl,
-		J2_tr			=> j2_tr,
+		J2_tr			=> p2_tr,
 		RESET			=> reset);
 		
 	ram_inst: ram
@@ -338,6 +359,11 @@ begin
 		  ctrl_keys 
         );	
 
+	A_TOP <= 18;
+	B_TOP <= 4;
+--	ram_a(19) <= '0';
+		  
+		   
 	
 	-- glue logic
 
@@ -364,7 +390,7 @@ begin
 	process (clk_cpu)
 	begin
 		if rising_edge(clk_cpu) then
-			if resetKey = '1' then --q
+			if resetKey = '1' or reset = '0' then --q
 					bootloader <= '0';
 					reset_counter <= (others=>'1');
 					--RST_vram <= '1';
@@ -388,6 +414,8 @@ begin
 	
 	RST_vram <= '1' when bootloader='0' else '0'; --Q -vram fill
 	
+	sel_cpu <= '1' when bootloader = '0' else '0'; --high speed when downloading rom from SD / bootloader.
+	
    process (io_n,A,spi_D_out,vdp_D_out,io_D_out,irom_D_out,ram_D_out)
 	begin
 		if io_n='0' then
@@ -417,9 +445,9 @@ begin
 		if rising_edge(clk_cpu) then
 			if WR_n='0' and A(15 downto 2)="11111111111111" then
 				case A(1 downto 0) is
-				when "01" => bank0 <= D_in(4 downto 0); --Q
-				when "10" => bank1 <= D_in(4 downto 0); --Q
-				when "11" => bank2 <= D_in(4 downto 0); --Q
+				when "01" => bank0(B_TOP downto 0) <= D_in(B_TOP downto 0); --Q
+				when "10" => bank1(B_TOP downto 0) <= D_in(B_TOP downto 0); --Q
+				when "11" => bank2(B_TOP downto 0) <= D_in(B_TOP downto 0); --Q
 				when others =>
 				end case;
 			end if;
@@ -435,15 +463,15 @@ begin
 		when "00" =>
 			-- first kilobyte is always from bank 0
 			if A(13 downto 10)="0000" then
-				ram_a(18 downto 14) <= (others=>'0'); --Q
+				ram_a(A_TOP downto 14) <= (others=>'0'); --Q
 			else
-				ram_a(18 downto 14) <= bank0; --Q
+				ram_a(A_TOP downto 14) <= bank0(B_TOP downto 0); --Q
 			end if;
 		when "01" =>
-			ram_a(18 downto 14) <= bank1; --Q
+			ram_a(A_TOP downto 14) <= bank1(B_TOP downto 0); --Q
 			
 		when others =>
-			ram_a(18 downto 14) <= bank2; --Q
+			ram_a(A_TOP downto 14) <= bank2(B_TOP downto 0); --Q
 		end case;
 	end process;
 	
@@ -464,17 +492,19 @@ begin
 	p1_tl <= ctrl_keys(4) xnor not j1_tl;
 	p1_tr <= '0' when ctrl_keys(5)='1' or j1_tr='0' else 'Z';
 	
+	p2_tr <= '0' when j2_tr='0' else 'Z'; --j2_tr tristate
+	
 
 	process (ctrl_keys(7))
 	begin
-		if ctrl_keys(7) = '1' then
+		if ctrl_keys(7) = '1' or pause = '0' then --Pause
 			Kpause <= '0';
 		else
 			Kpause <= '1';
 		end if;
 	end process;
 
-	process (ctrl_keys(6))
+	process (ctrl_keys(6)) --RGB/VGA
 	begin
 		if ctrl_keys(6) = '0' then
 			scanSW <= '0';
@@ -483,10 +513,28 @@ begin
 		end if;
 	end process;
 	
+	process (ctrl_keys(8)) --scanlines
+	begin
+		if ctrl_keys(8) = '0' then
+			scanL <= '0';
+		else
+			scanL <= '1';
+		end if;
+	end process;	
+	
+	process (ctrl_keys(9)) --vfreq
+	begin
+		if ctrl_keys(9) = '0' then
+			vfreQ <= '0';
+		else
+			vfreQ <= '1';
+		end if;
+	end process;	
+
 	
 ------------multiboot---------------
 
-	multiboot: entity work.multiboot
+	multiboot_i: multiboot
 	port map(
 		clk_icap		      => clk_vdp,
 		REBOOT				=> MRESET

cores/MasterSystem/src/vdp_main.vhd

@@ -110,7 +110,7 @@ begin
 		vram_D			=> vram_D,		
 		color				=> spr_color);
 
-	process (x, y, bg_priority, spr_color, bg_color, overscan)
+	process (x, y, bg_priority, spr_color, bg_color, overscan, mask_column0)
 		variable spr_active	: boolean;
 		variable bg_active	: boolean;
 	begin

cores/MasterSystem/src/vga_video.vhd

@@ -14,8 +14,10 @@ entity vga_video is
 		vsync:			out std_logic;
 		red:				out std_logic_vector(2 downto 0);
 		green:			out std_logic_vector(2 downto 0);
-		blue:				out std_logic_vector(2 downto 0)
-		; blank:			out std_logic
+		blue:				out std_logic_vector(2 downto 0);
+		blank:			out std_logic;
+		scanlines:		in	 std_logic;
+		vfreq:			in	 std_logic
 		);
 end vga_video;
 
@@ -27,14 +29,22 @@ architecture Behavioral of vga_video is
 	
 	signal y9:			unsigned (8 downto 0);
 	
+	signal hcount_max: integer range 0 to 1023;
+	signal vcount_max: integer range 0 to 1023;
+	signal ypos:		 integer range 0 to 64;
+	
 begin
 
+	hcount_max <= 511 when vfreq = '0' else 507;
+	vcount_max <= 622 when vfreq = '0' else 522;
+	ypos <= 55 when vfreq = '0' else 27;
+	
 	process (clk16)
 	begin
 		if rising_edge(clk16) then
-			if hcount=511 then --507 = 60Hz , 511 = 50Hz
+			if hcount=hcount_max then --507 = 60Hz , 511 = 50Hz
 				hcount <= (others => '0');
-				if vcount=622 then --523 = 60Hz, 623 = 50Hz --622
+				if vcount=vcount_max then --523 = 60Hz, 623 = 50Hz --622
 					vcount <= (others=>'0');
 				else
 					vcount <= vcount + 1;
@@ -47,7 +57,8 @@ begin
 	
 	x				<= hcount-(91+60); --62
 --	y9				<= vcount(9 downto 1)-(13+27); --60Hz
-	y9				<= vcount(9 downto 1)-(13+55);
+--	y9				<= vcount(9 downto 1)-(13+55); --50Hz
+	y9				<= vcount(9 downto 1)-(13+ypos); --var
 	y				<= y9(7 downto 0);
 	hblank		<= '1' when hcount=0 and vcount(0 downto 0)=0 else '0';
 	vblank		<= '1' when hcount=0 and vcount=0 else '0';
@@ -56,19 +67,29 @@ begin
 	vsync			<= '0' when vcount<2 else '1';
 	
 --	visible		<= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406; --60Hz
-	visible		<= vcount>=35 and vcount<35+580 and hcount>=91 and hcount<91+406; --50Hz	
+--	visible		<= vcount>=35 and vcount<35+580 and hcount>=91 and hcount<91+406; --50Hz	
+	visible		<= vcount>=35 and vcount<35+vcount_max-42 and hcount>=91 and hcount<91+406; --var	
 	
 	
 	process (clk16)
 	begin
 		if rising_edge(clk16) then
 			if visible then
-					red	<= color(1 downto 0) & color(0);  --Q & color 
-					green	<= color(3 downto 2) & color(2);  --Q & color
-					blue	<= color(5 downto 4) & color(4);  --Q & color
---					red	<= color(1 downto 0) & '0'; 
---					green	<= color(3 downto 2) & '0';
---					blue	<= color(5 downto 4) & '0';
+			   if scanlines = '1' then --scanlines
+					if (vcount mod 2) = 0 then
+						red	<= '0' & color(1 downto 0);  
+						green	<= '0' & color(3 downto 2);  
+						blue	<= '0' & color(5 downto 4); 
+					else									
+						red	<= color(1 downto 0) & color(0);  
+						green	<= color(3 downto 2) & color(2);  
+						blue	<= color(5 downto 4) & color(4);  
+					end if;
+				else
+					red	<= color(1 downto 0) & color(0);  
+					green	<= color(3 downto 2) & color(2);  
+					blue	<= color(5 downto 4) & color(4);   
+				end if;
 				
 				blank <= '0';
 			else