From 757d0afa8436e54a02f0c0d2aef3b186a0d9d6fc Mon Sep 17 00:00:00 2001
From: antoniovillena <espineter@yahoo.com>
Date: Wed, 4 May 2016 18:23:49 +0200
Subject: [PATCH] Limpio carpeta Jupiter Ace

---
 cores/BBCMicro/working/make.bat               |  22 +-
 cores/JupiterAce/jupiter_ace.gise             | 188 --------
 cores/JupiterAce/jupiter_ace.prj              |  13 +
 cores/JupiterAce/jupiter_ace.ut               |  30 ++
 .../{tld_jace_spartan6.v => jupiter_ace.v}    |   0
 cores/JupiterAce/jupiter_ace.xise             | 427 ------------------
 cores/JupiterAce/jupiter_ace.xst              |  52 +++
 cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf     |  89 ++++
 cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf  |  91 ++++
 cores/JupiterAce/jupiter_ace_zxuno_v4.ucf     |  91 ++++
 cores/JupiterAce/make.bat                     |   7 +
 cores/JupiterAce/par_usage_statistics.html    |  32 --
 cores/JupiterAce/pines_zxuno.ucf              |  82 ----
 cores/JupiterAce/pines_zxuno_Ap.ucf           |  82 ----
 cores/JupiterAce/pines_zxuno_v4.ucf           |  85 ----
 cores/JupiterAce/relojes.v                    | 145 ++++++
 cores/generar.bat                             |   6 +
 cores/genxst.bat                              |   2 +
 18 files changed, 537 insertions(+), 907 deletions(-)
 delete mode 100644 cores/JupiterAce/jupiter_ace.gise
 create mode 100644 cores/JupiterAce/jupiter_ace.prj
 create mode 100644 cores/JupiterAce/jupiter_ace.ut
 rename cores/JupiterAce/{tld_jace_spartan6.v => jupiter_ace.v} (100%)
 delete mode 100644 cores/JupiterAce/jupiter_ace.xise
 create mode 100644 cores/JupiterAce/jupiter_ace.xst
 create mode 100644 cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
 create mode 100644 cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
 create mode 100644 cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
 create mode 100644 cores/JupiterAce/make.bat
 delete mode 100644 cores/JupiterAce/par_usage_statistics.html
 delete mode 100644 cores/JupiterAce/pines_zxuno.ucf
 delete mode 100644 cores/JupiterAce/pines_zxuno_Ap.ucf
 delete mode 100644 cores/JupiterAce/pines_zxuno_v4.ucf
 create mode 100644 cores/JupiterAce/relojes.v
 create mode 100644 cores/generar.bat
 create mode 100644 cores/genxst.bat

diff --git a/cores/BBCMicro/working/make.bat b/cores/BBCMicro/working/make.bat
index 6038303..6024c18 100644
--- a/cores/BBCMicro/working/make.bat
+++ b/cores/BBCMicro/working/make.bat
@@ -1,17 +1,17 @@
-SET machine = "bbc_micro"
+SET machine=bbc_micro
 if not exist projnav.tmp mkdir projnav.tmp
 call xst      -intstyle ise -ifn %machine%.xst -ofn %machine%.syr
-call :generar v2 %machine%
-call :generar v3 %machine%
-call :generar v4 %machine%
-call :generar Ap %machine%
+call :generar v2
+call :generar v3
+call :generar v4
+call :generar Ap
 goto :eof
 
 :generar
-call ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ..\src\%2_zxuno_%1.ucf -p xc6slx9-tqg144-2 %2.ngc %2.ngd
-call map      -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %2_map.ncd %2.ngd %2.pcf
-call par      -intstyle ise -w -ol high -mt 4 %2_map.ncd %2.ncd %2.pcf
-call trce     -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %2.twx %2.ncd -o %2.twr %2.pcf
-call bitgen   -intstyle ise -f %2.ut %2.ncd
-copy /y %2.bit %2.%1.bit
+call ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ..\src\%machine%_zxuno_%1.ucf -p xc6slx9-tqg144-2 %machine%.ngc %machine%.ngd
+call map      -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %machine%_map.ncd %machine%.ngd %machine%.pcf
+call par      -intstyle ise -w -ol high -mt 4 %machine%_map.ncd %machine%.ncd %machine%.pcf
+call trce     -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %machine%.twx %machine%.ncd -o %machine%.twr %machine%.pcf
+call bitgen   -intstyle ise -f %machine%.ut %machine%.ncd
+copy /y %machine%.bit %machine%.%1.bit
 :eof
\ No newline at end of file
diff --git a/cores/JupiterAce/jupiter_ace.gise b/cores/JupiterAce/jupiter_ace.gise
deleted file mode 100644
index d297a4b..0000000
--- a/cores/JupiterAce/jupiter_ace.gise
+++ /dev/null
@@ -1,188 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="jupiter_ace.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.bgn" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_jace_spartan6.bit" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_jace_spartan6.bld"/>
-    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_jace_spartan6.cmd_log"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_jace_spartan6.drc" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_jace_spartan6.lso"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6.ncd" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_jace_spartan6.ngc"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_jace_spartan6.ngd"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_jace_spartan6.ngr"/>
-    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_jace_spartan6.pad"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_jace_spartan6.par" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_jace_spartan6.pcf" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_jace_spartan6.prj"/>
-    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_jace_spartan6.ptwx"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_jace_spartan6.stx"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_jace_spartan6.syr"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_jace_spartan6.twr" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_jace_spartan6.twx" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_jace_spartan6.unroutes" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.ut" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_jace_spartan6.xpi"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_jace_spartan6.xst"/>
-    <file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_guide.ncd" xil_pn:origination="imported"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.map" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.mrp" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_map.ncd" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_jace_spartan6_map.ngm" xil_pn:subbranch="Map"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_map.xrpt"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_jace_spartan6_pad.csv" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_jace_spartan6_pad.txt" xil_pn:subbranch="Par"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_par.xrpt"/>
-    <file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_jace_spartan6_summary.html"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_jace_spartan6_summary.xml"/>
-    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_jace_spartan6_usage.xml"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
-    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
-    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4731562624927410055" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6263557264038183016" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1951148348739412805" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2932384963007625358" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482377" xil_pn:in_ck="-1011495219309582457" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5110793382240503873" xil_pn:start_ts="1460482304">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.lso"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ngc"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ngr"/>
-      <outfile xil_pn:name="tld_jace_spartan6.prj"/>
-      <outfile xil_pn:name="tld_jace_spartan6.stx"/>
-      <outfile xil_pn:name="tld_jace_spartan6.syr"/>
-      <outfile xil_pn:name="tld_jace_spartan6.xst"/>
-      <outfile xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
-      <outfile xil_pn:name="webtalk_pn.xml"/>
-      <outfile xil_pn:name="xst"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482871" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3073422981912245990" xil_pn:start_ts="1460482871">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482887" xil_pn:in_ck="-8973030265980210664" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4306676935314038505" xil_pn:start_ts="1460482871">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_ngo"/>
-      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.bld"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ngd"/>
-      <outfile xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482933" xil_pn:in_ck="-8973030265980210663" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1460482887">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.pcf"/>
-      <outfile xil_pn:name="tld_jace_spartan6_map.map"/>
-      <outfile xil_pn:name="tld_jace_spartan6_map.mrp"/>
-      <outfile xil_pn:name="tld_jace_spartan6_map.ncd"/>
-      <outfile xil_pn:name="tld_jace_spartan6_map.ngm"/>
-      <outfile xil_pn:name="tld_jace_spartan6_map.xrpt"/>
-      <outfile xil_pn:name="tld_jace_spartan6_summary.xml"/>
-      <outfile xil_pn:name="tld_jace_spartan6_usage.xml"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-5559234896413727310" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1460482933">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ncd"/>
-      <outfile xil_pn:name="tld_jace_spartan6.pad"/>
-      <outfile xil_pn:name="tld_jace_spartan6.par"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ptwx"/>
-      <outfile xil_pn:name="tld_jace_spartan6.unroutes"/>
-      <outfile xil_pn:name="tld_jace_spartan6.xpi"/>
-      <outfile xil_pn:name="tld_jace_spartan6_pad.csv"/>
-      <outfile xil_pn:name="tld_jace_spartan6_pad.txt"/>
-      <outfile xil_pn:name="tld_jace_spartan6_par.xrpt"/>
-    </transform>
-    <transform xil_pn:end_ts="1460483026" xil_pn:in_ck="-5273148268032026713" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1664592939731293453" xil_pn:start_ts="1460482979">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputRemoved"/>
-      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.bgn"/>
-      <outfile xil_pn:name="tld_jace_spartan6.drc"/>
-      <outfile xil_pn:name="tld_jace_spartan6.ut"/>
-      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
-      <outfile xil_pn:name="webtalk.log"/>
-      <outfile xil_pn:name="webtalk_pn.xml"/>
-    </transform>
-    <transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-8973030265980210795" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1460482966">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
-      <outfile xil_pn:name="tld_jace_spartan6.twr"/>
-      <outfile xil_pn:name="tld_jace_spartan6.twx"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/cores/JupiterAce/jupiter_ace.prj b/cores/JupiterAce/jupiter_ace.prj
new file mode 100644
index 0000000..ec3518e
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace.prj
@@ -0,0 +1,13 @@
+verilog work "tv80_reg.v"
+verilog work "tv80_mcode.v"
+verilog work "tv80_alu.v"
+verilog work "tv80_core.v"
+verilog work "tv80n.v"
+verilog work "rom.v"
+verilog work "ps2_port.v"
+verilog work "memorias.v"
+verilog work "jace_logic.v"
+verilog work "relojes.v"
+verilog work "keyboard_for_ace.v"
+verilog work "fpga_ace.v"
+verilog work "tld_jace_spartan6.v"
diff --git a/cores/JupiterAce/jupiter_ace.ut b/cores/JupiterAce/jupiter_ace.ut
new file mode 100644
index 0000000..a9facca
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace.ut
@@ -0,0 +1,30 @@
+-w
+-g Binary:no
+-g Compress
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/cores/JupiterAce/tld_jace_spartan6.v b/cores/JupiterAce/jupiter_ace.v
similarity index 100%
rename from cores/JupiterAce/tld_jace_spartan6.v
rename to cores/JupiterAce/jupiter_ace.v
diff --git a/cores/JupiterAce/jupiter_ace.xise b/cores/JupiterAce/jupiter_ace.xise
deleted file mode 100644
index d10d56d..0000000
--- a/cores/JupiterAce/jupiter_ace.xise
+++ /dev/null
@@ -1,427 +0,0 @@
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-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="tld_jace_spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="tld_jace_spartan6_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="tld_jace_spartan6_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="tld_jace_spartan6_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="tld_jace_spartan6_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/12.4/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="jupiter_ace_250" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-27T19:18:56" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E4DA2434A3A4AF5BDCC92DB051566E7" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/tld_jace_spartan6" xil_pn:name="pines_zxuno.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-    <file xil_pn:name="mapa_teclado_es.vh" xil_pn:type="FILE_VERILOG"/>
-  </autoManagedFiles>
-
-</project>
diff --git a/cores/JupiterAce/jupiter_ace.xst b/cores/JupiterAce/jupiter_ace.xst
new file mode 100644
index 0000000..f22e93a
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace.xst
@@ -0,0 +1,52 @@
+set -tmpdir "projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn jupiter_ace.prj
+-ofn jupiter_ace
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top jupiter_ace
+-opt_mode Area
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
new file mode 100644
index 0000000..a5f6e18
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
@@ -0,0 +1,89 @@
+# Clocks & debug
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+#NET "testled"         LOC="P2"   | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "r<2>"            LOC="P97"  | IOSTANDARD = LVCMOS33;
+NET "r<1>"            LOC="P95"  | IOSTANDARD = LVCMOS33;
+NET "r<0>"            LOC="P94"  | IOSTANDARD = LVCMOS33;
+NET "g<2>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "g<1>"            LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "g<0>"            LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "b<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "b<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "b<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "csync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
+#NET "vsync"           LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "stdn"            LOC="P51"  | IOSTANDARD = LVCMOS33;
+NET "stdnb"           LOC="P50"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "audio_out_left"  LOC="P98"  | IOSTANDARD = LVCMOS33;
+NET "audio_out_right" LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "clkps2"          LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2"         LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P57"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+#NET "sd_cs_n"         LOC="P78"  | IOSTANDARD = LVCMOS33;
+#NET "sd_clk"          LOC="P80"  | IOSTANDARD = LVCMOS33;
+#NET "sd_mosi"         LOC="P79"  | IOSTANDARD = LVCMOS33;
+#NET "sd_miso"         LOC="P81"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+#NET "joyup"           LOC="P74"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joydown"         LOC="P67"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyleft"         LOC="P59"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyright"        LOC="P58"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire"         LOC="P75"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+
+
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
new file mode 100644
index 0000000..7008ca4
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+#NET "testled"         LOC="P10"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "r<2>"            LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "r<1>"            LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "r<0>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "g<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "g<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "b<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "b<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "b<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+#NET "vsync"          LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "stdn"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+NET "stdnb"           LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "audio_out_left"  LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "audio_out_right" LOC="P9"   | IOSTANDARD = LVCMOS33;
+NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "clkps2"          LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P94"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+#NET "sd_cs_n"         LOC="P59"  | IOSTANDARD = LVCMOS33;
+#NET "sd_clk"          LOC="P75"  | IOSTANDARD = LVCMOS33;
+#NET "sd_mosi"         LOC="P74"  | IOSTANDARD = LVCMOS33;
+#NET "sd_miso"         LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+#NET "joyup"           LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joydown"         LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyleft"         LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyright"        LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire"         LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+# Otros
+
+
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
new file mode 100644
index 0000000..1fe1cb8
--- /dev/null
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
@@ -0,0 +1,91 @@
+# Clocks & debug
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "r<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "r<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "r<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "g<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "g<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "b<2>"            LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "b<1>"            LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "b<0>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+#NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "stdn"            LOC="P66"  | IOSTANDARD = LVCMOS33;
+NET "stdnb"           LOC="P67"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "audio_out_left"  LOC="P10"  | IOSTANDARD = LVCMOS33;
+NET "audio_out_right" LOC="P9"   | IOSTANDARD = LVCMOS33;
+NET "ear"             LOC="P94"  | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "clkps2"          LOC="P99"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+#NET "sram_addr<0>"    LOC="P141" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<1>"    LOC="P139" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<2>"    LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<3>"    LOC="P134" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<4>"    LOC="P133" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<5>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<6>"    LOC="P118" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<7>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<8>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<9>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<10>"   LOC="P104" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<11>"   LOC="P102" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<12>"   LOC="P101" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<13>"   LOC="P100" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<14>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<16>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<17>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<18>"   LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<1>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<2>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<3>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<4>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<5>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<6>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+#NET "sram_data<7>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+
+#NET "sram_we_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
+
+# SPI Flash
+NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+#NET "sd_cs_n"         LOC="P59"  | IOSTANDARD = LVCMOS33;
+#NET "sd_clk"          LOC="P75"  | IOSTANDARD = LVCMOS33;
+#NET "sd_mosi"         LOC="P74"  | IOSTANDARD = LVCMOS33;
+#NET "sd_miso"         LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+#NET "joyup"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joydown"         LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyleft"         LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyright"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire"         LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+
+
diff --git a/cores/JupiterAce/make.bat b/cores/JupiterAce/make.bat
new file mode 100644
index 0000000..809d5db
--- /dev/null
+++ b/cores/JupiterAce/make.bat
@@ -0,0 +1,7 @@
+SET machine=jupiter_ace
+SET ruta_ucf=jupiter_ace
+SET ruta_bat=..\
+call ..\genxst.bat
+call ..\generar.bat v2_v3
+call ..\generar.bat v4
+call ..\generar.bat Ap
diff --git a/cores/JupiterAce/par_usage_statistics.html b/cores/JupiterAce/par_usage_statistics.html
deleted file mode 100644
index e9e92b5..0000000
--- a/cores/JupiterAce/par_usage_statistics.html
+++ /dev/null
@@ -1,32 +0,0 @@
-<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
-<xtag-section name="ParStatistics">
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>2039</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>10425</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>12.3 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>16.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>17.8 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>25.6 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>26.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>8.6</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.4</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>6.0303</xtag-par-property-value></TD></TR>
-</xtag-section>
-</TABLE>
diff --git a/cores/JupiterAce/pines_zxuno.ucf b/cores/JupiterAce/pines_zxuno.ucf
deleted file mode 100644
index 7fea9f7..0000000
--- a/cores/JupiterAce/pines_zxuno.ucf
+++ /dev/null
@@ -1,82 +0,0 @@
-# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
-#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
-NET "clk50mhz" PERIOD=20 ns;
-#NET "clk12" PERIOD=83 ns;
-
-# Video output
-NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
-NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
-NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
-NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
-NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
-NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
-NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
-NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
-NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
-NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
-NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
-
-# Sound input/output
-NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
-NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
-NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
-
-# Keyboard and mouse
-NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;     # pin 1 DIN
-NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;    # pin 5 DIN
-#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;   # pin 6 DIN
-#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;  # pin 2 DIN
-
-# SRAM
-#NET "sram_addr<0>"  LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"  LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"  LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"  LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"  LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"  LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"  LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"  LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"  LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"  LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#
-#NET "sram_data<0>"  LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>"  LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>"  LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>"  LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>"  LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>"  LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>"  LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>"  LOC="P100" | IOSTANDARD = LVCMOS33;
-
-#NET "sram_we_n"     LOC="P134" | IOSTANDARD = LVCMOS33;
-
-# SPI Flash
-#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
-#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
-#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
-#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
-
-# SD/MMC
-#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
-#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
-#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
-#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
-
-# JOYSTICK
-#NET "joyup"    LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;    #JOY6
-#NET "joydown"  LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY4
-#NET "joyleft"  LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY3
-#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
-#NET "joyfire"  LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY7
diff --git a/cores/JupiterAce/pines_zxuno_Ap.ucf b/cores/JupiterAce/pines_zxuno_Ap.ucf
deleted file mode 100644
index 7fea9f7..0000000
--- a/cores/JupiterAce/pines_zxuno_Ap.ucf
+++ /dev/null
@@ -1,82 +0,0 @@
-# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
-#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
-NET "clk50mhz" PERIOD=20 ns;
-#NET "clk12" PERIOD=83 ns;
-
-# Video output
-NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
-NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
-NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
-NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
-NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
-NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
-NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
-NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
-NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
-NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
-NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
-
-# Sound input/output
-NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
-NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
-NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
-
-# Keyboard and mouse
-NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;     # pin 1 DIN
-NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;    # pin 5 DIN
-#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;   # pin 6 DIN
-#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;  # pin 2 DIN
-
-# SRAM
-#NET "sram_addr<0>"  LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"  LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"  LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"  LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"  LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"  LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"  LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"  LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"  LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"  LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#
-#NET "sram_data<0>"  LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>"  LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>"  LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>"  LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>"  LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>"  LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>"  LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>"  LOC="P100" | IOSTANDARD = LVCMOS33;
-
-#NET "sram_we_n"     LOC="P134" | IOSTANDARD = LVCMOS33;
-
-# SPI Flash
-#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
-#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
-#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
-#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
-
-# SD/MMC
-#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
-#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
-#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
-#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
-
-# JOYSTICK
-#NET "joyup"    LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;    #JOY6
-#NET "joydown"  LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY4
-#NET "joyleft"  LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY3
-#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
-#NET "joyfire"  LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY7
diff --git a/cores/JupiterAce/pines_zxuno_v4.ucf b/cores/JupiterAce/pines_zxuno_v4.ucf
deleted file mode 100644
index 7862a72..0000000
--- a/cores/JupiterAce/pines_zxuno_v4.ucf
+++ /dev/null
@@ -1,85 +0,0 @@
-# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
-#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
-NET "clk50mhz" PERIOD=20 ns;
-#NET "clk12" PERIOD=83 ns;
-
-# Video output
-NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
-NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
-NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
-NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
-NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
-NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
-NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
-NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
-NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
-NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
-NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
-
-# Sound input/output
-NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
-NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
-NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
-
-# Keyboard and mouse
-NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;     # pin 1 DIN
-NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;    # pin 5 DIN
-#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;   # pin 6 DIN
-#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;  # pin 2 DIN
-
-# SRAM
-#NET "sram_addr<0>"  LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"  LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"  LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"  LOC="P134" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"  LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"  LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"  LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"  LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"  LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"  LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
-
-#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
-
-#NET "sram_we_n"    LOC="P121" | IOSTANDARD = LVCMOS33;
-
-# SPI Flash
-#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
-#NET "flash_clk"  LOC="P70" | IOSTANDARD = LVCMOS33;
-#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
-#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
-
-# SD/MMC
-#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
-#NET "sd_clk"  LOC="P75" | IOSTANDARD = LVCMOS33;
-#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
-#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
-
-# JOYSTICK
-#NET "joyup"    LOC="P1"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY6
-#NET "joydown"  LOC="P5"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY4
-#NET "joyleft"  LOC="P6"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY3
-#NET "joyright" LOC="P7"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY2
-#NET "joyfire"  LOC="P2"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY7
-#NET "btn2"    LOC="P8"  | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY5
diff --git a/cores/JupiterAce/relojes.v b/cores/JupiterAce/relojes.v
new file mode 100644
index 0000000..592c2c2
--- /dev/null
+++ b/cores/JupiterAce/relojes.v
@@ -0,0 +1,145 @@
+// file: tres_relojes.v
+// 
+// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* CORE_GENERATION_INFO = "tres_relojes,clk_wiz_v1_8,{component_name=tres_relojes,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
+module cuatro_relojes
+ (// Clock in ports
+  input wire        CLK_IN1,
+  // Clock out ports
+  output wire       CLK_OUT1,
+  output wire       CLK_OUT2,
+  output wire       CLK_OUT3,
+  output wire       CLK_OUT4
+ );
+
+  wire clkin1,clkout0,clkout1,clkout2,clkout3;
+  // Input buffering
+  //------------------------------------
+  IBUFG clkin1_buf
+   (.O (clkin1),
+    .I (CLK_IN1));
+
+
+  // Clocking primitive
+  //------------------------------------
+  // Instantiation of the PLL primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        locked_unused;
+  wire        clkfbout;
+  wire        clkfbout_buf;
+  wire        clkout4_unused;
+  wire        clkout5_unused;
+
+  PLL_BASE
+  #(.BANDWIDTH              ("OPTIMIZED"),
+    .CLK_FEEDBACK           ("CLKFBOUT"),
+    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
+    .DIVCLK_DIVIDE          (1),
+    .CLKFBOUT_MULT          (8),
+    .CLKFBOUT_PHASE         (0.000),
+    .CLKOUT0_DIVIDE         (15),
+    .CLKOUT0_PHASE          (0.000),
+    .CLKOUT0_DUTY_CYCLE     (0.500),
+    .CLKOUT1_DIVIDE         (60),
+    .CLKOUT1_PHASE          (0.000),
+    .CLKOUT1_DUTY_CYCLE     (0.500),
+    .CLKOUT2_DIVIDE         (120),
+    .CLKOUT2_PHASE          (0.000),
+    .CLKOUT3_DIVIDE         (30),
+    .CLKOUT3_PHASE          (0.000),
+    .CLKOUT2_DUTY_CYCLE     (0.500),
+    .CLKIN_PERIOD           (20.0),
+    .REF_JITTER             (0.010))
+  pll_base_inst
+    // Output clocks
+   (.CLKFBOUT              (clkfbout),
+    .CLKOUT0               (clkout0),
+    .CLKOUT1               (clkout1),
+    .CLKOUT2               (clkout2),
+    .CLKOUT3               (clkout3),
+    .CLKOUT4               (clkout4_unused),
+    .CLKOUT5               (clkout5_unused),
+    .LOCKED                (locked_unused),
+    .RST                   (1'b0),
+     // Input clock control
+    .CLKFBIN               (clkfbout_buf),
+    .CLKIN                 (clkin1));
+
+
+  // Output buffering
+  //-----------------------------------
+  BUFG clkf_buf
+   (.O (clkfbout_buf),
+    .I (clkfbout));
+
+
+  BUFG clkout1_buf
+   (.O   (CLK_OUT1),
+    .I   (clkout0));
+
+
+  BUFG clkout2_buf
+   (.O   (CLK_OUT2),
+    .I   (clkout1));
+
+  BUFG clkout3_buf
+   (.O   (CLK_OUT3),
+    .I   (clkout2));
+
+  BUFG clkout4_buf
+   (.O   (CLK_OUT4),
+    .I   (clkout3));
+
+endmodule
diff --git a/cores/generar.bat b/cores/generar.bat
new file mode 100644
index 0000000..14dfb84
--- /dev/null
+++ b/cores/generar.bat
@@ -0,0 +1,6 @@
+call %ruta_bat%ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc %ruta_ucf%_zxuno_%1.ucf -p xc6slx9-tqg144-2 %machine%.ngc %machine%.ngd
+call %ruta_bat%map      -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %machine%_map.ncd %machine%.ngd %machine%.pcf
+call %ruta_bat%par      -intstyle ise -w -ol high -mt 4 %machine%_map.ncd %machine%.ncd %machine%.pcf
+call %ruta_bat%trce     -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %machine%.twx %machine%.ncd -o %machine%.twr %machine%.pcf
+call %ruta_bat%bitgen   -intstyle ise -f %machine%.ut %machine%.ncd
+copy /y %machine%.bit %machine%.%1.bit
diff --git a/cores/genxst.bat b/cores/genxst.bat
new file mode 100644
index 0000000..5d87234
--- /dev/null
+++ b/cores/genxst.bat
@@ -0,0 +1,2 @@
+if not exist projnav.tmp mkdir projnav.tmp
+call %ruta_bat%xst -intstyle ise -ifn %machine%.xst -ofn %machine%.syr