diff --git a/cores/MasterSystem/src/sms_rgb_zxuno_Ap.ucf b/cores/MasterSystem/src/sms_rgb_zxuno_Ap.ucf
index d39ec1b..6e2051e 100644
--- a/cores/MasterSystem/src/sms_rgb_zxuno_Ap.ucf
+++ b/cores/MasterSystem/src/sms_rgb_zxuno_Ap.ucf
@@ -18,9 +18,9 @@ NET NTSC              LOC="P51"  | IOSTANDARD = LVCMOS33;
 NET PAL               LOC="P50"  | IOSTANDARD = LVCMOS33;
 
 # Sound input/output
-NET "audio_l"         LOC="P98"   | IOSTANDARD = LVCMOS33;                               
-NET "audio_r"         LOC="P99"   | IOSTANDARD = LVCMOS33;                               
-#NET "ear"             LOC="P1"    | IOSTANDARD = LVCMOS33;
+NET "audio_l"         LOC="P98"  | IOSTANDARD = LVCMOS33;
+NET "audio_r"         LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
 
 # Keyboard and mouse
 #NET "clkps2"          LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
diff --git a/cores/MasterSystem/src/sms_rgb_zxuno_v2.ucf b/cores/MasterSystem/src/sms_rgb_zxuno_v2.ucf
index 06c336c..aa74be8 100644
--- a/cores/MasterSystem/src/sms_rgb_zxuno_v2.ucf
+++ b/cores/MasterSystem/src/sms_rgb_zxuno_v2.ucf
@@ -3,23 +3,23 @@ NET CLK               LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
 NET "led"             LOC="P10"  | IOSTANDARD = LVCMOS33;
 
 # Video output
-NET "red(2)"          LOC="P93"  | IOSTANDARD = LVCMOS33;                              
-NET "red(1)"          LOC="P92"  | IOSTANDARD = LVCMOS33;                                
-NET "red(0)"          LOC="P88"  | IOSTANDARD = LVCMOS33;                               
-NET "green(2)"        LOC="P84"  | IOSTANDARD = LVCMOS33;                               
-NET "green(1)"        LOC="P83"  | IOSTANDARD = LVCMOS33;                                
-NET "green(0)"        LOC="P82"  | IOSTANDARD = LVCMOS33;                                
-NET "blue(2)"         LOC="P81"  | IOSTANDARD = LVCMOS33;                                
-NET "blue(1)"         LOC="P80"  | IOSTANDARD = LVCMOS33;                                
-NET "blue(0)"         LOC="P79"  | IOSTANDARD = LVCMOS33;                               
-NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;                                
-NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;                                
+NET "red(2)"          LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "red(1)"          LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "red(0)"          LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "green(2)"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "green(1)"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "green(0)"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "blue(2)"         LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "blue(1)"         LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "blue(0)"         LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET NTSC              LOC="P67"  | IOSTANDARD = LVCMOS33;
 NET PAL               LOC="P66"  | IOSTANDARD = LVCMOS33;
 
 # Sound input/output
-NET "audio_l"   LOC="P8"   | IOSTANDARD=LVCMOS33;                               
-NET "audio_r"   LOC="P9"   | IOSTANDARD=LVCMOS33;                               
+NET "audio_l"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;
 #NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
 
 # Keyboard and mouse
@@ -83,7 +83,7 @@ NET "j1_left"         LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
 NET "j1_right"        LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
 NET "j1_tr"           LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
 NET "j1_tl"           LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
-#NET "joyfire3"       LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 
diff --git a/cores/MasterSystem/src/sms_rgb_zxuno_v3.ucf b/cores/MasterSystem/src/sms_rgb_zxuno_v3.ucf
index c529d61..41efd6c 100644
--- a/cores/MasterSystem/src/sms_rgb_zxuno_v3.ucf
+++ b/cores/MasterSystem/src/sms_rgb_zxuno_v3.ucf
@@ -18,8 +18,8 @@ NET NTSC              LOC="P67"  | IOSTANDARD = LVCMOS33;
 NET PAL               LOC="P66"  | IOSTANDARD = LVCMOS33;
 
 # Sound input/output
-NET "audio_l"         LOC="P8"   | IOSTANDARD = LVCMOS33;                               
-NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;                               
+NET "audio_l"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;
 #NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
 
 # Keyboard and mouse
@@ -71,10 +71,10 @@ NET ram_WE_n          LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
 #NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
 
 # SD/MMC
-NET "spi_cs_n"        LOC="P59"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_sclk"        LOC="P75"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_di"          LOC="P74"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_do"          LOC="P78"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
 
 # JOYSTICK
 NET "j1_up"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
@@ -89,3 +89,6 @@ NET "j1_tr"           LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 
+
+
+
diff --git a/cores/MasterSystem/src/sms_rgb_zxuno_v4.ucf b/cores/MasterSystem/src/sms_rgb_zxuno_v4.ucf
index 84b51be..39fd8b8 100644
--- a/cores/MasterSystem/src/sms_rgb_zxuno_v4.ucf
+++ b/cores/MasterSystem/src/sms_rgb_zxuno_v4.ucf
@@ -18,8 +18,8 @@ NET NTSC              LOC="P66"  | IOSTANDARD = LVCMOS33;
 NET PAL               LOC="P67"  | IOSTANDARD = LVCMOS33;
 
 # Sound input/output
-NET "audio_l"         LOC="P10"  | IOSTANDARD = LVCMOS33;                               
-NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;                               
+NET "audio_l"         LOC="P10"  | IOSTANDARD = LVCMOS33;
+NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;
 #NET "ear"             LOC="P94"  | IOSTANDARD = LVCMOS33;
 
 # Keyboard and mouse
@@ -71,10 +71,10 @@ NET ram_WE_n          LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
 #NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
 
 # SD/MMC
-NET "spi_cs_n"        LOC="P59"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_sclk"        LOC="P75"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_di"          LOC="P74"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
-NET "spi_do"          LOC="P78"  | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
 
 # JOYSTICK
 NET "j1_up"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
diff --git a/cores/NES/src/ZXUNO_NES_v2.ucf b/cores/NES/src/ZXUNO_NES_v2.ucf
deleted file mode 100644
index 08114a2..0000000
--- a/cores/NES/src/ZXUNO_NES_v2.ucf
+++ /dev/null
@@ -1,134 +0,0 @@
-
-
-NET "vga_b[0]" LOC = P79;
-NET "vga_b[0]" IOSTANDARD = LVCMOS33;
-NET "vga_b[1]" LOC = P80;
-NET "vga_b[1]" IOSTANDARD = LVCMOS33;
-NET "vga_b[2]" LOC = P81;
-NET "vga_b[2]" IOSTANDARD = LVCMOS33;
-NET "vga_g[0]" LOC = P82;
-NET "vga_g[0]" IOSTANDARD = LVCMOS33;
-NET "vga_g[1]" LOC = P83;
-NET "vga_g[1]" IOSTANDARD = LVCMOS33;
-NET "vga_g[2]" LOC = P84;
-NET "vga_g[2]" IOSTANDARD = LVCMOS33;
-NET "vga_r[0]" LOC = P88;
-NET "vga_r[0]" IOSTANDARD = LVCMOS33;
-NET "vga_r[1]" LOC = P92;
-NET "vga_r[1]" IOSTANDARD = LVCMOS33;
-NET "vga_r[2]" LOC = P93;
-NET "vga_r[2]" IOSTANDARD = LVCMOS33;
-NET "CLOCK_50" LOC = P55;
-NET "CLOCK_50" IOSTANDARD = LVCMOS33;
-
-NET "vga_v" LOC = P85;
-NET "vga_v" IOSTANDARD = LVCMOS33;
-NET "vga_h" LOC = P87;
-NET "vga_h" IOSTANDARD = LVCMOS33;
-NET "led" LOC = P10;
-NET "led" IOSTANDARD = LVCMOS33;
-NET "AUDIO_L" LOC = P8;
-NET "AUDIO_L" IOSTANDARD = LVCMOS33;
-NET "AUDIO_R" LOC = P9;
-NET "AUDIO_R" IOSTANDARD = LVCMOS33;
-
-#NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
-#NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
-
-NET ram_a(0)  LOC="P115"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR0
-NET ram_a(1)  LOC="P116"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR1
-NET ram_a(2)  LOC="P117"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR2
-NET ram_a(3)  LOC="P119"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR3
-NET ram_a(4)  LOC="P120"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR4
-NET ram_a(5)  LOC="P123"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR5
-NET ram_a(6)  LOC="P126"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR6
-NET ram_a(7)  LOC="P131"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR7
-NET ram_a(8)  LOC="P127"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR8
-NET ram_a(9)  LOC="P124"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR9
-NET ram_a(10) LOC="P118"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR10
-NET ram_a(11) LOC="P121"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR11
-NET ram_a(12) LOC="P133"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR12
-NET ram_a(13) LOC="P132"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR13
-NET ram_a(14) LOC="P137"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR14
-NET ram_a(15) LOC="P140"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR15
-NET ram_a(16) LOC="P139"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR16
-NET ram_a(17) LOC="P141"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR17
-NET ram_a(18) LOC="P138"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR18
-
-NET ram_d(0)  LOC="P114"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA0
-NET ram_d(1)  LOC="P112"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA1
-NET ram_d(2)  LOC="P111"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA2
-NET ram_d(3)  LOC="P99"    | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA3
-NET ram_d(4)  LOC="P100"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA4
-NET ram_d(5)  LOC="P101"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA5
-NET ram_d(6)  LOC="P102"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA6
-NET ram_d(7)  LOC="P104"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA7
-
-NET ram_WE_n  LOC="P134" | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                  # nWE
-
-NET "P_A" LOC = P143;
-NET "P_A" IOSTANDARD = LVCMOS33;
-NET "P_A" PULLUP;
-NET "P_D" LOC = P1;
-NET "P_D" IOSTANDARD = LVCMOS33;
-NET "P_D" PULLUP;
-NET "P_L" LOC = P2;
-NET "P_L" IOSTANDARD = LVCMOS33;
-NET "P_L" PULLUP;
-NET "P_R" LOC = P5;
-NET "P_R" IOSTANDARD = LVCMOS33;
-NET "P_R" PULLUP;
-NET "P_U" LOC = P142;
-NET "P_U" IOSTANDARD = LVCMOS33;
-NET "P_U" PULLUP;
-NET "P_tr" LOC = P6;
-NET "P_tr" IOSTANDARD = LVCMOS33;
-NET "P_tr" PULLUP;
-
-
-NET "PS2_CLK" LOC = P98;
-NET "PS2_CLK" IOSTANDARD = LVCMOS33;
-NET "PS2_CLK" PULLUP;
-NET "PS2_DAT" LOC = P97;
-NET "PS2_DAT" IOSTANDARD = LVCMOS33;
-NET "PS2_DAT" PULLUP;
-
-
-NET "SPI_MOSI" LOC = P74;
-NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "SPI_MOSI" DRIVE = 8;
-NET "SPI_MOSI" SLEW = FAST;
-NET "SPI_MISO" LOC = P78;
-NET "SPI_MISO" IOSTANDARD = LVCMOS33;
-NET "SPI_MISO" DRIVE = 8;
-NET "SPI_MISO" SLEW = FAST;
-NET "SPI_CLK" LOC = P75;
-NET "SPI_CLK" IOSTANDARD = LVCMOS33;
-NET "SPI_CLK" DRIVE = 8;
-NET "SPI_CLK" SLEW = FAST;
-NET "SPI_CS" LOC = P59;
-NET "SPI_CS" IOSTANDARD = LVCMOS33;
-NET "SPI_CS" DRIVE = 8;
-NET "SPI_CS" SLEW = FAST;
-
-
-#NET "PAL" LOC = P66;
-#NET "PAL" IOSTANDARD = LVCMOS33;
-#NET "NTSC" LOC = P67;
-#NET "NTSC" IOSTANDARD = LVCMOS33;
-
-
-#DEBUG
-#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
-#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
-#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
diff --git a/cores/NES/src/ZXUNO_NES_v3.ucf b/cores/NES/src/ZXUNO_NES_v3.ucf
deleted file mode 100644
index 4597fc3..0000000
--- a/cores/NES/src/ZXUNO_NES_v3.ucf
+++ /dev/null
@@ -1,134 +0,0 @@
-
-
-NET "vga_b[0]" LOC = P79;
-NET "vga_b[0]" IOSTANDARD = LVCMOS33;
-NET "vga_b[1]" LOC = P80;
-NET "vga_b[1]" IOSTANDARD = LVCMOS33;
-NET "vga_b[2]" LOC = P81;
-NET "vga_b[2]" IOSTANDARD = LVCMOS33;
-NET "vga_g[0]" LOC = P82;
-NET "vga_g[0]" IOSTANDARD = LVCMOS33;
-NET "vga_g[1]" LOC = P83;
-NET "vga_g[1]" IOSTANDARD = LVCMOS33;
-NET "vga_g[2]" LOC = P84;
-NET "vga_g[2]" IOSTANDARD = LVCMOS33;
-NET "vga_r[0]" LOC = P88;
-NET "vga_r[0]" IOSTANDARD = LVCMOS33;
-NET "vga_r[1]" LOC = P92;
-NET "vga_r[1]" IOSTANDARD = LVCMOS33;
-NET "vga_r[2]" LOC = P93;
-NET "vga_r[2]" IOSTANDARD = LVCMOS33;
-NET "CLOCK_50" LOC = P55;
-NET "CLOCK_50" IOSTANDARD = LVCMOS33;
-
-NET "vga_v" LOC = P85;
-NET "vga_v" IOSTANDARD = LVCMOS33;
-NET "vga_h" LOC = P87;
-NET "vga_h" IOSTANDARD = LVCMOS33;
-NET "led" LOC = P10;
-NET "led" IOSTANDARD = LVCMOS33;
-NET "AUDIO_L" LOC = P8;
-NET "AUDIO_L" IOSTANDARD = LVCMOS33;
-NET "AUDIO_R" LOC = P9;
-NET "AUDIO_R" IOSTANDARD = LVCMOS33;
-
-# NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
-# NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
-
-NET ram_a(0)  LOC="P143"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR0
-NET ram_a(1)  LOC="P142"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR1
-NET ram_a(2)  LOC="P141"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR2
-NET ram_a(3)  LOC="P140"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR3
-NET ram_a(4)  LOC="P139"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR4
-NET ram_a(5)  LOC="P104"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR5
-NET ram_a(6)  LOC="P102"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR6
-NET ram_a(7)  LOC="P101"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR7
-NET ram_a(8)  LOC="P100"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR8
-NET ram_a(9)  LOC="P99"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR9
-NET ram_a(10) LOC="P112"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR10
-NET ram_a(11) LOC="P114"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR11
-NET ram_a(12) LOC="P115"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR12
-NET ram_a(13) LOC="P116"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR13
-NET ram_a(14) LOC="P117"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR14
-NET ram_a(15) LOC="P131"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR15
-NET ram_a(16) LOC="P133"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR16
-NET ram_a(17) LOC="P134"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR17
-NET ram_a(18) LOC="P137"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # ADDR18
-
-NET ram_d(0)  LOC="P132"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA0
-NET ram_d(1)  LOC="P126"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA1
-NET ram_d(2)  LOC="P123"  	| IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA2
-NET ram_d(3)  LOC="P120"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA3
-NET ram_d(4)  LOC="P119"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA4
-NET ram_d(5)  LOC="P121"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA5
-NET ram_d(6)  LOC="P124"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA6
-NET ram_d(7)  LOC="P127"   | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                # DATA7
-
-NET ram_WE_n  LOC="P118" | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                  # nWE
-
-NET "P_A" LOC = P39;
-NET "P_A" IOSTANDARD = LVCMOS33;
-NET "P_A" PULLUP;
-NET "P_D" LOC = P5;
-NET "P_D" IOSTANDARD = LVCMOS33;
-NET "P_D" PULLUP;
-NET "P_L" LOC = P6;
-NET "P_L" IOSTANDARD = LVCMOS33;
-NET "P_L" PULLUP;
-NET "P_R" LOC = P7;
-NET "P_R" IOSTANDARD = LVCMOS33;
-NET "P_R" PULLUP;
-NET "P_U" LOC = P1;
-NET "P_U" IOSTANDARD = LVCMOS33;
-NET "P_U" PULLUP;
-NET "P_tr" LOC = P2;
-NET "P_tr" IOSTANDARD = LVCMOS33;
-NET "P_tr" PULLUP;
-
-
-NET "PS2_CLK" LOC = P98;
-NET "PS2_CLK" IOSTANDARD = LVCMOS33;
-NET "PS2_CLK" PULLUP;
-NET "PS2_DAT" LOC = P97;
-NET "PS2_DAT" IOSTANDARD = LVCMOS33;
-NET "PS2_DAT" PULLUP;
-
-
-NET "SPI_MOSI" LOC = P74;
-NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "SPI_MOSI" DRIVE = 8;
-NET "SPI_MOSI" SLEW = FAST;
-NET "SPI_MISO" LOC = P78;
-NET "SPI_MISO" IOSTANDARD = LVCMOS33;
-NET "SPI_MISO" DRIVE = 8;
-NET "SPI_MISO" SLEW = FAST;
-NET "SPI_CLK" LOC = P75;
-NET "SPI_CLK" IOSTANDARD = LVCMOS33;
-NET "SPI_CLK" DRIVE = 8;
-NET "SPI_CLK" SLEW = FAST;
-NET "SPI_CS" LOC = P59;
-NET "SPI_CS" IOSTANDARD = LVCMOS33;
-NET "SPI_CS" DRIVE = 8;
-NET "SPI_CS" SLEW = FAST;
-
-
-#NET "PAL" LOC = P66;
-#NET "PAL" IOSTANDARD = LVCMOS33;
-#NET "NTSC" LOC = P67;
-#NET "NTSC" IOSTANDARD = LVCMOS33;
-
-
-#DEBUG
-#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
-#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
-#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
\ No newline at end of file
diff --git a/cores/NES/src/ZXUNO_NES_v4.ucf b/cores/NES/src/ZXUNO_NES_v4.ucf
deleted file mode 100644
index d069707..0000000
--- a/cores/NES/src/ZXUNO_NES_v4.ucf
+++ /dev/null
@@ -1,134 +0,0 @@
-#PIN "clock_21mhz/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
-
-NET "vga_r[0]" LOC = P79;
-NET "vga_r[0]" IOSTANDARD = LVCMOS33;
-NET "vga_r[1]" LOC = P80;
-NET "vga_r[1]" IOSTANDARD = LVCMOS33;
-NET "vga_r[2]" LOC = P81;
-NET "vga_r[2]" IOSTANDARD = LVCMOS33;
-NET "vga_g[0]" LOC = P82;
-NET "vga_g[0]" IOSTANDARD = LVCMOS33;
-NET "vga_g[1]" LOC = P83;
-NET "vga_g[1]" IOSTANDARD = LVCMOS33;
-NET "vga_g[2]" LOC = P84;
-NET "vga_g[2]" IOSTANDARD = LVCMOS33;
-NET "vga_b[0]" LOC = P88;
-NET "vga_b[0]" IOSTANDARD = LVCMOS33;
-NET "vga_b[1]" LOC = P92;
-NET "vga_b[1]" IOSTANDARD = LVCMOS33;
-NET "vga_b[2]" LOC = P93;
-NET "vga_b[2]" IOSTANDARD = LVCMOS33;
-NET "CLOCK_50" LOC = P55;
-NET "CLOCK_50" IOSTANDARD = LVCMOS33;
-
-NET "vga_v" LOC = P85;
-NET "vga_v" IOSTANDARD = LVCMOS33;
-NET "vga_h" LOC = P87;
-NET "vga_h" IOSTANDARD = LVCMOS33;
-NET "led" LOC = P11;
-NET "led" IOSTANDARD = LVCMOS33;
-NET "AUDIO_L" LOC = P10;
-NET "AUDIO_L" IOSTANDARD = LVCMOS33;
-NET "AUDIO_R" LOC = P9;
-NET "AUDIO_R" IOSTANDARD = LVCMOS33;
-
-# NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
-# NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
-NET "ram_a<0>"  LOC="P141" | IOSTANDARD = LVCMOS33;
-NET "ram_a<1>"  LOC="P139" | IOSTANDARD = LVCMOS33;
-NET "ram_a<2>"  LOC="P137" | IOSTANDARD = LVCMOS33;
-NET "ram_a<3>"  LOC="P134" | IOSTANDARD = LVCMOS33;
-NET "ram_a<4>"  LOC="P133" | IOSTANDARD = LVCMOS33;
-NET "ram_a<5>"  LOC="P120" | IOSTANDARD = LVCMOS33;
-NET "ram_a<6>"  LOC="P118" | IOSTANDARD = LVCMOS33;
-NET "ram_a<7>"  LOC="P116" | IOSTANDARD = LVCMOS33;
-NET "ram_a<8>"  LOC="P114" | IOSTANDARD = LVCMOS33;
-NET "ram_a<9>"  LOC="P112"  | IOSTANDARD = LVCMOS33;
-NET "ram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
-NET "ram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
-NET "ram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
-NET "ram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
-NET "ram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
-NET "ram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
-NET "ram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
-NET "ram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
-NET "ram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
-
-NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
-NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
-NET "ram_d<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
-NET "ram_d<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
-NET "ram_d<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
-NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
-NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
-NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
-
-NET ram_WE_n  LOC="P121" | IOSTANDARD=LVCMOS33 | SLEW=FAST;                                  # nWE
-
-NET "P_A" LOC = P8;
-NET "P_A" IOSTANDARD = LVCMOS33;
-NET "P_A" PULLUP;
-NET "P_D" LOC = P5;
-NET "P_D" IOSTANDARD = LVCMOS33;
-NET "P_D" PULLUP;
-NET "P_L" LOC = P6;
-NET "P_L" IOSTANDARD = LVCMOS33;
-NET "P_L" PULLUP;
-NET "P_R" LOC = P7;
-NET "P_R" IOSTANDARD = LVCMOS33;
-NET "P_R" PULLUP;
-NET "P_U" LOC = P1;
-NET "P_U" IOSTANDARD = LVCMOS33;
-NET "P_U" PULLUP;
-NET "P_tr" LOC = P2;
-NET "P_tr" IOSTANDARD = LVCMOS33;
-NET "P_tr" PULLUP;
-
-
-NET "PS2_CLK" LOC = P99;
-NET "PS2_CLK" IOSTANDARD = LVCMOS33;
-NET "PS2_CLK" PULLUP;
-NET "PS2_DAT" LOC = P98;
-NET "PS2_DAT" IOSTANDARD = LVCMOS33;
-NET "PS2_DAT" PULLUP;
-
-
-NET "SPI_MOSI" LOC = P74;
-NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "SPI_MOSI" DRIVE = 8;
-NET "SPI_MOSI" SLEW = FAST;
-NET "SPI_MISO" LOC = P78;
-NET "SPI_MISO" IOSTANDARD = LVCMOS33;
-NET "SPI_MISO" DRIVE = 8;
-NET "SPI_MISO" SLEW = FAST;
-NET "SPI_CLK" LOC = P75;
-NET "SPI_CLK" IOSTANDARD = LVCMOS33;
-NET "SPI_CLK" DRIVE = 8;
-NET "SPI_CLK" SLEW = FAST;
-NET "SPI_CS" LOC = P59;
-NET "SPI_CS" IOSTANDARD = LVCMOS33;
-NET "SPI_CS" DRIVE = 8;
-NET "SPI_CS" SLEW = FAST;
-
-#NET "PAL" LOC = P67;
-#NET "PAL" IOSTANDARD = LVCMOS33;
-#NET "NTSC" LOC = P66;
-#NET "NTSC" IOSTANDARD = LVCMOS33;
-
-
-#DEBUG
-#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
-#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
-#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
-#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
-#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
\ No newline at end of file
diff --git a/cores/NES/src/nes_zxuno_Ap.ucf b/cores/NES/src/nes_zxuno_Ap.ucf
new file mode 100644
index 0000000..0db2a3b
--- /dev/null
+++ b/cores/NES/src/nes_zxuno_Ap.ucf
@@ -0,0 +1,105 @@
+#UCF para el ZX-UNO
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "led"             LOC="P2"   | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "vga_r[2]"        LOC="P97"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[1]"        LOC="P95"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[0]"        LOC="P94"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[2]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[1]"        LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[0]"        LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "vga_h"           LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vga_v"           LOC="P92"  | IOSTANDARD = LVCMOS33;
+#NET "NTSC"            LOC="P51"  | IOSTANDARD = LVCMOS33;
+#NET "PAL"             LOC="P50"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P98"  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P99"  | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P1"   | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P57"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET ram_a(0)          LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(1)          LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(2)          LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(3)          LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(4)          LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(5)          LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(6)          LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(7)          LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(8)          LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(9)          LOC="P124  | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(10)         LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(11)         LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(12)         LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(13)         LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(14)         LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(15)         LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(16)         LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(17)         LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(18)         LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+NET ram_d(0)          LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(1)          LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(2)          LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(3)          LOC="P105" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(4)          LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(5)          LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(6)          LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(7)          LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+                           
+NET ram_WE_n          LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_CLK"         LOC="P80"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MOSI"        LOC="P79"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MISO"        LOC="P81"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P74"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P67"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P59"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P58"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P75"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+#DEBUG
+# NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
+# NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
+
+#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
+#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
+#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
diff --git a/cores/NES/src/nes_zxuno_v2.ucf b/cores/NES/src/nes_zxuno_v2.ucf
new file mode 100644
index 0000000..a513f9b
--- /dev/null
+++ b/cores/NES/src/nes_zxuno_v2.ucf
@@ -0,0 +1,105 @@
+#UCF para el ZX-UNO
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "led"             LOC="P10"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "vga_r[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "vga_h"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vga_v"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+#NET "NTSC"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+#NET "PAL"             LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P94"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET ram_a(0)          LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(1)          LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(2)          LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(3)          LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(4)          LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(5)          LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(6)          LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(7)          LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(8)          LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(9)          LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(10)         LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(11)         LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(12)         LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(13)         LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(14)         LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(15)         LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(16)         LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(17)         LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(18)         LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+NET ram_d(0)          LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(1)          LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(2)          LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(3)          LOC="P99"  | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(4)          LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(5)          LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(6)          LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(7)          LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+NET ram_WE_n          LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+#DEBUG
+#NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
+#NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
+
+#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
+#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
+#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
diff --git a/cores/NES/src/nes_zxuno_v3.ucf b/cores/NES/src/nes_zxuno_v3.ucf
new file mode 100644
index 0000000..2d09355
--- /dev/null
+++ b/cores/NES/src/nes_zxuno_v3.ucf
@@ -0,0 +1,105 @@
+#UCF para el ZX-UNO
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "led"             LOC="P10"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "vga_r[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "vga_h"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vga_v"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+#NET "NTSC"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+#NET "PAL"             LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P8"   | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P105" | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P94"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET ram_a(0)          LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(1)          LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(2)          LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(3)          LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(4)          LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(5)          LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(6)          LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(7)          LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(8)          LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(9)          LOC="P99"  | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(10)         LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(11)         LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(12)         LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(13)         LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(14)         LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(15)         LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(16)         LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(17)         LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(18)         LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+
+NET ram_d(0)          LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(1)          LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(2)          LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(3)          LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(4)          LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(5)          LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(6)          LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(7)          LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+NET ram_WE_n          LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire2"        LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+#DEBUG
+# NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
+# NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
+
+#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
+#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
+#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
diff --git a/cores/NES/src/nes_zxuno_v4.ucf b/cores/NES/src/nes_zxuno_v4.ucf
new file mode 100644
index 0000000..5ac500c
--- /dev/null
+++ b/cores/NES/src/nes_zxuno_v4.ucf
@@ -0,0 +1,105 @@
+#UCF para el ZX-UNO
+NET "CLOCK_50"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "led"             LOC="P11"  | IOSTANDARD = LVCMOS33;
+
+# Video output
+NET "vga_r[2]"        LOC="P81"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[1]"        LOC="P80"  | IOSTANDARD = LVCMOS33;
+NET "vga_r[0]"        LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[2]"        LOC="P84"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[1]"        LOC="P83"  | IOSTANDARD = LVCMOS33;
+NET "vga_g[0]"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[2]"        LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[1]"        LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "vga_b[0]"        LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "vga_h"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vga_v"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+#NET "NTSC"            LOC="P67"  | IOSTANDARD = LVCMOS33;
+#NET "PAL"             LOC="P66"  | IOSTANDARD = LVCMOS33;
+
+# Sound input/output
+NET "AUDIO_L"         LOC="P10"  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_R"         LOC="P9"   | IOSTANDARD = LVCMOS33;
+#NET "ear"             LOC="P94"  | IOSTANDARD = LVCMOS33;
+
+# Keyboard and mouse
+NET "PS2_CLK"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "PS2_DAT"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mouseclk"        LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+# SRAM
+NET ram_a(0)          LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(1)          LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(2)          LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(3)          LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(4)          LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(5)          LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(6)          LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(7)          LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(8)          LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(9)          LOC="P112  | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(10)         LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(11)         LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(12)         LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(13)         LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(14)         LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(15)         LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(16)         LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(17)         LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_a(18)         LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+
+NET ram_d(0)          LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(1)          LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(2)          LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(3)          LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(4)          LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(5)          LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(6)          LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+NET ram_d(7)          LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+NET ram_WE_n          LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
+
+# SPI Flash
+#NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
+#NET "flash_clk"       LOC="P70"  | IOSTANDARD = LVCMOS33;
+#NET "flash_mosi"      LOC="P64"  | IOSTANDARD = LVCMOS33;
+#NET "flash_miso"      LOC="P65"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext1"      LOC="P62"  | IOSTANDARD = LVCMOS33;
+#NET "flash_ext2"      LOC="P61"  | IOSTANDARD = LVCMOS33;
+
+# SD/MMC
+NET "SPI_CS"          LOC="P59"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_CLK"         LOC="P75"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MOSI"        LOC="P74"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+NET "SPI_MISO"        LOC="P78"  | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
+
+# JOYSTICK
+NET "P_U"             LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_D"             LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_L"             LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_R"             LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_tr"            LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "P_A"             LOC="P8"   | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "joyfire3"        LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+#DEBUG
+# NET "UART_RXD" LOC = P12 | IOSTANDARD=LVCMOS33; #ext36  mas exterior
+# NET "UART_TXD" LOC = P15 | IOSTANDARD=LVCMOS33; #ext35
+
+#NET "sseg_an[0]" LOC = P11   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[1]" LOC = P16   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[2]" LOC = P58   | IOSTANDARD=LVCMOS33;
+#NET "sseg_an[3]" LOC = P51   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[3]" LOC = P44   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[0]" LOC = P40   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[1]" LOC = P21   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[2]" LOC = P33   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[4]" LOC = P47   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[5]" LOC = P24   | IOSTANDARD=LVCMOS33;
+#NET "sseg_a_to_dp[6]" LOC = P29   | IOSTANDARD=LVCMOS33;
+#NET "reset" LOC = P56   | IOSTANDARD=LVCMOS33;
+#NET "set" LOC = P48   | IOSTANDARD=LVCMOS33;
diff --git a/cores/NES/xilinx/NES_ZXUNO.prj b/cores/NES/xilinx/NES_ZXUNO.prj
new file mode 100644
index 0000000..85ea51e
--- /dev/null
+++ b/cores/NES/xilinx/NES_ZXUNO.prj
@@ -0,0 +1,23 @@
+vhdl work "ipcore_dir/nes_clk.vhd"
+vhdl work "ipcore_dir/ram8k.vhd"
+vhdl work "ipcore_dir/ram2k.vhd"
+vhdl work "ipcore_dir/DualPortRAM_Block.vhd"
+vhdl work "ipcore_dir/fifo_loader.vhd"
+vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpupkg.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/CharROM/CharROM_ROM.vhd"
+verilog work "../src/compat.v"
+vhdl work "../src/CtrlModule/ZPUFlex/RTL/zpu_core_flex.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/spi.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/OnScreenDisplay.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/io_ps2_com.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/interrupt_controller.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
+verilog work "../src/vga.v"
+verilog work "../src/sigma_delta_dac.v"
+verilog work "../src/nes.v"
+verilog work "../src/memorycontroller.v"
+verilog work "../src/hq2x.v"
+verilog work "../src/GameLoader.v"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/OSD_Overlay.vhd"
+vhdl work "../src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd"
+verilog work "../src/NES_ZXUNO.v"
diff --git a/cores/NES/xilinx/NES_ZXUNO.ut b/cores/NES/xilinx/NES_ZXUNO.ut
new file mode 100644
index 0000000..dfd4060
--- /dev/null
+++ b/cores/NES/xilinx/NES_ZXUNO.ut
@@ -0,0 +1,30 @@
+-w
+-g Binary:no
+-g Compress
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/cores/NES/xilinx/NES_ZXUNO.xst b/cores/NES/xilinx/NES_ZXUNO.xst
new file mode 100644
index 0000000..4ccf3f5
--- /dev/null
+++ b/cores/NES/xilinx/NES_ZXUNO.xst
@@ -0,0 +1,53 @@
+set -tmpdir "projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn NES_ZXUNO.prj
+-ofn NES_ZXUNO
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top NES_ZXUNO
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-sd {"ipcore_dir"  }
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/cores/NES/xilinx/ipcore_dir/_xmsgs/pn_parser.xmsgs b/cores/NES/xilinx/ipcore_dir/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index abb142b..0000000
--- a/cores/NES/xilinx/ipcore_dir/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated   -->
-<!--     by the Xilinx ISE software.  Any direct editing or        -->
-<!--     changes made to this file may result in unpredictable     -->
-<!--     behavior or data corruption.  It is strongly advised that -->
-<!--     users do not edit the contents of this file.              -->
-<!--                                                               -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;P:/ZXUNO/cores/nes_v2_spartan6/test1_v4/xilinx/ipcore_dir/nes_clk.vhd&quot; into library work</arg>
-</msg>
-
-</messages>
-
diff --git a/cores/NES/xilinx/ipcore_dir/fifo_loader.xise b/cores/NES/xilinx/ipcore_dir/fifo_loader.xise
deleted file mode 100644
index ffa6eb2..0000000
--- a/cores/NES/xilinx/ipcore_dir/fifo_loader.xise
+++ /dev/null
@@ -1,402 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="fifo_loader.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="fifo_loader.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_loader|fifo_loader_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_loader.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_loader" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="fifo_loader" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_loader_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_loader_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_loader_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_loader_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_loader" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-11T09:02:59" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2141ADB74DA74261A32453485F084DC8" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/cores/NES/xilinx/ipcore_dir/nes_clk.xise b/cores/NES/xilinx/ipcore_dir/nes_clk.xise
deleted file mode 100644
index 7cb76d2..0000000
--- a/cores/NES/xilinx/ipcore_dir/nes_clk.xise
+++ /dev/null
@@ -1,403 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="nes_clk.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="nes_clk.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|nes_clk|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="nes_clk.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/nes_clk" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="nes_clk" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="nes_clk_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="nes_clk_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="nes_clk_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="nes_clk_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="nes_clk" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-02-11T10:23:01" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF1227F33362452DA06CF39C5929D9C7" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/nes_clk" xil_pn:name="nes_clk.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>