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Arreglo core SMS

This commit is contained in:
antoniovillena 2016-07-10 13:06:19 +02:00
parent d4ccffcb4c
commit 7719c3aa3b
8 changed files with 11 additions and 272 deletions
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1
cores/MasterSystem/inyectar_bootloader.bat
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@ -1 +0,0 @@
data2mem -bm src\sms_bd.bmm -bt sms_vga.bit -bd all.mem -o b sms_final.bit

1
cores/MasterSystem/inyectar_bootloader_rgb.bat
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@ -1 +0,0 @@
data2mem -bm src\sms_bd.bmm -bt sms_rgb.bit -bd all.mem -o b sms_rgb_final.bit

1
cores/MasterSystem/inyectar_bootloader_vga.bat
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@ -1 +0,0 @@
data2mem -bm src\sms_bd.bmm -bt sms_vga.bit -bd all.mem -o b sms_vga_final.bit

10
cores/MasterSystem/make.bat
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@ -2,8 +2,8 @@ SET machine=sms
SET speed=3
SET ruta_ucf=src\sms
SET ruta_bat=..\
call %ruta_bat%genxst.bat
rem call %ruta_bat%generar.bat v2
rem call %ruta_bat%generar.bat v3
call %ruta_bat%generar.bat v4
rem call %ruta_bat%generar.bat Ap
rem call %ruta_bat%genxst.bat
rem call %ruta_bat%generar.bat v2 src\sms_bd.bmm all.mem
rem call %ruta_bat%generar.bat v3 src\sms_bd.bmm all.mem
call %ruta_bat%generar.bat v4 src\sms_bd.bmm all.mem
rem call %ruta_bat%generar.bat Ap src\sms_bd.bmm all.mem

1
cores/MasterSystem/sms.ut
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@ -1,6 +1,5 @@
-w
-g DebugBitstream:No
-g Compress
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No

193
cores/MasterSystem/src/sms_vga.vhd
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@ -1,193 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sms_vga is
port (
clk: in STD_LOGIC;
ram_we_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
-- j1_MDsel: out STD_LOGIC; --Q
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: inout STD_LOGIC;
audio_l: out STD_LOGIC;
audio_r: out STD_LOGIC;
red: out STD_LOGIC_VECTOR(2 downto 0); --Q
green: out STD_LOGIC_VECTOR(2 downto 0); --Q
blue: out STD_LOGIC_VECTOR(2 downto 0); --Q
hsync: out STD_LOGIC;
vsync: out STD_LOGIC;
spi_do: in STD_LOGIC;
spi_sclk: out STD_LOGIC;
spi_di: out STD_LOGIC;
spi_cs_n: buffer STD_LOGIC; --Q
led: out STD_LOGIC; --Q
NTSC : out std_logic; --Q
PAL : out std_logic --Q
);
end sms_vga;
architecture Behavioral of sms_vga is
component clock is
port (
clk_in: in std_logic;
clk_cpu: out std_logic;
clk16: out std_logic;
clk32: out std_logic;
clk64: out std_logic);
end component;
component system is
port (
clk_cpu: in STD_LOGIC;
clk_vdp: in STD_LOGIC;
ram_we_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0);
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: inout STD_LOGIC;
j2_up: in STD_LOGIC;
j2_down: in STD_LOGIC;
j2_left: in STD_LOGIC;
j2_right: in STD_LOGIC;
j2_tl: in STD_LOGIC;
j2_tr: inout STD_LOGIC;
reset: in STD_LOGIC;
pause: in STD_LOGIC;
x: in UNSIGNED(8 downto 0);
y: in UNSIGNED(7 downto 0);
vblank: in STD_LOGIC;
hblank: in STD_LOGIC;
color: out STD_LOGIC_VECTOR(5 downto 0);
audio: out STD_LOGIC;
spi_do: in STD_LOGIC;
spi_sclk: out STD_LOGIC;
spi_di: out STD_LOGIC;
spi_cs_n: out STD_LOGIC
);
end component;
component vga_video is
port (
clk16: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
vblank: out std_logic;
hblank: out std_logic;
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0)
);
end component;
signal clk_cpu: std_logic;
signal clk16: std_logic;
signal x: unsigned(8 downto 0);
signal y: unsigned(7 downto 0);
signal vblank: std_logic;
signal hblank: std_logic;
signal color: std_logic_vector(5 downto 0);
signal audio: std_logic;
signal j2_tr: std_logic;
begin
clock_inst: clock
port map (
clk_in => clk,
clk_cpu => clk_cpu,
clk16 => clk16,
clk32 => open,
clk64 => open);
video_inst: vga_video
port map (
clk16 => clk16,
x => x,
y => y,
vblank => vblank,
hblank => hblank,
color => color,
hsync => hsync,
vsync => vsync,
red => red(2 downto 1), --Q
green => green(2 downto 1), --Q
blue => blue(2 downto 1) --Q
);
red(0) <= '0'; --Q
green(0) <= '0'; --Q
blue(0) <= '0'; --Q
system_inst: system
port map (
clk_cpu => clk_cpu, --clk_cpu
clk_vdp => clk16, --clk16
ram_we_n => ram_we_n,
ram_a => ram_a,
ram_d => ram_d,
j1_up => j1_up,
j1_down => j1_down,
j1_left => j1_left,
j1_right => j1_right,
j1_tl => j1_tl,
j1_tr => j1_tr,
j2_up => '1',
j2_down => '1',
j2_left => '1',
j2_right => '1',
j2_tl => '1',
j2_tr => j2_tr,
reset => '1',
pause => '1',
x => x,
y => y,
vblank => vblank,
hblank => hblank,
color => color,
audio => audio,
spi_do => spi_do,
spi_sclk => spi_sclk,
spi_di => spi_di,
spi_cs_n => spi_cs_n
);
led <= not spi_cs_n; --Q
audio_l <= audio;
audio_r <= audio;
NTSC <= '0';
PAL <= '0';
end Behavioral;

69
cores/MasterSystem/src/sms_vga_zxuno.ucf
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@ -1,69 +0,0 @@
#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD=LVCMOS33 ; # CLK
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
NET "j1_tr" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_MDsel" LOC="P7" | IOSTANDARD=LVCMOS33;
NET "j1_tl" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B1
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B2
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B3
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B4
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR0
NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR1
NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR2
NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR3
NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR4
NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR5
NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR6
NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR7
NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR8
NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR9
NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR10
NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR11
NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR12
NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR13
NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR14
NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR15
NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR16
NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR17
NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR18
NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA0
NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA1
NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA2
NET ram_d(3) LOC="P99" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA3
NET ram_d(4) LOC="P100" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA4
NET ram_d(5) LOC="P101" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA5
NET ram_d(6) LOC="P102" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA6
NET ram_d(7) LOC="P104" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA7
NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # nWE
NET TX LOC="P11" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # TX

7
cores/generar.bat
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@ -3,4 +3,9 @@ call %ruta_bat%map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-%speed
call %ruta_bat%par -intstyle ise -w -ol high -mt 4 %machine%_map.ncd %machine%.ncd %machine%.pcf
call %ruta_bat%trce -intstyle ise -v 3 -s %speed% -n 3 -fastpaths -xml %machine%.twx %machine%.ncd -o %machine%.twr %machine%.pcf
call %ruta_bat%bitgen -intstyle ise -f %machine%.ut %machine%.ncd
copy /y %machine%.bit %machine%.%1.bit
if "%2" == "" (
copy /y %machine%.bit %machine%.%1.bit
) ELSE (
%mypath%data2mem -bm %2 -bt %machine%.bit -bd %3 -o b %machine%_final.bit
copy /y %machine%_final.bit %machine%.%1.bit
)