diff --git a/cores/JupiterAce/T80.vhd b/cores/JupiterAce/T80.vhd
deleted file mode 100644
index 54f7ed2..0000000
--- a/cores/JupiterAce/T80.vhd
+++ /dev/null
@@ -1,1129 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed wait and halt
---
--- 0211 : Fixed Refresh addition and IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
--- 0235 : Added clock enable and IM 2 fix by Mike Johnson
---
--- 0237 : Changed 8080 I/O address output, added IntE output
---
--- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
--- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
--- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic;
-
- SavePC : out std_logic_vector(15 downto 0);
- SaveINT : out std_logic_vector(7 downto 0);
- RestorePC : in std_logic_vector(15 downto 0);
- RestoreINT : in std_logic_vector(7 downto 0);
-
- RestorePC_n : in std_logic
- );
-end T80;
-
-architecture rtl of T80 is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- -- Registers
- signal ACC, F : std_logic_vector(7 downto 0);
- signal Ap, Fp : std_logic_vector(7 downto 0);
- signal I : std_logic_vector(7 downto 0);
- signal R : unsigned(7 downto 0);
- signal SP, PC : unsigned(15 downto 0);
- signal RegDIH : std_logic_vector(7 downto 0);
- signal RegDIL : std_logic_vector(7 downto 0);
- signal RegBusA : std_logic_vector(15 downto 0);
- signal RegBusB : std_logic_vector(15 downto 0);
- signal RegBusC : std_logic_vector(15 downto 0);
- signal RegAddrA_r : std_logic_vector(2 downto 0);
- signal RegAddrA : std_logic_vector(2 downto 0);
- signal RegAddrB_r : std_logic_vector(2 downto 0);
- signal RegAddrB : std_logic_vector(2 downto 0);
- signal RegAddrC : std_logic_vector(2 downto 0);
- signal RegWEH : std_logic;
- signal RegWEL : std_logic;
- signal Alternate : std_logic;
-
- -- Help Registers
- signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
- signal IR : std_logic_vector(7 downto 0); -- Instruction register
- signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
- signal RegBusA_r : std_logic_vector(15 downto 0);
-
- signal ID16 : signed(15 downto 0);
- signal Save_Mux : std_logic_vector(7 downto 0);
-
- signal TState : unsigned(2 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal IntE_FF1 : std_logic;
- signal IntE_FF2 : std_logic;
- signal Halt_FF : std_logic;
- signal BusReq_s : std_logic;
- signal BusAck : std_logic;
- signal ClkEn : std_logic;
- signal NMI_s : std_logic;
- signal INT_s : std_logic;
- signal IStatus : std_logic_vector(1 downto 0);
-
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal T_Res : std_logic;
- signal XY_State : std_logic_vector(1 downto 0);
- signal Pre_XY_F_M : std_logic_vector(2 downto 0);
- signal NextIs_XY_Fetch : std_logic;
- signal XY_Ind : std_logic;
- signal No_BTR : std_logic;
- signal BTR_r : std_logic;
- signal Auto_Wait : std_logic;
- signal Auto_Wait_t1 : std_logic;
- signal Auto_Wait_t2 : std_logic;
- signal IncDecZ : std_logic;
-
- -- ALU signals
- signal BusB : std_logic_vector(7 downto 0);
- signal BusA : std_logic_vector(7 downto 0);
- signal ALU_Q : std_logic_vector(7 downto 0);
- signal F_Out : std_logic_vector(7 downto 0);
-
- -- Registered micro code outputs
- signal Read_To_Reg_r : std_logic_vector(4 downto 0);
- signal Arith16_r : std_logic;
- signal Z16_r : std_logic;
- signal ALU_Op_r : std_logic_vector(3 downto 0);
- signal Save_ALU_r : std_logic;
- signal PreserveC_r : std_logic;
- signal MCycles : std_logic_vector(2 downto 0);
-
- -- Micro code outputs
- signal MCycles_d : std_logic_vector(2 downto 0);
- signal TStates : std_logic_vector(2 downto 0);
- signal IntCycle : std_logic;
- signal NMICycle : std_logic;
- signal Inc_PC : std_logic;
- signal Inc_WZ : std_logic;
- signal IncDec_16 : std_logic_vector(3 downto 0);
- signal Prefix : std_logic_vector(1 downto 0);
- signal Read_To_Acc : std_logic;
- signal Read_To_Reg : std_logic;
- signal Set_BusB_To : std_logic_vector(3 downto 0);
- signal Set_BusA_To : std_logic_vector(3 downto 0);
- signal ALU_Op : std_logic_vector(3 downto 0);
- signal Save_ALU : std_logic;
- signal PreserveC : std_logic;
- signal Arith16 : std_logic;
- signal Set_Addr_To : std_logic_vector(2 downto 0);
- signal Jump : std_logic;
- signal JumpE : std_logic;
- signal JumpXY : std_logic;
- signal Call : std_logic;
- signal RstP : std_logic;
- signal LDZ : std_logic;
- signal LDW : std_logic;
- signal LDSPHL : std_logic;
- signal IORQ_i : std_logic;
- signal Special_LD : std_logic_vector(2 downto 0);
- signal ExchangeDH : std_logic;
- signal ExchangeRp : std_logic;
- signal ExchangeAF : std_logic;
- signal ExchangeRS : std_logic;
- signal I_DJNZ : std_logic;
- signal I_CPL : std_logic;
- signal I_CCF : std_logic;
- signal I_SCF : std_logic;
- signal I_RETN : std_logic;
- signal I_BT : std_logic;
- signal I_BC : std_logic;
- signal I_BTR : std_logic;
- signal I_RLD : std_logic;
- signal I_RRD : std_logic;
- signal I_INRC : std_logic;
- signal SetDI : std_logic;
- signal SetEI : std_logic;
- signal IMode : std_logic_vector(1 downto 0);
- signal Halt : std_logic;
-
-begin
-
- mcode : T80_MCode
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- IR => IR,
- ISet => ISet,
- MCycle => MCycle,
- F => F,
- NMICycle => NMICycle,
- IntCycle => IntCycle,
- MCycles => MCycles_d,
- TStates => TStates,
- Prefix => Prefix,
- Inc_PC => Inc_PC,
- Inc_WZ => Inc_WZ,
- IncDec_16 => IncDec_16,
- Read_To_Acc => Read_To_Acc,
- Read_To_Reg => Read_To_Reg,
- Set_BusB_To => Set_BusB_To,
- Set_BusA_To => Set_BusA_To,
- ALU_Op => ALU_Op,
- Save_ALU => Save_ALU,
- PreserveC => PreserveC,
- Arith16 => Arith16,
- Set_Addr_To => Set_Addr_To,
- IORQ => IORQ_i,
- Jump => Jump,
- JumpE => JumpE,
- JumpXY => JumpXY,
- Call => Call,
- RstP => RstP,
- LDZ => LDZ,
- LDW => LDW,
- LDSPHL => LDSPHL,
- Special_LD => Special_LD,
- ExchangeDH => ExchangeDH,
- ExchangeRp => ExchangeRp,
- ExchangeAF => ExchangeAF,
- ExchangeRS => ExchangeRS,
- I_DJNZ => I_DJNZ,
- I_CPL => I_CPL,
- I_CCF => I_CCF,
- I_SCF => I_SCF,
- I_RETN => I_RETN,
- I_BT => I_BT,
- I_BC => I_BC,
- I_BTR => I_BTR,
- I_RLD => I_RLD,
- I_RRD => I_RRD,
- I_INRC => I_INRC,
- SetDI => SetDI,
- SetEI => SetEI,
- IMode => IMode,
- Halt => Halt,
- NoRead => NoRead,
- Write => Write);
-
- alu : T80_ALU
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- Arith16 => Arith16_r,
- Z16 => Z16_r,
- ALU_Op => ALU_Op_r,
- IR => IR(5 downto 0),
- ISet => ISet,
- BusA => BusA,
- BusB => BusB,
- F_In => F,
- Q => ALU_Q,
- F_Out => F_Out);
-
- ClkEn <= CEN and not BusAck;
-
- T_Res <= '1' when TState = unsigned(TStates) else '0';
-
- NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
- ((Set_Addr_To = aXY) or
- (MCycle = "001" and IR = "11001011") or
- (MCycle = "001" and IR = "00110110")) else '0';
-
- Save_Mux <= BusB when ExchangeRp = '1' else
- DI_Reg when Save_ALU_r = '0' else
- ALU_Q;
-
- process (RESET_n, RestorePC_n, CLK_n)
- begin
-
- if CLK_n'event and CLK_n = '1' then
-
- if RESET_n = '0' then
- PC <= (others => '0'); -- Program Counter
- A <= (others => '0');
- TmpAddr <= (others => '0');
- IR <= "00000000";
- ISet <= "00";
- XY_State <= "00";
- IStatus <= "00";
- MCycles <= "000";
- DO <= "00000000";
-
- ACC <= (others => '1');
- F <= (others => '1');
- Ap <= (others => '1');
- Fp <= (others => '1');
- I <= (others => '0');
- R <= (others => '0');
- SP <= (others => '1');
- Alternate <= '0';
-
- Read_To_Reg_r <= "00000";
- F <= (others => '1');
- Arith16_r <= '0';
- BTR_r <= '0';
- Z16_r <= '0';
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- PreserveC_r <= '0';
- XY_Ind <= '0';
-
- elsif RestorePC_n = '0' then
- PC <= unsigned( RestorePC );
- A <= RestorePC;
- IStatus <= RestoreInt(1 downto 0);
-
- elsif ClkEn = '1' then
-
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- Read_To_Reg_r <= "00000";
-
- MCycles <= MCycles_d;
-
- if IMode /= "11" then
- IStatus <= IMode;
- end if;
-
- Arith16_r <= Arith16;
- PreserveC_r <= PreserveC;
- if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
- Z16_r <= '1';
- else
- Z16_r <= '0';
- end if;
-
- if MCycle = "001" and TState(2) = '0' then
- -- MCycle = 1 and TState = 1, 2, or 3
-
- if TState = 2 and Wait_n = '1' then
- if Mode < 2 then
- A(7 downto 0) <= std_logic_vector(R);
- A(15 downto 8) <= I;
- R(6 downto 0) <= R(6 downto 0) + 1;
- end if;
-
- if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
- PC <= PC + 1;
- end if;
-
- if IntCycle = '1' and IStatus = "01" then
- IR <= "11111111";
- elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
- IR <= "00000000";
- else
- IR <= DInst;
- end if;
-
- ISet <= "00";
- if Prefix /= "00" then
- if Prefix = "11" then
- if IR(5) = '1' then
- XY_State <= "10";
- else
- XY_State <= "01";
- end if;
- else
- if Prefix = "10" then
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- ISet <= Prefix;
- end if;
- else
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- end if;
-
- else
- -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
- if MCycle = "110" then
- XY_Ind <= '1';
- if Prefix = "01" then
- ISet <= "01";
- end if;
- end if;
-
- if T_Res = '1' then
- BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
- if Jump = '1' then
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(DI_Reg);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- elsif JumpXY = '1' then
- A <= RegBusC;
- PC <= unsigned(RegBusC);
- elsif Call = '1' or RstP = '1' then
- A <= TmpAddr;
- PC <= unsigned(TmpAddr);
- elsif MCycle = MCycles and NMICycle = '1' then
- A <= "0000000001100110";
- PC <= "0000000001100110";
- elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
- A(15 downto 8) <= I;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(I);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- else
- case Set_Addr_To is
- when aXY =>
- if XY_State = "00" then
- A <= RegBusC;
- else
- if NextIs_XY_Fetch = '1' then
- A <= std_logic_vector(PC);
- else
- A <= TmpAddr;
- end if;
- end if;
- when aIOA =>
- if Mode = 3 then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- elsif Mode = 2 then
- -- Duplicate I/O address on 8080
- A(15 downto 8) <= DI_Reg;
- else
- A(15 downto 8) <= ACC;
- end if;
- A(7 downto 0) <= DI_Reg;
- when aSP =>
- A <= std_logic_vector(SP);
- when aBC =>
- if Mode = 3 and IORQ_i = '1' then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- A(7 downto 0) <= RegBusC(7 downto 0);
- else
- A <= RegBusC;
- end if;
- when aDE =>
- A <= RegBusC;
- when aZI =>
- if Inc_WZ = '1' then
- A <= std_logic_vector(unsigned(TmpAddr) + 1);
- else
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- end if;
- when others =>
- A <= std_logic_vector(PC);
- end case;
- end if;
-
- Save_ALU_r <= Save_ALU;
- ALU_Op_r <= ALU_Op;
-
- if I_CPL = '1' then
- -- CPL
- ACC <= not ACC;
- F(Flag_Y) <= not ACC(5);
- F(Flag_H) <= '1';
- F(Flag_X) <= not ACC(3);
- F(Flag_N) <= '1';
- end if;
- if I_CCF = '1' then
- -- CCF
- F(Flag_C) <= not F(Flag_C);
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= F(Flag_C);
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- if I_SCF = '1' then
- -- SCF
- F(Flag_C) <= '1';
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= '0';
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- end if;
-
- if TState = 2 and Wait_n = '1' then
- if ISet = "01" and MCycle = "111" then
- IR <= DInst;
- end if;
- if JumpE = '1' then
- PC <= unsigned(signed(PC) + signed(DI_Reg));
- elsif Inc_PC = '1' then
- PC <= PC + 1;
- end if;
- if BTR_r = '1' then
- PC <= PC - 2;
- end if;
- if RstP = '1' then
- TmpAddr <= (others =>'0');
- TmpAddr(5 downto 3) <= IR(5 downto 3);
- end if;
- end if;
- if TState = 3 and MCycle = "110" then
- TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
- end if;
-
- if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
- if IncDec_16(2 downto 0) = "111" then
- if IncDec_16(3) = '1' then
- SP <= SP - 1;
- else
- SP <= SP + 1;
- end if;
- end if;
- end if;
-
- if LDSPHL = '1' then
- SP <= unsigned(RegBusC);
- end if;
- if ExchangeAF = '1' then
- Ap <= ACC;
- ACC <= Ap;
- Fp <= F;
- F <= Fp;
- end if;
- if ExchangeRS = '1' then
- Alternate <= not Alternate;
- end if;
- end if;
-
- if TState = 3 then
- if LDZ = '1' then
- TmpAddr(7 downto 0) <= DI_Reg;
- end if;
- if LDW = '1' then
- TmpAddr(15 downto 8) <= DI_Reg;
- end if;
-
- if Special_LD(2) = '1' then
- case Special_LD(1 downto 0) is
- when "00" =>
- ACC <= I;
- F(Flag_P) <= IntE_FF2;
- F(Flag_S) <= I(7);
-
- if I = x"00" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
-
- when "01" =>
- ACC <= std_logic_vector(R);
- F(Flag_P) <= IntE_FF2;
- F(Flag_S) <= R(7);
-
- if R = x"00" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
-
- when "10" =>
- I <= ACC;
- when others =>
- R <= unsigned(ACC);
- end case;
- end if;
- end if;
-
- if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
- if Mode = 3 then
- F(6) <= F_Out(6);
- F(5) <= F_Out(5);
- F(7) <= F_Out(7);
- if PreserveC_r = '0' then
- F(4) <= F_Out(4);
- end if;
- else
- F(7 downto 1) <= F_Out(7 downto 1);
- if PreserveC_r = '0' then
- F(Flag_C) <= F_Out(0);
- end if;
- end if;
- end if;
- if T_Res = '1' and I_INRC = '1' then
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- if DI_Reg(7 downto 0) = "00000000" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
- F(Flag_S) <= DI_Reg(7);
- F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
- DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
- end if;
-
- if TState = 1 and Auto_Wait_t1 = '0' then
- DO <= BusB;
- if I_RLD = '1' then
- DO(3 downto 0) <= BusA(3 downto 0);
- DO(7 downto 4) <= BusB(3 downto 0);
- end if;
- if I_RRD = '1' then
- DO(3 downto 0) <= BusB(7 downto 4);
- DO(7 downto 4) <= BusA(3 downto 0);
- end if;
- end if;
-
- if T_Res = '1' then
- Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
- Read_To_Reg_r(4) <= Read_To_Reg;
- if Read_To_Acc = '1' then
- Read_To_Reg_r(3 downto 0) <= "0111";
- Read_To_Reg_r(4) <= '1';
- end if;
- end if;
-
- if TState = 1 and I_BT = '1' then
- F(Flag_X) <= ALU_Q(3);
- F(Flag_Y) <= ALU_Q(1);
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- end if;
- if I_BC = '1' or I_BT = '1' then
- F(Flag_P) <= IncDecZ;
- end if;
-
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10111" =>
- ACC <= Save_Mux;
- when "10110" =>
- DO <= Save_Mux;
- when "11000" =>
- SP(7 downto 0) <= unsigned(Save_Mux);
- when "11001" =>
- SP(15 downto 8) <= unsigned(Save_Mux);
- when "11011" =>
- F <= Save_Mux;
- when others =>
- end case;
- end if;
-
- end if;
-
- end if;
-
- end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- -- Bus A / Write
- RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
- RegAddrA_r <= XY_State(1) & "11";
- end if;
-
- -- Bus B
- RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
- RegAddrB_r <= XY_State(1) & "11";
- end if;
-
- -- Address from register
- RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
- -- Jump (HL), LD SP,HL
- if (JumpXY = '1' or LDSPHL = '1') then
- RegAddrC <= Alternate & "10";
- end if;
- if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
- RegAddrC <= XY_State(1) & "11";
- end if;
-
- if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
- IncDecZ <= F_Out(Flag_Z);
- end if;
- if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
- if ID16 = 0 then
- IncDecZ <= '0';
- else
- IncDecZ <= '1';
- end if;
- end if;
-
- RegBusA_r <= RegBusA;
- end if;
- end if;
- end process;
-
- RegAddrA <=
- -- 16 bit increment/decrement
- XY_State(1) & "11" when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" and XY_State /= "00" else
- Alternate & IncDec_16(1 downto 0) when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) else
- -- EX HL,DL
- Alternate & "10" when ExchangeDH = '1' and TState = 3 else
- Alternate & "01" when ExchangeDH = '1' and TState = 4 else
- -- Bus A / Write
- RegAddrA_r;
-
- RegAddrB <=
- -- EX HL,DL
- Alternate & "01" when ExchangeDH = '1' and TState = 3 else
- -- Bus B
- RegAddrB_r;
-
- ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
- signed(RegBusA) + 1;
-
- process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegWEH <= '0';
- RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
- RegWEH <= not Read_To_Reg_r(0);
- RegWEL <= Read_To_Reg_r(0);
- when others =>
- end case;
- end if;
-
- if ExchangeDH = '1' and (TState = 3 or TState = 4) then
- RegWEH <= '1';
- RegWEL <= '1';
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- case IncDec_16(1 downto 0) is
- when "00" | "01" | "10" =>
- RegWEH <= '1';
- RegWEL <= '1';
- when others =>
- end case;
- end if;
- end process;
-
- process (Save_Mux, RegBusB, RegBusA_r, ID16,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegDIH <= Save_Mux;
- RegDIL <= Save_Mux;
-
- if ExchangeDH = '1' and TState = 3 then
- RegDIH <= RegBusB(15 downto 8);
- RegDIL <= RegBusB(7 downto 0);
- end if;
- if ExchangeDH = '1' and TState = 4 then
- RegDIH <= RegBusA_r(15 downto 8);
- RegDIL <= RegBusA_r(7 downto 0);
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- RegDIH <= std_logic_vector(ID16(15 downto 8));
- RegDIL <= std_logic_vector(ID16(7 downto 0));
- end if;
- end process;
-
- Regs : T80_Reg
- port map(
- Clk => CLK_n,
- CEN => ClkEn,
- WEH => RegWEH,
- WEL => RegWEL,
- AddrA => RegAddrA,
- AddrB => RegAddrB,
- AddrC => RegAddrC,
- DIH => RegDIH,
- DIL => RegDIL,
- DOAH => RegBusA(15 downto 8),
- DOAL => RegBusA(7 downto 0),
- DOBH => RegBusB(15 downto 8),
- DOBL => RegBusB(7 downto 0),
- DOCH => RegBusC(15 downto 8),
- DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- case Set_BusB_To is
- when "0111" =>
- BusB <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusB_To(0) = '1' then
- BusB <= RegBusB(7 downto 0);
- else
- BusB <= RegBusB(15 downto 8);
- end if;
- when "0110" =>
- BusB <= DI_Reg;
- when "1000" =>
- BusB <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusB <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusB <= "00000001";
- when "1011" =>
- BusB <= F;
- when "1100" =>
- BusB <= std_logic_vector(PC(7 downto 0));
- when "1101" =>
- BusB <= std_logic_vector(PC(15 downto 8));
- when "1110" =>
- BusB <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
-
- case Set_BusA_To is
- when "0111" =>
- BusA <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusA_To(0) = '1' then
- BusA <= RegBusA(7 downto 0);
- else
- BusA <= RegBusA(15 downto 8);
- end if;
- when "0110" =>
- BusA <= DI_Reg;
- when "1000" =>
- BusA <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusA <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusA <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
- process (RESET_n,CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if RESET_n = '0' then
- RFSH_n <= '1';
-
- elsif CEN = '1' then
- if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
- RFSH_n <= '0';
- else
- RFSH_n <= '1';
- end if;
- end if;
- end if;
- end process;
-
- MC <= std_logic_vector(MCycle);
- TS <= std_logic_vector(TState);
- DI_Reg <= DI;
- HALT_n <= not Halt_FF;
- BUSAK_n <= not BusAck;
- IntCycle_n <= not IntCycle;
- IntE <= IntE_FF1;
- IORQ <= IORQ_i;
- Stop <= I_DJNZ;
-
- SavePC <= std_logic_vector( PC );
- SaveINT <= "0000" & IntE_FF2 & IntE_FF1 & IStatus when MCycle = "001" and TState = "001" and Prefix = "00" and IntCycle = '0' and NMICycle = '0' else
- "1111" & IntE_FF2 & IntE_FF1 & IStatus;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- variable OldNMI_n : std_logic;
- begin
- if CLK_n'event and CLK_n = '1' then
-
- if RESET_n = '0' then
- BusReq_s <= '0';
- INT_s <= '0';
- NMI_s <= '0';
- OldNMI_n := '0';
-
- elsif CEN = '1' then
- BusReq_s <= not BUSRQ_n;
- INT_s <= not INT_n;
- if NMICycle = '1' then
- NMI_s <= '0';
- elsif NMI_n = '0' and OldNMI_n = '1' then
- NMI_s <= '1';
- end if;
- OldNMI_n := NMI_n;
- end if;
-
- end if;
- end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
- process (RESET_n, RestorePC_n, CLK_n)
- begin
-
- if CLK_n'event and CLK_n = '1' then
- if RESET_n = '0' then
- MCycle <= "001";
- TState <= "000";
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
- M1_n <= '1';
-
- elsif RestorePC_n = '0' then
- MCycle <= "001";
- TState <= "001";
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= RestoreINT(2);
- IntE_FF2 <= RestoreINT(3);
-
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
-
- elsif CEN = '1' then
- if T_Res = '1' then
- Auto_Wait_t1 <= '0';
- else
- Auto_Wait_t1 <= Auto_Wait or IORQ_i;
- end if;
- Auto_Wait_t2 <= Auto_Wait_t1;
- No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
- (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
- (I_BTR and (not IR(4) or F(Flag_Z)));
- if TState = 2 then
- if SetEI = '1' then
- IntE_FF1 <= '1';
- IntE_FF2 <= '1';
- end if;
- if I_RETN = '1' then
- IntE_FF1 <= IntE_FF2;
- end if;
- end if;
- if TState = 3 then
- if SetDI = '1' then
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- end if;
- if IntCycle = '1' or NMICycle = '1' then
- Halt_FF <= '0';
- end if;
- if MCycle = "001" and TState = 2 and Wait_n = '1' then
- M1_n <= '1';
- end if;
- if BusReq_s = '1' and BusAck = '1' then
- else
- BusAck <= '0';
- if TState = 2 and Wait_n = '0' then
- elsif T_Res = '1' then
- if Halt = '1' then
- Halt_FF <= '1';
- end if;
- if BusReq_s = '1' then
- BusAck <= '1';
- else
- TState <= "001";
-
- if NextIs_XY_Fetch = '1' then
- MCycle <= "110";
- Pre_XY_F_M <= MCycle;
- if IR = "00110110" and Mode = 0 then
- Pre_XY_F_M <= "010";
- end if;
- elsif (MCycle = MCycles) or
- No_BTR = '1' or
- (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') or
- ( MCycle = "111" and MCycles= "001" and Pre_XY_F_M = "001" ) then
- M1_n <= '0';
- MCycle <= "001";
- IntCycle <= '0';
- NMICycle <= '0';
- if NMI_s = '1' and Prefix = "00" then
- NMICycle <= '1';
- IntE_FF1 <= '0';
- elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
- IntCycle <= '1';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- elsif (MCycle = "111") or
- (MCycle = "110" and Mode = 1 and ISet /= "01") then
- MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
- else
- MCycle <= std_logic_vector(unsigned(MCycle) + 1);
- end if;
- end if;
- else
- if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
- (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
- TState <= TState + 1;
- end if;
- end if;
- end if;
- if TState = 0 then
- M1_n <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process (IntCycle, NMICycle, MCycle)
- begin
- Auto_Wait <= '0';
- if IntCycle = '1' or NMICycle = '1' then
- if MCycle = "001" then
- Auto_Wait <= '1';
- end if;
- end if;
- end process;
-
-end;
diff --git a/cores/JupiterAce/T80_ALU.vhd b/cores/JupiterAce/T80_ALU.vhd
deleted file mode 100644
index 86fddce..0000000
--- a/cores/JupiterAce/T80_ALU.vhd
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0238 : Fixed zero flag for 16 bit SBC and ADC
---
--- 0240 : Added GB operations
---
--- 0242 : Cleanup
---
--- 0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
- procedure AddSub(A : std_logic_vector;
- B : std_logic_vector;
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector;
- signal Carry : out std_logic) is
- variable B_i : unsigned(A'length - 1 downto 0);
- variable Res_i : unsigned(A'length + 1 downto 0);
- begin
- if Sub = '1' then
- B_i := not unsigned(B);
- else
- B_i := unsigned(B);
- end if;
- Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
- Carry <= Res_i(A'length + 1);
- Res <= std_logic_vector(Res_i(A'length downto 1));
- end;
-
- -- AddSub variables (temporary signals)
- signal UseCarry : std_logic;
- signal Carry7_v : std_logic;
- signal Overflow_v : std_logic;
- signal HalfCarry_v : std_logic;
- signal Carry_v : std_logic;
- signal Q_v : std_logic_vector(7 downto 0);
-
- signal BitMask : std_logic_vector(7 downto 0);
-
-begin
-
- with IR(5 downto 3) select BitMask <= "00000001" when "000",
- "00000010" when "001",
- "00000100" when "010",
- "00001000" when "011",
- "00010000" when "100",
- "00100000" when "101",
- "01000000" when "110",
- "10000000" when others;
-
- UseCarry <= not ALU_Op(2) and ALU_Op(0);
- AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
- AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
- AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
- OverFlow_v <= Carry_v xor Carry7_v;
-
- process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
- variable Q_t : std_logic_vector(7 downto 0);
- variable DAA_Q : unsigned(8 downto 0);
- begin
- Q_t := "--------";
- F_Out <= F_In;
- DAA_Q := "---------";
- case ALU_Op is
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
- F_Out(Flag_N) <= '0';
- F_Out(Flag_C) <= '0';
- case ALU_OP(2 downto 0) is
- when "000" | "001" => -- ADD, ADC
- Q_t := Q_v;
- F_Out(Flag_C) <= Carry_v;
- F_Out(Flag_H) <= HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "010" | "011" | "111" => -- SUB, SBC, CP
- Q_t := Q_v;
- F_Out(Flag_N) <= '1';
- F_Out(Flag_C) <= not Carry_v;
- F_Out(Flag_H) <= not HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "100" => -- AND
- Q_t(7 downto 0) := BusA and BusB;
- F_Out(Flag_H) <= '1';
- when "101" => -- XOR
- Q_t(7 downto 0) := BusA xor BusB;
- F_Out(Flag_H) <= '0';
- when others => -- OR "110"
- Q_t(7 downto 0) := BusA or BusB;
- F_Out(Flag_H) <= '0';
- end case;
- if ALU_Op(2 downto 0) = "111" then -- CP
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- else
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- end if;
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- if Z16 = '1' then
- F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
- end if;
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- case ALU_Op(2 downto 0) is
- when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
- when others =>
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- end case;
- if Arith16 = '1' then
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- F_Out(Flag_P) <= F_In(Flag_P);
- end if;
- when "1100" =>
- -- DAA
- F_Out(Flag_H) <= F_In(Flag_H);
- F_Out(Flag_C) <= F_In(Flag_C);
- DAA_Q(7 downto 0) := unsigned(BusA);
- DAA_Q(8) := '0';
- if F_In(Flag_N) = '0' then
- -- After addition
- -- Alow > 9 or H = 1
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if (DAA_Q(3 downto 0) > 9) then
- F_Out(Flag_H) <= '1';
- else
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q := DAA_Q + 6;
- end if;
- -- new Ahigh > 9 or C = 1
- if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q + 96; -- 0x60
- end if;
- else
- -- After subtraction
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if DAA_Q(3 downto 0) > 5 then
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
- end if;
- if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q - 352; -- 0x160
- end if;
- end if;
- F_Out(Flag_X) <= DAA_Q(3);
- F_Out(Flag_Y) <= DAA_Q(5);
- F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
- Q_t := std_logic_vector(DAA_Q(7 downto 0));
- if DAA_Q(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= DAA_Q(7);
- F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
- DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
- when "1101" | "1110" =>
- -- RLD, RRD
- Q_t(7 downto 4) := BusA(7 downto 4);
- if ALU_Op(0) = '1' then
- Q_t(3 downto 0) := BusB(7 downto 4);
- else
- Q_t(3 downto 0) := BusB(3 downto 0);
- end if;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- when "1001" =>
- -- BIT
- Q_t(7 downto 0) := BusB and BitMask;
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- F_Out(Flag_P) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- F_Out(Flag_P) <= '0';
- end if;
- F_Out(Flag_H) <= '1';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= '0';
- F_Out(Flag_Y) <= '0';
- if IR(2 downto 0) /= "110" then
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- end if;
- when "1010" =>
- -- SET
- Q_t(7 downto 0) := BusB or BitMask;
- when "1011" =>
- -- RES
- Q_t(7 downto 0) := BusB and not BitMask;
- when "1000" =>
- -- ROT
- case IR(5 downto 3) is
- when "000" => -- RLC
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := BusA(7);
- F_Out(Flag_C) <= BusA(7);
- when "010" => -- RL
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(7);
- when "001" => -- RRC
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(0);
- F_Out(Flag_C) <= BusA(0);
- when "011" => -- RR
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(0);
- when "100" => -- SLA
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '0';
- F_Out(Flag_C) <= BusA(7);
- when "110" => -- SLL (Undocumented) / SWAP
- if Mode = 3 then
- Q_t(7 downto 4) := BusA(3 downto 0);
- Q_t(3 downto 0) := BusA(7 downto 4);
- F_Out(Flag_C) <= '0';
- else
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '1';
- F_Out(Flag_C) <= BusA(7);
- end if;
- when "101" => -- SRA
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(7);
- F_Out(Flag_C) <= BusA(0);
- when others => -- SRL
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := '0';
- F_Out(Flag_C) <= BusA(0);
- end case;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- if ISet = "00" then
- F_Out(Flag_P) <= F_In(Flag_P);
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- end if;
- when others =>
- null;
- end case;
- Q <= Q_t;
- end process;
-
-end;
diff --git a/cores/JupiterAce/T80_MCode.vhd b/cores/JupiterAce/T80_MCode.vhd
deleted file mode 100644
index 15e2816..0000000
--- a/cores/JupiterAce/T80_MCode.vhd
+++ /dev/null
@@ -1,1971 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0235 : Added IM 2 fix by Mike Johnson
---
--- 0238 : Added NoRead signal
---
--- 0238b: Fixed instruction timing for POP and DJNZ
---
--- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
--- 0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
--- constant aNone : std_logic_vector(2 downto 0) := "000";
--- constant aXY : std_logic_vector(2 downto 0) := "001";
--- constant aIOA : std_logic_vector(2 downto 0) := "010";
--- constant aSP : std_logic_vector(2 downto 0) := "011";
--- constant aBC : std_logic_vector(2 downto 0) := "100";
--- constant aDE : std_logic_vector(2 downto 0) := "101";
--- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- function is_cc_true(
- F : std_logic_vector(7 downto 0);
- cc : bit_vector(2 downto 0)
- ) return boolean is
- begin
- if Mode = 3 then
- case cc is
- when "000" => return F(7) = '0'; -- NZ
- when "001" => return F(7) = '1'; -- Z
- when "010" => return F(4) = '0'; -- NC
- when "011" => return F(4) = '1'; -- C
- when "100" => return false;
- when "101" => return false;
- when "110" => return false;
- when "111" => return false;
- end case;
- else
- case cc is
- when "000" => return F(6) = '0'; -- NZ
- when "001" => return F(6) = '1'; -- Z
- when "010" => return F(0) = '0'; -- NC
- when "011" => return F(0) = '1'; -- C
- when "100" => return F(2) = '0'; -- PO
- when "101" => return F(2) = '1'; -- PE
- when "110" => return F(7) = '0'; -- P
- when "111" => return F(7) = '1'; -- M
- end case;
- end if;
- end;
-
-begin
-
- process (IR, ISet, MCycle, F, NMICycle, IntCycle)
- variable DDD : std_logic_vector(2 downto 0);
- variable SSS : std_logic_vector(2 downto 0);
- variable DPair : std_logic_vector(1 downto 0);
- variable IRB : bit_vector(7 downto 0);
- begin
- DDD := IR(5 downto 3);
- SSS := IR(2 downto 0);
- DPair := IR(5 downto 4);
- IRB := to_bitvector(IR);
-
- MCycles <= "001";
- if MCycle = "001" then
- TStates <= "100";
- else
- TStates <= "011";
- end if;
- Prefix <= "00";
- Inc_PC <= '0';
- Inc_WZ <= '0';
- IncDec_16 <= "0000";
- Read_To_Acc <= '0';
- Read_To_Reg <= '0';
- Set_BusB_To <= "0000";
- Set_BusA_To <= "0000";
- ALU_Op <= "0" & IR(5 downto 3);
- Save_ALU <= '0';
- PreserveC <= '0';
- Arith16 <= '0';
- IORQ <= '0';
- Set_Addr_To <= aNone;
- Jump <= '0';
- JumpE <= '0';
- JumpXY <= '0';
- Call <= '0';
- RstP <= '0';
- LDZ <= '0';
- LDW <= '0';
- LDSPHL <= '0';
- Special_LD <= "000";
- ExchangeDH <= '0';
- ExchangeRp <= '0';
- ExchangeAF <= '0';
- ExchangeRS <= '0';
- I_DJNZ <= '0';
- I_CPL <= '0';
- I_CCF <= '0';
- I_SCF <= '0';
- I_RETN <= '0';
- I_BT <= '0';
- I_BC <= '0';
- I_BTR <= '0';
- I_RLD <= '0';
- I_RRD <= '0';
- I_INRC <= '0';
- SetDI <= '0';
- SetEI <= '0';
- IMode <= "11";
- Halt <= '0';
- NoRead <= '0';
- Write <= '0';
-
- case ISet is
- when "00" =>
-
-------------------------------------------------------------------------------
---
--- Unprefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
--- 8 BIT LOAD GROUP
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- LD r,r'
- Set_BusB_To(2 downto 0) <= SSS;
- ExchangeRp <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
- -- LD r,n
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
- -- LD r,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
- -- LD (HL),r
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110110" =>
- -- LD (HL),n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00001010" =>
- -- LD A,(BC)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00011010" =>
- -- LD A,(DE)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00111010" =>
- if Mode = 3 then
- -- LDD A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end if;
- when "00000010" =>
- -- LD (BC),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00010010" =>
- -- LD (DE),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110010" =>
- if Mode = 3 then
- -- LDD (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 16 BIT LOAD GROUP
- when "00000001"|"00010001"|"00100001"|"00110001" =>
- -- LD dd,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1000";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1001";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "00101010" =>
- if Mode = 3 then
- -- LDI A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD HL,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end if;
- when "00100010" =>
- if Mode = 3 then
- -- LDI (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD (nn),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "0101"; -- L
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "0100"; -- H
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
- when "11111001" =>
- -- LD SP,HL
- TStates <= "110";
- LDSPHL <= '1';
- when "11000101"|"11010101"|"11100101"|"11110101" =>
- -- PUSH qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "0111";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 2 =>
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "1011";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- Write <= '1';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "11000001"|"11010001"|"11100001"|"11110001" =>
- -- POP qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1011";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- IncDec_16 <= "0111";
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "0111";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
- when "11101011" =>
- if Mode /= 3 then
- -- EX DE,HL
- ExchangeDH <= '1';
- end if;
- when "00001000" =>
- if Mode = 3 then
- -- LD (nn),SP
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "1000";
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "1001";
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EX AF,AF'
- ExchangeAF <= '1';
- end if;
- when "11011001" =>
- if Mode = 3 then
- -- RETI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- SetEI <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EXX
- ExchangeRS <= '1';
- end if;
- when "11100011" =>
- if Mode /= 3 then
- -- EX (SP),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0101";
- Set_BusB_To <= "0101";
- Set_Addr_To <= aSP;
- when 3 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0100";
- Set_BusB_To <= "0100";
- Set_Addr_To <= aSP;
- when 5 =>
- IncDec_16 <= "1111";
- TStates <= "101";
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- ADD A,r
- -- ADC A,r
- -- SUB A,r
- -- SBC A,r
- -- AND A,r
- -- OR A,r
- -- XOR A,r
- -- CP A,r
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- ADD A,(HL)
- -- ADC A,(HL)
- -- SUB A,(HL)
- -- SBC A,(HL)
- -- AND A,(HL)
- -- OR A,(HL)
- -- XOR A,(HL)
- -- CP A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- when others => null;
- end case;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- ADD A,n
- -- ADC A,n
- -- SUB A,n
- -- SBC A,n
- -- AND A,n
- -- OR A,n
- -- XOR A,n
- -- CP A,n
- MCycles <= "010";
- if MCycle = "010" then
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- end if;
- when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
- -- INC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- when "00110100" =>
- -- INC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
- -- DEC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0010";
- when "00110101" =>
- -- DEC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- ALU_Op <= "0010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
- when "00100111" =>
- -- DAA
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- ALU_Op <= "1100";
- Save_ALU <= '1';
- when "00101111" =>
- -- CPL
- I_CPL <= '1';
- when "00111111" =>
- -- CCF
- I_CCF <= '1';
- when "00110111" =>
- -- SCF
- I_SCF <= '1';
- when "00000000" =>
- if NMICycle = '1' then
- -- NMI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when others => null;
- end case;
- elsif IntCycle = '1' then
- -- INT (IM 2)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- LDZ <= '1';
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- --TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- --TStates <= "100";
- Write <= '1';
- when 4 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 5 =>
- Jump <= '1';
- when others => null;
- end case;
- else
- -- NOP
- end if;
- when "01110110" =>
- -- HALT
- Halt <= '1';
- when "11110011" =>
- -- DI
- SetDI <= '1';
- when "11111011" =>
- -- EI
- SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
- when "00001001"|"00011001"|"00101001"|"00111001" =>
- -- ADD HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- Arith16 <= '1';
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- Arith16 <= '1';
- when others =>
- end case;
- when "00000011"|"00010011"|"00100011"|"00110011" =>
- -- INC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "01";
- IncDec_16(1 downto 0) <= DPair;
- when "00001011"|"00011011"|"00101011"|"00111011" =>
- -- DEC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "11";
- IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
- when "00000111"
- -- RLCA
- |"00010111"
- -- RLA
- |"00001111"
- -- RRCA
- |"00011111" =>
- -- RRA
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
-
--- JUMP GROUP
- when "11000011" =>
- -- JP nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- Jump <= '1';
- when others => null;
- end case;
- when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+C),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "01" =>
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- when "10" =>
- -- LD A,($FF00+C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "11" =>
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end case;
- else
- -- JP cc,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Jump <= '1';
- end if;
- when others => null;
- end case;
- end if;
- when "00011000" =>
- if Mode /= 2 then
- -- JR e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00111000" =>
- if Mode /= 2 then
- -- JR C,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00110000" =>
- if Mode /= 2 then
- -- JR NC,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00101000" =>
- if Mode /= 2 then
- -- JR Z,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00100000" =>
- if Mode /= 2 then
- -- JR NZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "11101001" =>
- -- JP (HL)
- JumpXY <= '1';
- when "00010000" =>
- if Mode = 3 then
- I_DJNZ <= '1';
- elsif Mode < 2 then
- -- DJNZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- I_DJNZ <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= "000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- I_DJNZ <= '1';
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
-
--- CALL AND RETURN GROUP
- when "11001101" =>
- -- CALL nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- IncDec_16 <= "1111";
- Inc_PC <= '1';
- TStates <= "100";
- Set_Addr_To <= aSP;
- LDW <= '1';
- Set_BusB_To <= "1101";
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
- if IR(5) = '0' or Mode /= 3 then
- -- CALL cc,nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- LDW <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- TStates <= "100";
- Set_BusB_To <= "1101";
- else
- MCycles <= "011";
- end if;
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- end if;
- when "11001001" =>
- -- RET
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- --TStates <= "101";
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+nn),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "01" =>
- -- ADD SP,n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- ALU_Op <= "0000";
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To <= "1000";
- Set_BusB_To <= "0110";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To <= "1001";
- Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
- when others =>
- end case;
- when "10" =>
- -- LD A,($FF00+nn)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "11" =>
- -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end case;
- else
- -- RET cc
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Set_Addr_TO <= aSP;
- else
- MCycles <= "001";
- end if;
- TStates <= "101";
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- end if;
- when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
- -- RST p
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- Write <= '1';
- RstP <= '1';
- when others => null;
- end case;
-
--- INPUT AND OUTPUT GROUP
- when "11011011" =>
- if Mode /= 3 then
- -- IN A,(n)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
- when "11010011" =>
- if Mode /= 3 then
- -- OUT (n),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
- when "11001011" =>
- if Mode /= 2 then
- Prefix <= "01";
- end if;
-
- when "11101101" =>
- if Mode < 2 then
- Prefix <= "10";
- end if;
-
- when "11011101"|"11111101" =>
- if Mode < 2 then
- Prefix <= "11";
- end if;
-
- end case;
-
- when "01" =>
-
-------------------------------------------------------------------------------
---
--- CB prefixed instructions
---
-------------------------------------------------------------------------------
-
- Set_BusA_To(2 downto 0) <= IR(2 downto 0);
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
- -- RLC r
- -- RL r
- -- RRC r
- -- RR r
- -- SLA r
- -- SRA r
- -- SRL r
- -- SLL r (Undocumented) / SWAP r
- if MCycle = "001" or MCycle = "111" then
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
- -- RLC (HL)
- -- RL (HL)
- -- RRC (HL)
- -- RR (HL)
- -- SRA (HL)
- -- SRL (HL)
- -- SLA (HL)
- -- SLL (HL) (Undocumented) / SWAP (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- BIT b,r
- if MCycle = "001" or MCycle = "111" then
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
- ALU_Op <= "1001";
- end if;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
- -- BIT b,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1001";
- TStates <= "100";
- when others =>
- end case;
- when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
- -- SET b,r
- if MCycle = "001" then
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- else
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusB_To(2 downto 0) <= "110";
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Set_Addr_To <= aXY;
- when 4 =>
- Write <= '1';
- when others =>
- end case;
- end if;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- SET b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- RES b,r
- if MCycle = "001" then
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- else
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusB_To(2 downto 0) <= "110";
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Set_Addr_To <= aXY;
- when 4 =>
- Write <= '1';
- when others =>
- end case;
- end if;
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- RES b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- end case;
-
- when others =>
-
-------------------------------------------------------------------------------
---
--- ED prefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
- |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
- | "10100100"|"10100101"|"10100110"|"10100111"
- | "10101100"|"10101101"|"10101110"|"10101111"
- | "10110100"|"10110101"|"10110110"|"10110111"
- | "10111100"|"10111101"|"10111110"|"10111111"
- |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
- null; -- NOP, undocumented
- when "01111110"|"01111111" =>
- -- NOP, undocumented
- null;
--- 8 BIT LOAD GROUP
- when "01010111" =>
- -- LD A,I
- Special_LD <= "100";
- TStates <= "101";
- when "01011111" =>
- -- LD A,R
- Special_LD <= "101";
- TStates <= "101";
- when "01000111" =>
- -- LD I,A
- Special_LD <= "110";
- TStates <= "101";
- when "01001111" =>
- -- LD R,A
- Special_LD <= "111";
- TStates <= "101";
--- 16 BIT LOAD GROUP
- when "01001011"|"01011011"|"01101011"|"01111011" =>
- -- LD dd,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1000";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '1';
- end if;
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1001";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "01000011"|"01010011"|"01100011"|"01110011" =>
- -- LD (nn),dd
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1000";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1001";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- when "10100000" | "10101000" | "10110000" | "10111000" =>
- -- LDI, LDD, LDIR, LDDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0000";
- Set_Addr_To <= aDE;
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- IX
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- I_BT <= '1';
- TStates <= "101";
- Write <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0101"; -- DE
- else
- IncDec_16 <= "1101";
- end if;
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100001" | "10101001" | "10110001" | "10111001" =>
- -- CPI, CPD, CPIR, CPDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0111";
- Save_ALU <= '1';
- PreserveC <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- NoRead <= '1';
- I_BC <= '1';
- TStates <= "101";
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
- -- NEG
- Alu_OP <= "0010";
- Set_BusB_To <= "0111";
- Set_BusA_To <= "1010";
- Read_To_Acc <= '1';
- Save_ALU <= '1';
- when "01000110"|"01001110"|"01100110"|"01101110" =>
- -- IM 0
- IMode <= "00";
- when "01010110"|"01110110" =>
- -- IM 1
- IMode <= "01";
- when "01011110"|"01110111" =>
- -- IM 2
- IMode <= "10";
--- 16 bit arithmetic
- when "01001010"|"01011010"|"01101010"|"01111010" =>
- -- ADC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0001";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01000010"|"01010010"|"01100010"|"01110010" =>
- -- SBC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01101111" =>
- -- RLD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1101";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RLD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01100111" =>
- -- RRD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1110";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RRD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
- -- RETI, RETN
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- when others => null;
- end case;
- when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
- -- IN r,(C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- IORQ <= '1';
- if IR(5 downto 3) /= "110" then
- Read_To_Reg <= '1';
- Set_BusA_To(2 downto 0) <= IR(5 downto 3);
- end if;
- I_INRC <= '1';
- when others =>
- end case;
- when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
- -- OUT (C),r
- -- OUT (C),0
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To(2 downto 0) <= IR(5 downto 3);
- if IR(5 downto 3) = "110" then
- Set_BusB_To(3) <= '1';
- end if;
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "10100010" | "10101010" | "10110010" | "10111010" =>
- -- INI, IND, INIR, INDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aBC;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- IORQ <= '1';
- Set_BusB_To <= "0110";
- Set_Addr_To <= aXY;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- TStates <= "011"; -- "100"
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100011" | "10101011" | "10110011" | "10111011" =>
- -- OUTI, OUTD, OTIR, OTDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aXY;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- Set_BusB_To <= "0110";
- Set_Addr_To <= aBC;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- IORQ <= '1';
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end case;
-
- end case;
-
- if Mode = 1 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "011";
- end if;
- end if;
-
- if Mode = 3 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "100";
- end if;
- end if;
-
- if Mode < 2 then
- if MCycle = "110" then
- Inc_PC <= '1';
- if Mode = 1 then
- Set_Addr_To <= aXY;
- TStates <= "100";
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- end if;
- if IRB = "00110110" or IRB = "11001011" then
- Set_Addr_To <= aNone;
- end if;
- end if;
- if MCycle = "111" then
- if Mode = 0 then
- TStates <= "101";
- end if;
- if ISet /= "01" then
- Set_Addr_To <= aXY;
- end if;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- if IRB = "00110110" or ISet = "01" then
- -- LD (HL),n
- Inc_PC <= '1';
- else
- NoRead <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-end;
diff --git a/cores/JupiterAce/T80_Pack.vhd b/cores/JupiterAce/T80_Pack.vhd
deleted file mode 100644
index d1b11e1..0000000
--- a/cores/JupiterAce/T80_Pack.vhd
+++ /dev/null
@@ -1,215 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
- component T80
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic;
-
- SavePC : out std_logic_vector(15 downto 0);
- SaveINT : out std_logic_vector(7 downto 0);
- RestorePC : in std_logic_vector(15 downto 0);
- RestoreINT : in std_logic_vector(7 downto 0);
-
- RestorePC_n : in std_logic
- );
- end component;
-
- component T80_Reg
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component T80_MCode
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
- end component;
-
- component T80_ALU
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
-end;
diff --git a/cores/JupiterAce/T80_Reg.vhd b/cores/JupiterAce/T80_Reg.vhd
deleted file mode 100644
index 828485f..0000000
--- a/cores/JupiterAce/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
- signal RegsH : Register_Image(0 to 7);
- signal RegsL : Register_Image(0 to 7);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if CEN = '1' then
- if WEH = '1' then
- RegsH(to_integer(unsigned(AddrA))) <= DIH;
- end if;
- if WEL = '1' then
- RegsL(to_integer(unsigned(AddrA))) <= DIL;
- end if;
- end if;
- end if;
- end process;
-
- DOAH <= RegsH(to_integer(unsigned(AddrA)));
- DOAL <= RegsL(to_integer(unsigned(AddrA)));
- DOBH <= RegsH(to_integer(unsigned(AddrB)));
- DOBL <= RegsL(to_integer(unsigned(AddrB)));
- DOCH <= RegsH(to_integer(unsigned(AddrC)));
- DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/cores/JupiterAce/T80a.vhd b/cores/JupiterAce/T80a.vhd
deleted file mode 100644
index 5e1224e..0000000
--- a/cores/JupiterAce/T80a.vhd
+++ /dev/null
@@ -1,286 +0,0 @@
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed interrupt cycle
---
--- 0235 : Updated for T80 interface change
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
- generic(
- Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- D : inout std_logic_vector(7 downto 0);
-
- SavePC : out std_logic_vector(15 downto 0);
- SaveINT : out std_logic_vector(7 downto 0);
- RestorePC : in std_logic_vector(15 downto 0);
- RestoreINT : in std_logic_vector(7 downto 0);
-
- RestorePC_n : in std_logic
-
- );
-end T80a;
-
-architecture rtl of T80a is
-
- signal CEN : std_logic;
- signal Reset_s : std_logic;
- signal IntCycle_n : std_logic;
- signal IORQ : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal MREQ : std_logic;
- signal MReq_Inhibit : std_logic;
- signal Req_Inhibit : std_logic;
- signal RD : std_logic;
- signal MREQ_n_i : std_logic;
- signal IORQ_n_i : std_logic;
- signal RD_n_i : std_logic;
- signal WR_n_i : std_logic;
- signal RFSH_n_i : std_logic;
- signal BUSAK_n_i : std_logic;
- signal A_i : std_logic_vector(15 downto 0);
- signal DO : std_logic_vector(7 downto 0);
- signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
- signal Wait_s : std_logic;
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- CEN <= '1';
-
- BUSAK_n <= BUSAK_n_i;
- MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
- RD_n_i <= not RD or Req_Inhibit;
-
- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- Reset_s <= '0';
- elsif CLK_n'event and CLK_n = '1' then
- Reset_s <= '1';
- end if;
- end process;
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => 1)
- port map(
- CEN => CEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n_i,
- HALT_n => HALT_n,
- WAIT_n => Wait_s,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => Reset_s,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n_i,
- CLK_n => CLK_n,
- A => A_i,
- DInst => D,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n,
-
- SavePC => SavePC,
- SaveINT => SaveINT,
- RestorePC => RestorePC,
- RestoreINT => RestoreINT,
-
- RestorePC_n => RestorePC_n );
-
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '0' then
- Wait_s <= WAIT_n;
- if TState = "011" and BUSAK_n_i = '1' then
- DI_Reg <= to_x01(D);
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- WR_n_i <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- WR_n_i <= '1';
- if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
- WR_n_i <= not Write;
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- Req_Inhibit <= '0';
- elsif CLK_n'event and CLK_n = '1' then
- if MCycle = "001" and TState = "010" then
- Req_Inhibit <= '1';
- else
- Req_Inhibit <= '0';
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- MReq_Inhibit <= '0';
- elsif CLK_n'event and CLK_n = '0' then
- if MCycle = "001" and TState = "010" then
- MReq_Inhibit <= '1';
- else
- MReq_Inhibit <= '0';
- end if;
- end if;
- end process;
-
- process(Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- RD <= '0';
- MREQ <= '0';
- elsif CLK_n'event and CLK_n = '0' then
-
- if MCycle = "001" then
- if TState = "001" then
- RD <= IntCycle_n;
- MREQ <= IntCycle_n;
- end if;
- if TState = "011" then
- RD <= '0';
- MREQ <= '1';
- end if;
- if TState = "100" then
- MREQ <= '0';
- end if;
- else
- if TState = "001" and NoRead = '0' then
- RD <= not Write;
- MREQ <= not IORQ;
- end if;
- if TState = "011" then
- RD <= '0';
- MREQ <= '0';
- end if;
- end if;
- end if;
- end process;
-
- -- IORQ_n_i uses a different timming than MREQ.
- process(Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- IORQ_n_i <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if MCycle = "001" then
- if TState = "001" then
- IORQ_n_i <= IntCycle_n;
- end if;
- if TState = "011" then
- IORQ_n_i <= '1';
- end if;
- else
- if TState = "001" then
- IORQ_n_i <= not IORQ;
- end if;
- if TState = "011" then
- IORQ_n_i <= '1';
- end if;
- end if;
- end if;
- end process;
-end;
diff --git a/cores/JupiterAce/fpga_ace.v b/cores/JupiterAce/fpga_ace.v
index 3c8fa3e..9a88d70 100644
--- a/cores/JupiterAce/fpga_ace.v
+++ b/cores/JupiterAce/fpga_ace.v
@@ -22,17 +22,18 @@
//////////////////////////////////////////////////////////////////////////////////
module fpga_ace (
- input wire clkram,
+ input wire clkram,
input wire clk65,
- input wire clkcpu,
+ input wire clkcpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
input wire [4:0] columnas,
output wire video,
- output wire sync,
- output wire mic,
- output wire spk
+ output wire hsync,
+ output wire vsync,
+ output wire mic,
+ output wire spk
);
// Los buses del Z80
@@ -40,24 +41,31 @@ module fpga_ace (
wire [7:0] DoutZ80;
wire [15:0] AZ80;
+ // Señales de control, direccion y datos de parte de todas las memorias
wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
- wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
- wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
- wire [7:0] sram_data, cram_data;
- wire [9:0] sram_addr, cram_addr;
+ wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
+ wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
+ wire [7:0] sram_data, cram_data;
+ wire [9:0] sram_addr, cram_addr;
+
+ // Señales para la implementación de la habilitación de escritura en ROM
+ wire enable_write_to_rom;
+ wire [7:0] dout_modulo_enable_write;
+ wire modulo_enable_write_oe;
// Copia del bus de direcciones para las filas del teclado
- assign filas = AZ80[15:8];
+ assign filas = AZ80[15:8];
- // Multiplexor para asignar un valor al bus de datos de entrada del Z80
- assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
- (sram_enable == 1'b1)? dout_sram :
- (cram_enable == 1'b1)? dout_cram :
- (uram_enable == 1'b1)? dout_uram :
- (xram_enable == 1'b1)? dout_xram :
- (eram_enable == 1'b1)? dout_eram :
- (data_from_jace_oe == 1'b1)? data_from_jace :
- sram_data | cram_data; // By default, this is what the data bus sees
+ // Multiplexor para asignar un valor al bus de datos de entrada del Z80
+ assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
+ (sram_enable == 1'b1)? dout_sram :
+ (cram_enable == 1'b1)? dout_cram :
+ (uram_enable == 1'b1)? dout_uram :
+ (xram_enable == 1'b1)? dout_xram :
+ (eram_enable == 1'b1)? dout_eram :
+ (modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
+ (data_from_jace_oe == 1'b1)? data_from_jace :
+ sram_data | cram_data; // By default, this is what the data bus sees
// Memoria del equipo
ram1k_dualport sram (
@@ -112,8 +120,11 @@ module fpga_ace (
/* La ROM */
rom the_rom(
.clk(clkram),
+ .ce(rom_enable),
.a(AZ80[12:0]),
- .dout(dout_rom)
+ .din(DoutZ80),
+ .dout(dout_rom),
+ .we(~wr_n & enable_write_to_rom)
);
/* La CPU */
@@ -155,7 +166,21 @@ module fpga_ace (
.spk(spk),
.mic(mic),
.video(video),
- .csync(sync)
+ .hsync_pal(hsync),
+ .vsync_pal(vsync)
);
+
+ io_write_to_rom modulo_habilitador_escrituras (
+ .clk(clk65),
+ .a(AZ80),
+ .iorq_n(iorq_n),
+ .rd_n(rd_n),
+ .wr_n(wr_n),
+ .din(DoutZ80),
+ .dout(dout_modulo_enable_write),
+ .dout_oe(modulo_enable_write_oe),
+ .enable_write_to_rom(enable_write_to_rom)
+ );
+
endmodule
diff --git a/cores/JupiterAce/jace_logic.v b/cores/JupiterAce/jace_logic.v
index 78481da..2814ffd 100644
--- a/cores/JupiterAce/jace_logic.v
+++ b/cores/JupiterAce/jace_logic.v
@@ -50,7 +50,8 @@ module jace_logic (
output reg spk,
output reg mic,
output wire video,
- output wire csync
+ output wire hsync_pal,
+ output wire vsync_pal
);
initial begin
@@ -62,6 +63,7 @@ module jace_logic (
reg [8:0] cntpix = 9'd0;
reg [8:0] cntscn = 9'd0;
wire [17:0] cnt = {cntscn, cntpix};
+
always @(posedge clk) begin
if (cntpix != 9'd415)
cntpix <= cntpix + 9'd1;
@@ -91,7 +93,9 @@ module jace_logic (
hsync = 1'b1;
end
- assign csync = hsync & vsync;
+ //assign csync = hsync & vsync;
+ assign hsync_pal = hsync;
+ assign vsync_pal = vsync;
reg viden; // VIDEN signal in schematic
always @* begin
diff --git a/cores/JupiterAce/jupiter_ace.prj b/cores/JupiterAce/jupiter_ace.prj
index 894ba1c..579de23 100644
--- a/cores/JupiterAce/jupiter_ace.prj
+++ b/cores/JupiterAce/jupiter_ace.prj
@@ -3,11 +3,13 @@ verilog work "tv80_mcode.v"
verilog work "tv80_alu.v"
verilog work "tv80_core.v"
verilog work "tv80n.v"
-verilog work "rom.v"
verilog work "ps2_port.v"
verilog work "memorias.v"
verilog work "jace_logic.v"
+verilog work "io_write_to_rom.v"
+verilog work "vga_scandoubler.v"
verilog work "relojes.v"
+verilog work "multiboot.v"
verilog work "keyboard_for_ace.v"
verilog work "fpga_ace.v"
verilog work "jupiter_ace.v"
diff --git a/cores/JupiterAce/jupiter_ace.v b/cores/JupiterAce/jupiter_ace.v
index 18f3eca..6f3c3ff 100644
--- a/cores/JupiterAce/jupiter_ace.v
+++ b/cores/JupiterAce/jupiter_ace.v
@@ -6,7 +6,7 @@
//
// Create Date: 17:18:12 11/07/2015
// Design Name:
-// Module Name: tld_jace_spartan6
+// Module Name: jupiter_ace
// Project Name:
// Target Devices:
// Tool versions:
@@ -29,24 +29,32 @@ module jupiter_ace (
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
- output wire csync,
+ output wire hsync,
+ output wire vsync,
output wire stdn,
- output wire stdnb
+ output wire stdnb,
+ ///// SRAM pins (just to get the current video output setting) ////////////
+ output wire [20:0] sram_addr,
+ input wire [7:0] sram_data,
+ output wire sram_we_n
);
- wire clkram; // 50MHz (maybe less if needed) to clock internal RAM/ROM
+ wire clkram; // 26.666666MHz to clock internal RAM/ROM
wire clk65; // 6.5MHz main frequency Jupiter ACE
wire clkcpu; // CPU CLK
+ wire clkvga; // Twice the original pixel clock
wire kbd_reset;
+ wire kbd_mreset;
wire [7:0] kbd_rows;
wire [4:0] kbd_columns;
wire video; // 1-bit video signal (black/white)
- // Trivial conversion from B/W video to RGB
- assign r = {video,video,1'b0};
- assign g = {video,video,1'b0};
- assign b = {video,video,1'b0};
+ // Trivial conversion from B/W video to RGB for the scandoubler
+ wire pal_hsync, pal_vsync; // inputs to the scandoubler
+ wire [2:0] ri = {video,video,1'b0};
+ wire [2:0] gi = {video,video,1'b0};
+ wire [2:0] bi = {video,video,1'b0};
// Trivial conversion for audio
wire mic,spk;
@@ -56,19 +64,27 @@ module jupiter_ace (
// Select PAL
assign stdn = 1'b0; // PAL selection for AD724
assign stdnb = 1'b1; // 4.43MHz crystal selected
+
+ // Initial video output settings
+ reg [7:0] scandblr_reg; // same layout as in the Spectrum core, SCANDBLR_CTRL
// Power-on RESET (8 clocks)
reg [7:0] poweron_reset = 8'h00;
- always @(posedge clk65)
+ assign sram_addr = 21'h008FD5; // magic place where the scandoubler settings have been stored
+ assign sram_we_n = 1'b1;
+ always @(posedge clk65) begin
+ if (poweron_reset == 1'b0)
+ scandblr_reg <= sram_data;
poweron_reset <= {poweron_reset[6:0],1'b1};
+ end
cuatro_relojes system_clocks_pll (
.CLK_IN1(clk50mhz),
- .CLK_OUT1(clkram), // for driving synch RAM and ROM = 26.6666 MHz
- .CLK_OUT2(clk65), // video clock = 6.66666 MHz
- .CLK_OUT3(clkcpu), // CPU clock = 0.5 video clock
- .CLK_OUT4() // Super CPU clock (just a test)
- );
+ .CLK_OUT1(clkram), // for driving RAM and ROM = 26 MHz
+ .CLK_OUT2(clkvga), // VGA clock: 2 x video clock
+ .CLK_OUT3(clk65), // video clock = 6.5 MHz
+ .CLK_OUT4(clkcpu) // CPU clock = 3.25 MHz
+ );
fpga_ace the_core (
.clkram(clkram),
@@ -79,7 +95,8 @@ module jupiter_ace (
.filas(kbd_rows),
.columnas(kbd_columns),
.video(video),
- .sync(csync),
+ .hsync(pal_hsync),
+ .vsync(pal_vsync),
.mic(mic),
.spk(spk)
);
@@ -91,7 +108,30 @@ module jupiter_ace (
.rows(kbd_rows),
.columns(kbd_columns),
.kbd_reset(kbd_reset),
- .kbd_nmi()
+ .kbd_nmi(),
+ .kbd_mreset(kbd_mreset)
);
+
+ vga_scandoubler #(.CLKVIDEO(6500)) salida_vga (
+ .clkvideo(clk65),
+ .clkvga(clkvga),
+ .enable_scandoubling(scandblr_reg[0]),
+ .disable_scaneffect(~scandblr_reg[1]),
+ .ri(ri),
+ .gi(gi),
+ .bi(bi),
+ .hsync_ext_n(pal_hsync),
+ .vsync_ext_n(pal_vsync),
+ .ro(r),
+ .go(g),
+ .bo(b),
+ .hsync(hsync),
+ .vsync(vsync)
+ );
+
+ multiboot return_to_main_core (
+ .clk_icap(clkvga),
+ .mrst_n(kbd_mreset)
+ );
endmodule
diff --git a/cores/JupiterAce/jupiter_ace.xst b/cores/JupiterAce/jupiter_ace.xst
index f22e93a..29822f2 100644
--- a/cores/JupiterAce/jupiter_ace.xst
+++ b/cores/JupiterAce/jupiter_ace.xst
@@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn jupiter_ace.prj
+-infer_ramb8 No
-ofn jupiter_ace
-ofmt NGC
-p xc6slx9-2-tqg144
-top jupiter_ace
--opt_mode Area
--opt_level 1
+-opt_mode Speed
+-opt_level 2
-power NO
+-uc "timings.xcf"
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
--write_timing_constraints NO
+-write_timing_constraints YES
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
@@ -25,8 +27,7 @@ run
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
+-fsm_extract NO
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
index 14a1b53..41f557e 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
@@ -29,38 +29,38 @@ NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
-#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>" IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>" IOSTANDARD = LVCMOS33;
-#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
index 3f0861a..dd9a00d 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@@ -29,38 +29,38 @@ NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
-#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>" IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>" IOSTANDARD = LVCMOS33;
-#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
@@ -86,6 +86,6 @@ NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
-# Otros
+
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
index 1c0ef86..01eb3b3 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
@@ -29,38 +29,38 @@ NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
-#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
diff --git a/cores/JupiterAce/keyboard_for_ace.v b/cores/JupiterAce/keyboard_for_ace.v
index 12deba5..ba412f0 100644
--- a/cores/JupiterAce/keyboard_for_ace.v
+++ b/cores/JupiterAce/keyboard_for_ace.v
@@ -25,12 +25,14 @@ module keyboard_for_ace(
input wire [7:0] rows,
output wire [4:0] columns,
output reg kbd_reset,
- output reg kbd_nmi
+ output reg kbd_nmi,
+ output reg kbd_mreset
);
initial begin
kbd_reset = 1'b1;
kbd_nmi = 1'b1;
+ kbd_mreset = 1'b1;
end
`include "mapa_teclado_es.vh"
@@ -85,7 +87,13 @@ module keyboard_for_ace(
shift_pressed <= ~is_released;
`KEY_LCTRL,
`KEY_RCTRL:
- ctrl_pressed <= ~is_released;
+ begin
+ ctrl_pressed <= ~is_released;
+ if (is_extended)
+ matrix[0][1] <= is_released; // Right control = Symbol shift
+ else
+ matrix[0][0] <= is_released; // Left control = Caps shift
+ end
`KEY_LALT:
alt_pressed <= ~is_released;
`KEY_KPPUNTO:
@@ -113,7 +121,10 @@ module keyboard_for_ace(
matrix[7][0] <= is_released;
end
`KEY_BKSP:
- begin
+ if (ctrl_pressed && alt_pressed) begin
+ kbd_mreset <= is_released;
+ end
+ else begin
matrix[0][0] <= is_released;
matrix[4][0] <= is_released;
end
diff --git a/cores/JupiterAce/memorias.v b/cores/JupiterAce/memorias.v
index d59c279..45ce2cb 100644
--- a/cores/JupiterAce/memorias.v
+++ b/cores/JupiterAce/memorias.v
@@ -20,6 +20,28 @@
//
//////////////////////////////////////////////////////////////////////////////////
+module rom (
+ input wire clk,
+ input wire ce,
+ input wire [12:0] a,
+ input wire we,
+ input wire [7:0] din,
+ output reg [7:0] dout
+ );
+
+ reg [7:0] mem[0:8191];
+ integer i;
+ initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
+ $readmemh ("ace.hex", mem, 0);
+ end
+
+ always @(posedge clk) begin
+ dout <= mem[a];
+ if (we == 1'b1 && ce == 1'b1)
+ mem[a] <= din;
+ end
+endmodule
+
module ram1k (
input wire clk,
input wire ce,
diff --git a/cores/JupiterAce/relojes.v b/cores/JupiterAce/relojes.v
index 592c2c2..4e24039 100644
--- a/cores/JupiterAce/relojes.v
+++ b/cores/JupiterAce/relojes.v
@@ -61,7 +61,7 @@ module cuatro_relojes
output wire CLK_OUT4
);
- wire clkin1,clkout0,clkout1,clkout2,clkout3;
+ wire clkin1,clkout0;
// Input buffering
//------------------------------------
IBUFG clkin1_buf
@@ -76,47 +76,39 @@ module cuatro_relojes
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
- wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
- wire clkout4_unused;
- wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
- .CLKFBOUT_MULT (8),
+ .CLKFBOUT_MULT (13),
.CLKFBOUT_PHASE (0.000),
- .CLKOUT0_DIVIDE (15),
+ .CLKOUT0_DIVIDE (25),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
- .CLKOUT1_DIVIDE (60),
- .CLKOUT1_PHASE (0.000),
- .CLKOUT1_DUTY_CYCLE (0.500),
- .CLKOUT2_DIVIDE (120),
- .CLKOUT2_PHASE (0.000),
- .CLKOUT3_DIVIDE (30),
- .CLKOUT3_PHASE (0.000),
- .CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
- .CLKOUT1 (clkout1),
- .CLKOUT2 (clkout2),
- .CLKOUT3 (clkout3),
- .CLKOUT4 (clkout4_unused),
- .CLKOUT5 (clkout5_unused),
- .LOCKED (locked_unused),
+ .CLKOUT1 (),
+ .CLKOUT2 (),
+ .CLKOUT3 (),
+ .CLKOUT4 (),
+ .CLKOUT5 (),
+ .LOCKED (),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
+ reg [2:0] clkdivider = 3'b000;
+ always @(posedge clkout0)
+ clkdivider <= clkdivider + 3'b001;
// Output buffering
//-----------------------------------
@@ -124,22 +116,20 @@ module cuatro_relojes
(.O (clkfbout_buf),
.I (clkfbout));
-
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
-
BUFG clkout2_buf
(.O (CLK_OUT2),
- .I (clkout1));
+ .I (clkdivider[0]));
BUFG clkout3_buf
(.O (CLK_OUT3),
- .I (clkout2));
+ .I (clkdivider[1]));
BUFG clkout4_buf
(.O (CLK_OUT4),
- .I (clkout3));
+ .I (clkdivider[2]));
endmodule
diff --git a/cores/JupiterAce/rom.v b/cores/JupiterAce/rom.v
deleted file mode 100644
index 8145ce2..0000000
--- a/cores/JupiterAce/rom.v
+++ /dev/null
@@ -1,36 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 04:12:52 02/09/2014
-// Design Name:
-// Module Name: rom
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-module rom (
- input wire clk,
- input wire [12:0] a,
- output reg [7:0] dout
- );
-
- reg [7:0] mem[0:8191];
- integer i;
- initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
- $readmemh ("ace.hex", mem, 0);
- end
-
- always @(posedge clk) begin
- dout <= mem[a[12:0]];
- end
-endmodule
diff --git a/cores/JupiterAce/rom8k.asy b/cores/JupiterAce/rom8k.asy
deleted file mode 100644
index cd471c3..0000000
--- a/cores/JupiterAce/rom8k.asy
+++ /dev/null
@@ -1,21 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 rom8k
-RECTANGLE Normal 32 32 544 672
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName addra[12:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName ena
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName clka
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName douta[7:0]
-PINATTR Polarity OUT
-
diff --git a/cores/JupiterAce/rom8k.gise b/cores/JupiterAce/rom8k.gise
deleted file mode 100644
index 61efe22..0000000
--- a/cores/JupiterAce/rom8k.gise
+++ /dev/null
@@ -1,33 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- 11.1
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/cores/JupiterAce/rom8k.mif b/cores/JupiterAce/rom8k.mif
deleted file mode 100644
index ad2c368..0000000
--- a/cores/JupiterAce/rom8k.mif
+++ /dev/null
@@ -1,8192 +0,0 @@
-11110011
-00100001
-00000000
-00111100
-00111110
-11111100
-00011000
-00100000
-11011001
-11011101
-11001011
-00111110
-01011110
-11000011
-11101110
-00000011
-00101010
-00111011
-00111100
-01110011
-00100011
-11000011
-01011111
-00001000
-00101010
-00111011
-00111100
-00101011
-01010110
-11000011
-01011001
-00001000
-11100001
-01111110
-00110010
-00111101
-00111100
-11000011
-10101101
-00000000
-00100100
-01110111
-10111110
-00101000
-11111011
-10100100
-01100111
-00100010
-00011000
-00111100
-11111001
-00100001
-00001101
-00000001
-00011000
-00000011
-11000011
-00111010
-00000001
-00010001
-00100100
-00111100
-00000001
-00101101
-00000000
-11101101
-10110000
-11011101
-00100001
-00000000
-00111100
-11111101
-00100001
-11001000
-00000100
-11001101
-00100100
-00001010
-10101111
-00110010
-00000000
-00100111
-00100001
-00000000
-00101100
-01111101
-11100110
-10111111
-00001111
-00001111
-00001111
-00110000
-00000010
-00001111
-00001111
-00001111
-01000111
-10011111
-11001011
-00011000
-01000111
-10011111
-10101000
-11100110
-11110000
-10101000
-01110111
-00101100
-00100000
-11100111
-00010001
-11111111
-00101111
-00100001
-11111011
-00011111
-00000001
-00001000
-00000000
-11101101
-10111000
-11101011
-00111110
-01011111
-00001110
-00000111
-11001011
-01101111
-00101000
-00000011
-01110000
-00101011
-00001101
-11101011
-11101101
-10111000
-11101011
-01110000
-00101011
-00111101
-00100000
-11101110
-11101101
-01010110
-00011000
-00001001
-01010001
-01010101
-01001001
-11010100
-00000000
-00000000
-00000100
-10011011
-00000000
-11101101
-01111011
-00011000
-00111100
-11111011
-11000011
-11110010
-00000100
-01000001
-01000010
-01001111
-01010010
-11010100
-10011000
-00000000
-00000101
-10101101
-00000000
-11111101
-11100101
-11111101
-00100001
-10111001
-00000100
-00101010
-00110111
-00111100
-00100010
-00111011
-00111100
-00100001
-00111110
-00111100
-01111110
-11100110
-10110011
-11001011
-01010110
-01110111
-00101000
-00011010
-11001101
-10111001
-00000100
-10010000
-00000100
-10110011
-00001000
-01001011
-00010000
-00000101
-11010010
-00001101
-01101011
-00001000
-00010000
-00010110
-10110101
-00010101
-00010001
-00010000
-00110111
-00111100
-11000001
-00001000
-00001110
-00011010
-11011101
-11001011
-00111101
-01111110
-00100000
-00011011
-11001101
-00001000
-00011000
-01000101
-01010010
-01010010
-01001111
-11010010
-11001101
-10111001
-00000100
-00010001
-00010000
-00111101
-00111100
-10010110
-00001000
-10110011
-00001001
-10010101
-00001010
-00001110
-00011010
-11011101
-00110110
-00111101
-11111111
-00101010
-00110111
-00111100
-00000001
-00001100
-00000000
-00001001
-00100010
-00111011
-00111100
-11111101
-11100001
-00011000
-10001110
-11100000
-00100110
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-01001100
-00111100
-01001100
-00111100
-01001111
-00111100
-01010001
-00111100
-01000101
-00111100
-01011101
-00111100
-11111111
-00000000
-00001010
-01000110
-01001111
-01010010
-01010100
-11001000
-00000000
-00000000
-11111111
-00011111
-00000101
-10110101
-00010001
-01001001
-00111100
-00000000
-00000000
-00000000
-11110101
-00001000
-11110101
-11000101
-11010101
-11100101
-00000110
-00111110
-00010000
-11111110
-00100001
-00101011
-00111100
-00110100
-00100011
-00101000
-11111100
-11001101
-00010000
-00000011
-00100001
-00101000
-00111100
-11001011
-01000110
-00101000
-00100001
-10100111
-00101000
-00011110
-11111110
-00100000
-00111000
-00010100
-11001011
-01001110
-11000100
-00000111
-00001000
-11001011
-01010110
-00101000
-00000010
-11100110
-10011111
-11001011
-01011110
-00101000
-00000010
-11110110
-10000000
-11001101
-10010110
-00000001
-11001101
-11100110
-00000001
-11001101
-10000010
-00000010
-11100001
-11010001
-11000001
-11110001
-00001000
-11110001
-11111011
-11001001
-11111110
-00001101
-00100000
-00010100
-00100001
-00000000
-00100111
-00100010
-00100010
-00111100
-00100010
-00100000
-00111100
-10101111
-11001101
-10011000
-00000001
-00100001
-11100000
-00100110
-00100010
-00011110
-00111100
-11001001
-10100111
-11001000
-00001000
-00101010
-00100010
-00111100
-01111110
-10100111
-00101000
-00000110
-00010001
-00000000
-11011001
-00011001
-00110000
-00101000
-11101101
-01011011
-00100100
-00111100
-00100001
-10100000
-11011011
-00011001
-00110000
-00110100
-00101010
-00011100
-00111100
-00000001
-00100000
-00000000
-00001001
-11101101
-01010010
-11010101
-11010100
-00100001
-00000100
-11001101
-10110000
-00000010
-11010001
-11001101
-00101111
-00000100
-00100001
-00011110
-00111100
-00000110
-00000100
-11001101
-01000011
-00000100
-00010000
-11111011
-11001101
-00000010
-00000011
-01010100
-01011101
-00100011
-00100010
-00100010
-00111100
-00101011
-00101011
-00101000
-00000010
-11101101
-10111000
-00001000
-00010010
-00010011
-11101101
-01010011
-00100000
-00111100
-10101111
-11001001
-00100001
-11110000
-00000001
-00010110
-00000000
-01011111
-00011001
-01011110
-00011001
-11101001
-00100000
-00010011
-00001100
-00011110
-00001010
-00110111
-00011010
-01010000
-00000110
-10011100
-11001001
-00010101
-00010100
-11010011
-00100001
-00101000
-00111100
-10101110
-01110111
-11001001
-00101010
-00100000
-00111100
-00101011
-01111110
-10100111
-11001000
-00100010
-00100000
-00111100
-00100011
-01110111
-11001001
-00101010
-00100000
-00111100
-00100011
-11101101
-01011011
-00100010
-00111100
-10100111
-11101101
-01010010
-11001000
-00011001
-00100010
-00100000
-00111100
-01111110
-00101011
-01110111
-11001001
-00101010
-00100000
-00111100
-00100011
-00100010
-00100000
-00111100
-11001101
-00000010
-00000011
-01100010
-01101011
-00011011
-00011010
-10100111
-11001000
-11101101
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diff --git a/cores/JupiterAce/rom8k.ngc b/cores/JupiterAce/rom8k.ngc
deleted file mode 100644
index 703ae17..0000000
--- a/cores/JupiterAce/rom8k.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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diff --git a/cores/JupiterAce/rom8k.sym b/cores/JupiterAce/rom8k.sym
deleted file mode 100644
index 3485010..0000000
--- a/cores/JupiterAce/rom8k.sym
+++ /dev/null
@@ -1,21 +0,0 @@
-
-
- BLOCK
- 2011-3-23T1:22:54
-
-
-
-
-
- rom8k
-
-
-
-
-
-
-
-
-
-
-
diff --git a/cores/JupiterAce/rom8k.v b/cores/JupiterAce/rom8k.v
deleted file mode 100644
index 058068b..0000000
--- a/cores/JupiterAce/rom8k.v
+++ /dev/null
@@ -1,158 +0,0 @@
-/*******************************************************************************
-* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
-* *
-* This file contains confidential and proprietary information *
-* of Xilinx, Inc. and is protected under U.S. and *
-* international copyright and other intellectual property *
-* laws. *
-* *
-* DISCLAIMER *
-* This disclaimer is not a license and does not grant any *
-* rights to the materials distributed herewith. Except as *
-* otherwise provided in a valid license issued to you by *
-* Xilinx, and to the maximum extent permitted by applicable *
-* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-* (2) Xilinx shall not be liable (whether in contract or tort, *
-* including negligence, or under any other theory of *
-* liability) for any loss or damage of any kind or nature *
-* related to, arising under or in connection with these *
-* materials, including for any direct, or any indirect, *
-* special, incidental, or consequential loss or damage *
-* (including loss of data, profits, goodwill, or any type of *
-* loss or damage suffered as a result of any action brought *
-* by a third party) even if such damage or loss was *
-* reasonably foreseeable or Xilinx had been advised of the *
-* possibility of the same. *
-* *
-* CRITICAL APPLICATIONS *
-* Xilinx products are not designed or intended to be fail- *
-* safe, or for use in any application requiring fail-safe *
-* performance, such as life-support or safety devices or *
-* systems, Class III medical devices, nuclear facilities, *
-* applications related to the deployment of airbags, or any *
-* other applications that could lead to death, personal *
-* injury, or severe property or environmental damage *
-* (individually and collectively, "Critical *
-* Applications"). Customer assumes the sole risk and *
-* liability of any use of Xilinx products in Critical *
-* Applications, subject only to applicable laws and *
-* regulations governing limitations on product liability. *
-* *
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-* PART OF THIS FILE AT ALL TIMES. *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file rom8k.v when simulating
-// the core, rom8k. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module rom8k(
- clka,
- ena,
- addra,
- douta);
-
-
-input clka;
-input ena;
-input [12 : 0] addra;
-output [7 : 0] douta;
-
-// synthesis translate_off
-
- BLK_MEM_GEN_V4_3 #(
- .C_ADDRA_WIDTH(13),
- .C_ADDRB_WIDTH(13),
- .C_ALGORITHM(1),
- .C_BYTE_SIZE(9),
- .C_COMMON_CLK(0),
- .C_DEFAULT_DATA("0"),
- .C_DISABLE_WARN_BHV_COLL(0),
- .C_DISABLE_WARN_BHV_RANGE(0),
- .C_FAMILY("spartan6"),
- .C_HAS_ENA(1),
- .C_HAS_ENB(0),
- .C_HAS_INJECTERR(0),
- .C_HAS_MEM_OUTPUT_REGS_A(0),
- .C_HAS_MEM_OUTPUT_REGS_B(0),
- .C_HAS_MUX_OUTPUT_REGS_A(0),
- .C_HAS_MUX_OUTPUT_REGS_B(0),
- .C_HAS_REGCEA(0),
- .C_HAS_REGCEB(0),
- .C_HAS_RSTA(0),
- .C_HAS_RSTB(0),
- .C_HAS_SOFTECC_INPUT_REGS_A(0),
- .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
- .C_INITA_VAL("0"),
- .C_INITB_VAL("0"),
- .C_INIT_FILE_NAME("rom8k.mif"),
- .C_LOAD_INIT_FILE(1),
- .C_MEM_TYPE(3),
- .C_MUX_PIPELINE_STAGES(0),
- .C_PRIM_TYPE(1),
- .C_READ_DEPTH_A(8192),
- .C_READ_DEPTH_B(8192),
- .C_READ_WIDTH_A(8),
- .C_READ_WIDTH_B(8),
- .C_RSTRAM_A(0),
- .C_RSTRAM_B(0),
- .C_RST_PRIORITY_A("CE"),
- .C_RST_PRIORITY_B("CE"),
- .C_RST_TYPE("SYNC"),
- .C_SIM_COLLISION_CHECK("ALL"),
- .C_USE_BYTE_WEA(0),
- .C_USE_BYTE_WEB(0),
- .C_USE_DEFAULT_DATA(0),
- .C_USE_ECC(0),
- .C_USE_SOFTECC(0),
- .C_WEA_WIDTH(1),
- .C_WEB_WIDTH(1),
- .C_WRITE_DEPTH_A(8192),
- .C_WRITE_DEPTH_B(8192),
- .C_WRITE_MODE_A("WRITE_FIRST"),
- .C_WRITE_MODE_B("WRITE_FIRST"),
- .C_WRITE_WIDTH_A(8),
- .C_WRITE_WIDTH_B(8),
- .C_XDEVICEFAMILY("spartan6"))
- inst (
- .CLKA(clka),
- .ENA(ena),
- .ADDRA(addra),
- .DOUTA(douta),
- .RSTA(),
- .REGCEA(),
- .WEA(),
- .DINA(),
- .CLKB(),
- .RSTB(),
- .ENB(),
- .REGCEB(),
- .WEB(),
- .ADDRB(),
- .DINB(),
- .DOUTB(),
- .INJECTSBITERR(),
- .INJECTDBITERR(),
- .SBITERR(),
- .DBITERR(),
- .RDADDRECC());
-
-
-// synthesis translate_on
-
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of rom8k is "black_box"
-
-endmodule
-
diff --git a/cores/JupiterAce/rom8k.veo b/cores/JupiterAce/rom8k.veo
deleted file mode 100644
index a807a73..0000000
--- a/cores/JupiterAce/rom8k.veo
+++ /dev/null
@@ -1,65 +0,0 @@
-/*******************************************************************************
-* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
-* *
-* This file contains confidential and proprietary information *
-* of Xilinx, Inc. and is protected under U.S. and *
-* international copyright and other intellectual property *
-* laws. *
-* *
-* DISCLAIMER *
-* This disclaimer is not a license and does not grant any *
-* rights to the materials distributed herewith. Except as *
-* otherwise provided in a valid license issued to you by *
-* Xilinx, and to the maximum extent permitted by applicable *
-* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-* (2) Xilinx shall not be liable (whether in contract or tort, *
-* including negligence, or under any other theory of *
-* liability) for any loss or damage of any kind or nature *
-* related to, arising under or in connection with these *
-* materials, including for any direct, or any indirect, *
-* special, incidental, or consequential loss or damage *
-* (including loss of data, profits, goodwill, or any type of *
-* loss or damage suffered as a result of any action brought *
-* by a third party) even if such damage or loss was *
-* reasonably foreseeable or Xilinx had been advised of the *
-* possibility of the same. *
-* *
-* CRITICAL APPLICATIONS *
-* Xilinx products are not designed or intended to be fail- *
-* safe, or for use in any application requiring fail-safe *
-* performance, such as life-support or safety devices or *
-* systems, Class III medical devices, nuclear facilities, *
-* applications related to the deployment of airbags, or any *
-* other applications that could lead to death, personal *
-* injury, or severe property or environmental damage *
-* (individually and collectively, "Critical *
-* Applications"). Customer assumes the sole risk and *
-* liability of any use of Xilinx products in Critical *
-* Applications, subject only to applicable laws and *
-* regulations governing limitations on product liability. *
-* *
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-* PART OF THIS FILE AT ALL TIMES. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-rom8k YourInstanceName (
- .clka(clka),
- .ena(ena),
- .addra(addra), // Bus [12 : 0]
- .douta(douta)); // Bus [7 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file rom8k.v when simulating
-// the core, rom8k. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/cores/JupiterAce/rom8k.xco b/cores/JupiterAce/rom8k.xco
deleted file mode 100644
index 710aa0d..0000000
--- a/cores/JupiterAce/rom8k.xco
+++ /dev/null
@@ -1,93 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.4
-# Date: Wed Mar 23 01:23:52 2011
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s500e
-SET devicefamily = spartan3e
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg320
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET additional_inputs_for_power_estimation=false
-CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
-CSET byte_size=9
-CSET coe_file=.\rom_jace.coe
-CSET collision_warnings=ALL
-CSET component_name=rom8k
-CSET disable_collision_warnings=false
-CSET disable_out_of_range_warnings=false
-CSET ecc=false
-CSET ecctype=No_ECC
-CSET enable_a=Use_ENA_Pin
-CSET enable_b=Always_Enabled
-CSET error_injection_type=Single_Bit_Error_Injection
-CSET fill_remaining_memory_locations=false
-CSET load_init_file=true
-CSET memory_type=Single_Port_ROM
-CSET operating_mode_a=WRITE_FIRST
-CSET operating_mode_b=WRITE_FIRST
-CSET output_reset_value_a=0
-CSET output_reset_value_b=0
-CSET pipeline_stages=0
-CSET port_a_clock=100
-CSET port_a_enable_rate=100
-CSET port_a_write_rate=0
-CSET port_b_clock=0
-CSET port_b_enable_rate=0
-CSET port_b_write_rate=0
-CSET primitive=8kx2
-CSET read_width_a=8
-CSET read_width_b=8
-CSET register_porta_input_of_softecc=false
-CSET register_porta_output_of_memory_core=false
-CSET register_porta_output_of_memory_primitives=false
-CSET register_portb_output_of_memory_core=false
-CSET register_portb_output_of_memory_primitives=false
-CSET register_portb_output_of_softecc=false
-CSET remaining_memory_locations=0
-CSET reset_memory_latch_a=false
-CSET reset_memory_latch_b=false
-CSET reset_priority_a=CE
-CSET reset_priority_b=CE
-CSET reset_type=SYNC
-CSET softecc=false
-CSET use_byte_write_enable=false
-CSET use_error_injection_pins=false
-CSET use_regcea_pin=false
-CSET use_regceb_pin=false
-CSET use_rsta_pin=false
-CSET use_rstb_pin=false
-CSET write_depth_a=8192
-CSET write_width_a=8
-CSET write_width_b=8
-# END Parameters
-GENERATE
-# CRC: f60395b6
diff --git a/cores/JupiterAce/rom8k.xise b/cores/JupiterAce/rom8k.xise
deleted file mode 100644
index c07c4b1..0000000
--- a/cores/JupiterAce/rom8k.xise
+++ /dev/null
@@ -1,368 +0,0 @@
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diff --git a/cores/JupiterAce/rom8k_flist.txt b/cores/JupiterAce/rom8k_flist.txt
deleted file mode 100644
index 44fb91a..0000000
--- a/cores/JupiterAce/rom8k_flist.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-# Output products list for
-_xmsgs\pn_parser.xmsgs
-blk_mem_gen_ds512.pdf
-blk_mem_gen_readme.txt
-rom8k.asy
-rom8k.gise
-rom8k.mif
-rom8k.ngc
-rom8k.sym
-rom8k.v
-rom8k.veo
-rom8k.xco
-rom8k.xise
-rom8k_flist.txt
-rom8k_xmdf.tcl
diff --git a/cores/JupiterAce/rom8k_xmdf.tcl b/cores/JupiterAce/rom8k_xmdf.tcl
deleted file mode 100644
index 180f9c9..0000000
--- a/cores/JupiterAce/rom8k_xmdf.tcl
+++ /dev/null
@@ -1,84 +0,0 @@
-# The package naming convention is _xmdf
-package provide rom8k_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is _xmdf
-namespace eval ::rom8k_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::rom8k_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation:
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name rom8k
-}
-# ::rom8k_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::rom8k_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.mif
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.sym
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom8k
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/cores/MasterSystem/src/sms.vhd b/cores/MasterSystem/src/sms.vhd
index 0785317..9c4f44c 100644
--- a/cores/MasterSystem/src/sms.vhd
+++ b/cores/MasterSystem/src/sms.vhd
@@ -6,8 +6,8 @@ entity sms is
port (
clk: in STD_LOGIC;
- ram_we_n: out STD_LOGIC;
- ram_a: out STD_LOGIC_VECTOR(18 downto 0);
+ sram_we_n: out STD_LOGIC;
+ sram_a: out STD_LOGIC_VECTOR(18 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
-- j1_MDsel: out STD_LOGIC; --Q
@@ -171,13 +171,18 @@ architecture Behavioral of sms is
signal rgb_clk: std_logic;
--- signal scanDB: std_logic;
+ signal scanSWk: std_logic;
signal scanSW: std_logic;
signal j2_tr: std_logic;
signal c0, c1, c2 : std_logic_vector(9 downto 0); --hdmi
+ signal poweron_reset: unsigned(7 downto 0) := "00000000";
+ signal scandoubler_ctrl: std_logic_vector(1 downto 0);
+ signal ram_we_n: std_logic;
+ signal ram_a: std_logic_vector(18 downto 0);
+
begin
clock_inst: clock
@@ -257,7 +262,7 @@ begin
ps2_clk => ps2_clk,
ps2_data => ps2_data,
- scanSW => scanSW,
+ scanSW => scanSWk,
spi_do => spi_do,
spi_sclk => spi_sclk,
@@ -266,6 +271,7 @@ begin
);
led <= not spi_cs_n; --Q
+-- led <= scandoubler_ctrl(0); --debug scandblctrl reg.
audio_l <= audio;
audio_r <= audio;
@@ -273,6 +279,25 @@ begin
NTSC <= '0';
PAL <= '1';
+ ---- scandlbctrl register detection for video mode initialization at start ----
+
+ process (clk_cpu)
+ begin
+ if rising_edge(clk_cpu) then
+ if (poweron_reset < 126) then
+ scandoubler_ctrl <= ram_d(1 downto 0);
+ end if;
+ if poweron_reset < 254 then
+ poweron_reset <= poweron_reset + 1;
+ end if;
+ end if;
+ end process;
+
+
+ sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
+ sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
+
+ -------------------------------------------------------------------------------
vsync <= vga_vsync when scanSW='1' else '1';
hsync <= vga_hsync when scanSW='1' else rgb_hsync;
@@ -286,8 +311,10 @@ begin
x <= vga_x when scanSW='1' else rgb_x;
y <= vga_y when scanSW='1' else rgb_y;
--- sel_pclock <= '1' when scanDB='1' else '0';
sel_pclock <= '1' when scanSW='1' else '0';
+
+-- scanSW <= '1' when scanSWk = '1' else '0';
+ scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
--HDMI
diff --git a/cores/MasterSystem/src/sms_zxuno_Ap.ucf b/cores/MasterSystem/src/sms_zxuno_Ap.ucf
index c748d03..ae35176 100644
--- a/cores/MasterSystem/src/sms_zxuno_Ap.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_Ap.ucf
@@ -29,25 +29,25 @@ NET "ps2_data" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
-NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
-NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
-NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
-NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
-NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
-NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
-NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
-NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
-NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
-NET ram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
-NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
-NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
-NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
-NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
-NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
-NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
-NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
-NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
-NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
+NET sram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
+NET sram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
+NET sram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
+NET sram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
+NET sram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
+NET sram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
+NET sram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
+NET sram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
+NET sram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
+NET sram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
+NET sram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
@@ -60,7 +60,7 @@ NET ram_d(5) LOC="P102" | IOSTANDARD = LVCMOS33;
NET ram_d(6) LOC="P101" | IOSTANDARD = LVCMOS33;
NET ram_d(7) LOC="P100" | IOSTANDARD = LVCMOS33;
-NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;
+NET sram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;
diff --git a/cores/MasterSystem/src/sms_zxuno_v2.ucf b/cores/MasterSystem/src/sms_zxuno_v2.ucf
index 9aa7ab6..e153c27 100644
--- a/cores/MasterSystem/src/sms_zxuno_v2.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v2.ucf
@@ -1,84 +1,97 @@
#UCF para el ZX-UNO v2
+NET "CLK" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
+NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
-NET "CLK" PERIOD=20 ns;
-NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
+# Video output
+NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
+NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
+NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
+NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
+NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
+NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
+NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
+NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
+NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
+NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
-NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
+# Sound input/output
+NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
+NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
-NET "j1_tr" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_tl" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_right" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_left" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_down" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_up" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
-NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
-
-NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
-NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
-NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
-
-NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
-NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
-NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
-
-NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
-NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
-NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
-
-NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
-NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
-NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
-NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
-
-NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
-NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
-
-NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33;
-NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33;
-NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33;
-NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33;
-NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33;
-NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33;
-NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33;
-NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33;
-NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33;
-NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33;
-NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33;
-NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33;
-NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33;
-NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33;
-NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33;
-NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33;
-NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33;
-NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33;
-NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33;
+# Keyboard and mouse
+NET "ps2_clk" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ps2_data" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33;
-NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33;
-NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33;
-NET ram_d(3) LOC="P99" | IOSTANDARD=LVCMOS33;
-NET ram_d(4) LOC="P100" | IOSTANDARD=LVCMOS33;
-NET ram_d(5) LOC="P101" | IOSTANDARD=LVCMOS33;
-NET ram_d(6) LOC="P102" | IOSTANDARD=LVCMOS33;
-NET ram_d(7) LOC="P104" | IOSTANDARD=LVCMOS33;
+# SRAM
+NET sram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
+NET sram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
+NET sram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
+NET sram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
+NET sram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
+NET sram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
+NET sram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
+NET sram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
+NET sram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
+NET sram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
+NET sram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>" IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>" IOSTANDARD = LVCMOS33;
-NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33;
+NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33;
+NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33;
+NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33;
+NET ram_d(3) LOC="P99" | IOSTANDARD = LVCMOS33;
+NET ram_d(4) LOC="P100" | IOSTANDARD = LVCMOS33;
+NET ram_d(5) LOC="P101" | IOSTANDARD = LVCMOS33;
+NET ram_d(6) LOC="P102" | IOSTANDARD = LVCMOS33;
+NET ram_d(7) LOC="P104" | IOSTANDARD = LVCMOS33;
-NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
-NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
+NET sram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;
-NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
\ No newline at end of file
+
+
+
+
+
+
+
+# SD/MMC
+NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
+NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
+NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
+NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "j1_up" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_down" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_left" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_right" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tl" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tr" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+# Otros
+NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD = "TMDS_33";
diff --git a/cores/MasterSystem/src/sms_zxuno_v3.ucf b/cores/MasterSystem/src/sms_zxuno_v3.ucf
index 5fc4889..b41d2c7 100644
--- a/cores/MasterSystem/src/sms_zxuno_v3.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v3.ucf
@@ -1,84 +1,97 @@
#UCF para el ZX-UNO v3
+NET "CLK" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
+NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
-NET "CLK" PERIOD=20 ns;
-NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
+# Video output
+NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
+NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
+NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
+NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
+NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
+NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
+NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
+NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
+NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
+NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
-NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
+# Sound input/output
+NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
+NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
-NET "j1_tr" LOC="P39" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
-NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
-
-NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
-NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
-NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
-
-NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
-NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
-NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
-
-NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
-NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
-NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
-
-NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
-NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
-NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
-NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
-
-NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
-NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
-
-NET ram_a(0) LOC="P143" | IOSTANDARD=LVCMOS33;
-NET ram_a(1) LOC="P142" | IOSTANDARD=LVCMOS33;
-NET ram_a(2) LOC="P141" | IOSTANDARD=LVCMOS33;
-NET ram_a(3) LOC="P140" | IOSTANDARD=LVCMOS33;
-NET ram_a(4) LOC="P139" | IOSTANDARD=LVCMOS33;
-NET ram_a(5) LOC="P104" | IOSTANDARD=LVCMOS33;
-NET ram_a(6) LOC="P102" | IOSTANDARD=LVCMOS33;
-NET ram_a(7) LOC="P101" | IOSTANDARD=LVCMOS33;
-NET ram_a(8) LOC="P100" | IOSTANDARD=LVCMOS33;
-NET ram_a(9) LOC="P99" | IOSTANDARD=LVCMOS33;
-NET ram_a(10) LOC="P112" | IOSTANDARD=LVCMOS33;
-NET ram_a(11) LOC="P114" | IOSTANDARD=LVCMOS33;
-NET ram_a(12) LOC="P115" | IOSTANDARD=LVCMOS33;
-NET ram_a(13) LOC="P116" | IOSTANDARD=LVCMOS33;
-NET ram_a(14) LOC="P117" | IOSTANDARD=LVCMOS33;
-NET ram_a(15) LOC="P131" | IOSTANDARD=LVCMOS33;
-NET ram_a(16) LOC="P133" | IOSTANDARD=LVCMOS33;
-NET ram_a(17) LOC="P134" | IOSTANDARD=LVCMOS33;
-NET ram_a(18) LOC="P137" | IOSTANDARD=LVCMOS33;
+# Keyboard and mouse
+NET "ps2_clk" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ps2_data" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET ram_d(0) LOC="P132" | IOSTANDARD=LVCMOS33;
-NET ram_d(1) LOC="P126" | IOSTANDARD=LVCMOS33;
-NET ram_d(2) LOC="P123" | IOSTANDARD=LVCMOS33;
-NET ram_d(3) LOC="P120" | IOSTANDARD=LVCMOS33;
-NET ram_d(4) LOC="P119" | IOSTANDARD=LVCMOS33;
-NET ram_d(5) LOC="P121" | IOSTANDARD=LVCMOS33;
-NET ram_d(6) LOC="P124" | IOSTANDARD=LVCMOS33;
-NET ram_d(7) LOC="P127" | IOSTANDARD=LVCMOS33;
+# SRAM
+NET sram_a(0) LOC="P143" | IOSTANDARD = LVCMOS33;
+NET sram_a(1) LOC="P142" | IOSTANDARD = LVCMOS33;
+NET sram_a(2) LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(3) LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(4) LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(5) LOC="P104" | IOSTANDARD = LVCMOS33;
+NET sram_a(6) LOC="P102" | IOSTANDARD = LVCMOS33;
+NET sram_a(7) LOC="P101" | IOSTANDARD = LVCMOS33;
+NET sram_a(8) LOC="P100" | IOSTANDARD = LVCMOS33;
+NET sram_a(9) LOC="P99" | IOSTANDARD = LVCMOS33;
+NET sram_a(10) LOC="P112" | IOSTANDARD = LVCMOS33;
+NET sram_a(11) LOC="P114" | IOSTANDARD = LVCMOS33;
+NET sram_a(12) LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(13) LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(14) LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(16) LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(17) LOC="P134" | IOSTANDARD = LVCMOS33;
+NET sram_a(18) LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
-NET ram_WE_n LOC="P118" | IOSTANDARD=LVCMOS33;
+NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33;
+NET ram_d(1) LOC="P126" | IOSTANDARD = LVCMOS33;
+NET ram_d(2) LOC="P123" | IOSTANDARD = LVCMOS33;
+NET ram_d(3) LOC="P120" | IOSTANDARD = LVCMOS33;
+NET ram_d(4) LOC="P119" | IOSTANDARD = LVCMOS33;
+NET ram_d(5) LOC="P121" | IOSTANDARD = LVCMOS33;
+NET ram_d(6) LOC="P124" | IOSTANDARD = LVCMOS33;
+NET ram_d(7) LOC="P127" | IOSTANDARD = LVCMOS33;
-NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
-NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
+NET sram_WE_n LOC="P118" | IOSTANDARD = LVCMOS33;
-NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
\ No newline at end of file
+
+
+
+
+
+
+
+# SD/MMC
+NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
+NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
+NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
+NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+# Otros
+NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD = "TMDS_33";
diff --git a/cores/MasterSystem/src/sms_zxuno_v4.ucf b/cores/MasterSystem/src/sms_zxuno_v4.ucf
index 4c8f5cb..47f0fba 100644
--- a/cores/MasterSystem/src/sms_zxuno_v4.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v4.ucf
@@ -29,27 +29,27 @@ NET "ps2_data" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
-NET "ram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
-NET "ram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
-NET "ram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
-NET "ram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
-NET "ram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
-NET "ram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
-NET "ram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
-NET "ram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
-NET "ram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
-NET "ram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
-NET "ram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
-NET "ram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
-NET "ram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
-NET "ram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
-NET "ram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
-NET "ram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
-NET "ram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
-NET "ram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
-NET "ram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
@@ -60,7 +60,7 @@ NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
-NET "ram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
@@ -71,10 +71,10 @@ NET "ram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SD/MMC
-NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
+NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
-NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
+NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
diff --git a/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf b/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
index 8b62906..11d2892 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
@@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# Otros
-NET "clk12" PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v2.ucf b/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
index 711e9ac..17975e0 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# Otros
-NET "clk12" PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v3.ucf b/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
index 679a83e..451cf3a 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33;
# Otros
-NET "clk12" PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v4.ucf b/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
index 4daa913..9e2c339 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
@@ -1,5 +1,5 @@
# Clocks & debug
-NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
# Video output
@@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
-NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
-#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
@@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# Otros
-NET "clk12" PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/asic.v b/cores/SamCoupe/asic.v
index af6a145..ac37cdc 100644
--- a/cores/SamCoupe/asic.v
+++ b/cores/SamCoupe/asic.v
@@ -56,7 +56,8 @@ module asic (
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
- output reg csync,
+ output reg hsync_pal,
+ output reg vsync_pal,
output wire int_n
);
@@ -177,14 +178,17 @@ module asic (
reg rint_n;
always @* begin
- csync = 1'b1;
+ hsync_pal = 1'b1;
+ vsync_pal = 1'b1;
vint_n = 1'b1;
rint_n = 1'b1;
- if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC))
- csync = 1'b0;
- if (vc >= BEGINVSYNCV && vc < ENDVSYNCV)
- csync = ~csync;
- if (vc == BEGINVSYNCV && hc < 256)
+ if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC)) begin
+ hsync_pal = 1'b0;
+ end
+ if (vc >= BEGINVSYNCV && vc < ENDVSYNCV) begin
+ vsync_pal = 1'b0;
+ end
+ if (vc == BEGINVSYNCV && hc < 10'd256)
vint_n = 1'b0;
if (lineint >= 8'd0 && lineint <= 8'd191)
if ({1'b0, lineint} == vc && hc < 10'd256)
@@ -197,7 +201,7 @@ module asic (
reg fetching_pixels;
always @* begin
- if (vc>=0 && vc=256 && hc=0 && vc=10'd256 && hc=10'd256)) begin
mem_contention = 1'b1; // extra contention for MODE 1
- //io_contention = 1'b1;
end
end
assign asic_is_using_ram = mem_contention & fetching_pixels;
@@ -465,7 +466,7 @@ module asic (
border <= 8'h00;
end
else begin
- if (iorq_n == 1'b0 && wr_n == 1'b0) begin
+ if (iorq_n == 1'b0 && wr_n == 1'b0 && wait_n == 1'b1) begin
if (cpuaddr[7:0] == IOADDR_BORDER)
border <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_VMPR)
diff --git a/cores/SamCoupe/audio_management.v b/cores/SamCoupe/audio_management.v
index c40ec95..593c195 100644
--- a/cores/SamCoupe/audio_management.v
+++ b/cores/SamCoupe/audio_management.v
@@ -37,7 +37,7 @@ module dac (DACout, DACin, Clk, Reset);
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
- always @(posedge Clk or posedge Reset)
+ always @(posedge Clk)
begin
if(Reset)
begin
diff --git a/cores/SamCoupe/multiboot.v b/cores/SamCoupe/multiboot.v
new file mode 100644
index 0000000..f8346f4
--- /dev/null
+++ b/cores/SamCoupe/multiboot.v
@@ -0,0 +1,307 @@
+module multiboot (
+ input wire clk_icap, // WARNING: this clock must not be greater than 20MHz (50ns period)
+ input wire mrst_n
+ );
+
+ reg [4:0] q = 5'b00000;
+ reg reboot_ff = 1'b0;
+ always @(posedge clk_icap) begin
+ q[0] <= ~mrst_n;
+ q[1] <= q[0];
+ q[2] <= q[1];
+ q[3] <= q[2];
+ q[4] <= q[3];
+ reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
+ end
+
+ multiboot_spartan6 hacer_multiboot (
+ .CLK(clk_icap),
+ .MBT_RESET(1'b0),
+ .MBT_REBOOT(reboot_ff),
+ .spi_addr(24'h000000)
+ );
+endmodule
+
+module multiboot_spartan6 (
+ input wire CLK,
+ input wire MBT_RESET,
+ input wire MBT_REBOOT,
+ input wire [23:0] spi_addr
+ );
+
+reg [15:0] icap_din;
+reg icap_ce;
+reg icap_wr;
+
+reg [15:0] ff_icap_din_reversed;
+reg ff_icap_ce;
+reg ff_icap_wr;
+
+
+ ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
+
+ .CE (ff_icap_ce), // Clock enable input
+ .CLK (CLK), // Clock input
+ .I (ff_icap_din_reversed), // 16-bit data input
+ .WRITE (ff_icap_wr) // Write input
+ );
+
+
+// -------------------------------------------------
+// -- State Machine for ICAP_SPARTAN6 MultiBoot --
+// -------------------------------------------------
+
+
+parameter IDLE = 0,
+ SYNC_H = 1,
+ SYNC_L = 2,
+
+ CWD_H = 3,
+ CWD_L = 4,
+
+ GEN1_H = 5,
+ GEN1_L = 6,
+
+ GEN2_H = 7,
+ GEN2_L = 8,
+
+ GEN3_H = 9,
+ GEN3_L = 10,
+
+ GEN4_H = 11,
+ GEN4_L = 12,
+
+ GEN5_H = 13,
+ GEN5_L = 14,
+
+ NUL_H = 15,
+ NUL_L = 16,
+
+ MOD_H = 17,
+ MOD_L = 18,
+
+ HCO_H = 19,
+ HCO_L = 20,
+
+ RBT_H = 21,
+ RBT_L = 22,
+
+ NOOP_0 = 23,
+ NOOP_1 = 24,
+ NOOP_2 = 25,
+ NOOP_3 = 26;
+
+
+reg [4:0] state;
+reg [4:0] next_state;
+
+
+always @*
+ begin: COMB
+
+ case (state)
+
+ IDLE:
+ begin
+ if (MBT_REBOOT)
+ begin
+ next_state = SYNC_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'hAA99; // Sync word 1
+ end
+ else
+ begin
+ next_state = IDLE;
+ icap_ce = 1;
+ icap_wr = 1;
+ icap_din = 16'hFFFF; // Null
+ end
+ end
+
+ SYNC_H:
+ begin
+ next_state = SYNC_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h5566; // Sync word 2
+ end
+
+ SYNC_L:
+ begin
+ next_state = NUL_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h30A1; // Write to Command Register....
+ end
+
+ NUL_H:
+ begin
+ // next_state = NUL_L;
+ next_state = GEN1_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h0000; // Null Command issued.... value = 0x0000
+ end
+
+//Q
+
+ GEN1_H:
+ begin
+ next_state = GEN1_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
+ end
+
+ GEN1_L:
+ begin
+ next_state = GEN2_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
+ end
+
+ GEN2_H:
+ begin
+ next_state = GEN2_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h3281; // Escritura a reg GENERAL_2
+ end
+
+ GEN2_L:
+ begin
+ next_state = MOD_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
+ end
+
+/////// Registro MODE (para carga a 4x tras reboot)
+
+ MOD_H:
+ begin
+ next_state = MOD_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h3301; // Escritura a reg MODE
+ end
+
+ MOD_L:
+ begin
+ next_state = NUL_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
+ end
+/////
+
+ NUL_L:
+ begin
+ next_state = RBT_H;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h30A1; // Write to Command Register....
+ end
+
+ RBT_H:
+ begin
+ next_state = RBT_L;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h000E; // REBOOT Command 0x000E
+ end
+
+//--------------------
+
+ RBT_L:
+ begin
+ next_state = NOOP_0;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h2000; // NOOP
+ end
+
+ NOOP_0:
+ begin
+ next_state = NOOP_1;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h2000; // NOOP
+ end
+
+ NOOP_1:
+ begin
+ next_state = NOOP_2;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h2000; // NOOP
+ end
+
+ NOOP_2:
+ begin
+ next_state = NOOP_3;
+ icap_ce = 0;
+ icap_wr = 0;
+ icap_din = 16'h2000; // NOOP
+ end
+
+//--------------------
+
+ NOOP_3:
+ begin
+ next_state = IDLE;
+ icap_ce = 1;
+ icap_wr = 1;
+ icap_din = 16'h1111; // NULL value
+ end
+
+ default:
+ begin
+ next_state = IDLE;
+ icap_ce = 1;
+ icap_wr = 1;
+ icap_din = 16'h1111; // 16'h1111"
+ end
+
+ endcase
+ end
+
+always @(posedge CLK)
+
+ begin: SEQ
+ if (MBT_RESET)
+ state <= IDLE;
+ else
+ state <= next_state;
+ end
+
+
+always @(posedge CLK)
+
+ begin: ICAP_FF
+
+ ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
+ ff_icap_din_reversed[1] <= icap_din[6];
+ ff_icap_din_reversed[2] <= icap_din[5];
+ ff_icap_din_reversed[3] <= icap_din[4];
+ ff_icap_din_reversed[4] <= icap_din[3];
+ ff_icap_din_reversed[5] <= icap_din[2];
+ ff_icap_din_reversed[6] <= icap_din[1];
+ ff_icap_din_reversed[7] <= icap_din[0];
+ ff_icap_din_reversed[8] <= icap_din[15];
+ ff_icap_din_reversed[9] <= icap_din[14];
+ ff_icap_din_reversed[10] <= icap_din[13];
+ ff_icap_din_reversed[11] <= icap_din[12];
+ ff_icap_din_reversed[12] <= icap_din[11];
+ ff_icap_din_reversed[13] <= icap_din[10];
+ ff_icap_din_reversed[14] <= icap_din[9];
+ ff_icap_din_reversed[15] <= icap_din[8];
+
+ ff_icap_ce <= icap_ce;
+ ff_icap_wr <= icap_wr;
+ end
+
+
+endmodule
diff --git a/cores/SamCoupe/samcoupe.v b/cores/SamCoupe/samcoupe.v
index 9700164..12d82b5 100644
--- a/cores/SamCoupe/samcoupe.v
+++ b/cores/SamCoupe/samcoupe.v
@@ -31,7 +31,8 @@ module samcoupe (
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
- output wire csync,
+ output wire hsync_pal,
+ output wire vsync_pal,
// Audio output
input wire ear,
output wire audio_out_left,
@@ -61,6 +62,7 @@ module samcoupe (
wire [7:0] kbcolumns;
wire kb_nmi_n;
wire kb_rst_n;
+ wire kb_mrst_n;
wire rdmsel;
assign kbrows = {rdmsel, cpuaddr[15:8]};
@@ -91,7 +93,7 @@ module samcoupe (
(asic_oe_n == 1'b0)? data_from_asic :
8'hFF;
- tv80n el_z80 (
+ tv80a el_z80 (
.m1_n(),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
@@ -148,12 +150,13 @@ module samcoupe (
.g(g),
.b(b),
.bright(bright),
- .csync(csync),
+ .hsync_pal(hsync_pal),
+ .vsync_pal(vsync_pal),
.int_n(int_n)
);
rom rom_32k (
- .clk(clk12),
+ .clk(clk24),
.a(romaddr),
.dout(data_from_rom)
);
@@ -200,7 +203,7 @@ module samcoupe (
.cols(kbcolumns),
.rst_out_n(kb_rst_n),
.nmi_out_n(kb_nmi_n),
- .mrst_out_n(),
+ .mrst_out_n(kb_mrst_n),
.user_toggles(),
//---------------------------------
.zxuno_addr(8'h00),
@@ -239,4 +242,8 @@ module samcoupe (
.audio_right(audio_out_right)
);
+ multiboot back_to_bios (
+ .clk_icap(clk24), // WARNING: this clock must not be greater than 20MHz (50ns period)
+ .mrst_n(kb_mrst_n)
+ );
endmodule
diff --git a/cores/SamCoupe/scancode_to_speccy.v b/cores/SamCoupe/scancode_to_sam.v
similarity index 100%
rename from cores/SamCoupe/scancode_to_speccy.v
rename to cores/SamCoupe/scancode_to_sam.v
diff --git a/cores/SamCoupe/timings.xcf b/cores/SamCoupe/timings.xcf
new file mode 100644
index 0000000..8fdd74d
--- /dev/null
+++ b/cores/SamCoupe/timings.xcf
@@ -0,0 +1,5 @@
+#NET "clk50mhz" PERIOD=20 ns;
+NET "clk24" KEEP | S | PERIOD=41 ns;
+NET "clk12" KEEP | S | PERIOD=82 ns;
+NET "clk6" KEEP | S | PERIOD=164 ns;
+NET "clk8" KEEP | S | PERIOD=125 ns;
\ No newline at end of file
diff --git a/cores/SamCoupe/tld_sam.prj b/cores/SamCoupe/tld_sam.prj
index 1ad0847..013fdc6 100644
--- a/cores/SamCoupe/tld_sam.prj
+++ b/cores/SamCoupe/tld_sam.prj
@@ -2,15 +2,17 @@ verilog work "tv80_reg.v"
verilog work "tv80_mcode.v"
verilog work "tv80_alu.v"
verilog work "tv80_core.v"
-verilog work "scancode_to_speccy.v"
+verilog work "scancode_to_sam.v"
verilog work "ps2_port.v"
-verilog work "tv80n.v"
+verilog work "tv80a.v"
verilog work "saa1099.v"
verilog work "rom.v"
verilog work "ram.v"
verilog work "ps2_keyb.v"
+verilog work "multiboot.v"
verilog work "audio_management.v"
verilog work "asic.v"
+verilog work "vga_scandoubler.v"
verilog work "samcoupe.v"
verilog work "relojes.v"
verilog work "tld_sam.v"
diff --git a/cores/SamCoupe/tld_sam.ut b/cores/SamCoupe/tld_sam.ut
index 8440878..a9facca 100644
--- a/cores/SamCoupe/tld_sam.ut
+++ b/cores/SamCoupe/tld_sam.ut
@@ -3,7 +3,7 @@
-g Compress
-g CRC:Enable
-g Reset_on_err:No
--g ConfigRate:4
+-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
diff --git a/cores/SamCoupe/tld_sam.v b/cores/SamCoupe/tld_sam.v
index 37d5ae2..4bc1cec 100644
--- a/cores/SamCoupe/tld_sam.v
+++ b/cores/SamCoupe/tld_sam.v
@@ -30,11 +30,12 @@ module tld_sam (
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
- output wire csync,
+ output wire hsync,
+ output wire vsync,
output wire stdn,
output wire stdnb,
// SRAM interface
- output wire [18:0] sram_addr,
+ output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
// PS/2 keyoard interface
@@ -43,24 +44,34 @@ module tld_sam (
);
// Interface with RAM
- wire [18:0] ramaddr;
- wire [7:0] data_from_ram;
- wire [7:0] data_to_ram;
- wire ram_we_n;
+ wire [18:0] sram_addr_from_sam;
+ wire sram_we_n_from_sam;
// Audio and video
wire [1:0] sam_r, sam_g, sam_b;
wire sam_bright;
- assign r = {sam_r, sam_bright};
- assign g = {sam_g, sam_bright};
- assign b = {sam_b, sam_bright};
+ // scandoubler
+ wire hsync_pal, vsync_pal;
+ wire [2:0] ri = {sam_r, sam_bright};
+ wire [2:0] gi = {sam_g, sam_bright};
+ wire [2:0] bi = {sam_b, sam_bright};
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
wire clk24, clk12, clk6, clk8;
+ reg [7:0] poweron_reset = 8'h00;
+ reg [1:0] scandoubler_ctrl = 2'b00;
+ always @(posedge clk6) begin
+ poweron_reset <= {poweron_reset[6:0], 1'b1};
+ if (poweron_reset[6] == 1'b0)
+ scandoubler_ctrl <= sram_data[1:0];
+ end
+ assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
+ assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
+
relojes los_relojes (
.CLK_IN1 (clk50mhz), // IN
// Clock out ports
@@ -75,13 +86,14 @@ module tld_sam (
.clk12(clk12),
.clk6(clk6),
.clk8(clk8),
- .master_reset_n(1'b1), // esta señal es sólo para simulación
+ .master_reset_n(poweron_reset[7]),
// Video output
.r(sam_r),
.g(sam_g),
.b(sam_b),
.bright(sam_bright),
- .csync(csync),
+ .hsync_pal(hsync_pal),
+ .vsync_pal(vsync_pal),
// Audio output
.ear(~ear),
.audio_out_left(audio_out_left),
@@ -90,8 +102,26 @@ module tld_sam (
.clkps2(clkps2),
.dataps2(dataps2),
// SRAM external interface
- .sram_addr(sram_addr),
+ .sram_addr(sram_addr_from_sam),
.sram_data(sram_data),
- .sram_we_n(sram_we_n)
+ .sram_we_n(sram_we_n_from_sam)
);
+
+ vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
+ .clkvideo(clk12),
+ .clkvga(clk24),
+ .enable_scandoubling(scandoubler_ctrl[0]),
+ .disable_scaneffect(~scandoubler_ctrl[1]),
+ .ri(ri),
+ .gi(gi),
+ .bi(bi),
+ .hsync_ext_n(hsync_pal),
+ .vsync_ext_n(vsync_pal),
+ .ro(r),
+ .go(g),
+ .bo(b),
+ .hsync(hsync),
+ .vsync(vsync)
+ );
+
endmodule
diff --git a/cores/SamCoupe/tld_sam.xst b/cores/SamCoupe/tld_sam.xst
index 9b8b64c..635afd7 100644
--- a/cores/SamCoupe/tld_sam.xst
+++ b/cores/SamCoupe/tld_sam.xst
@@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn tld_sam.prj
+-infer_ramb8 No
-ofn tld_sam
-ofmt NGC
-p xc6slx9-2-tqg144
-top tld_sam
-opt_mode Speed
--opt_level 1
+-opt_level 2
-power NO
+-uc "timings.xcf"
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
--write_timing_constraints NO
+-write_timing_constraints YES
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
@@ -35,7 +37,7 @@ run
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
--resource_sharing NO
+-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
diff --git a/cores/SamCoupe/tv80n.v b/cores/SamCoupe/tv80a.v
similarity index 65%
rename from cores/SamCoupe/tv80n.v
rename to cores/SamCoupe/tv80a.v
index 70454a1..17b82ef 100644
--- a/cores/SamCoupe/tv80n.v
+++ b/cores/SamCoupe/tv80a.v
@@ -25,7 +25,7 @@
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
-module tv80n (/*AUTOARG*/
+module tv80a (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
@@ -33,7 +33,7 @@ module tv80n (/*AUTOARG*/
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
+ parameter T2Write = 1; // 1 => wr_n active in T3, 0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
@@ -59,10 +59,6 @@ module tv80n (/*AUTOARG*/
reg iorq_n;
reg rd_n;
reg wr_n;
- reg nxt_mreq_n;
- reg nxt_iorq_n;
- reg nxt_rd_n;
- reg nxt_wr_n;
wire cen;
wire intcycle_n;
@@ -102,56 +98,71 @@ module tv80n (/*AUTOARG*/
.intcycle_n (intcycle_n)
);
+ reg [6:0] tstate_r = 7'h00;
+ reg [6:0] tstate_rr = 7'h00;
+ always @(negedge clk) begin
+ tstate_r <= tstate;
+ end
+ always @(posedge clk) begin
+ tstate_rr <= tstate;
+ end
+
+ wire mreq_read = ~iorq & ~no_read & ~write;
+ wire mreq_write = ~iorq & ~no_read & write;
+ wire iorq_read = iorq & ~no_read & ~write;
+ wire iorq_write = iorq & ~no_read & write;
+
always @* begin
- nxt_mreq_n = 1;
- nxt_rd_n = 1;
- nxt_iorq_n = 1;
- nxt_wr_n = 1;
+ mreq_n = 1;
+ rd_n = 1;
+ iorq_n = 1;
+ wr_n = 1;
if (mcycle[0]) begin
- if (tstate[1] || tstate[2]) begin
- nxt_rd_n = ~ intcycle_n;
- nxt_mreq_n = ~ intcycle_n;
- nxt_iorq_n = intcycle_n;
- end
- end // if (mcycle[0])
- else begin
- if ((tstate[1] || tstate[2]) && !no_read && !write) begin
- nxt_rd_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
- end
- if (T2Write == 0) begin
- if (tstate[2] && write) begin
- nxt_wr_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
+ if (intcycle_n == 1'b1) begin
+ if (tstate_r[1] || tstate[2]) begin
+ mreq_n = 1'b0;
+ rd_n = 1'b0;
+ end
+ else if (rfsh_n == 1'b0 && tstate_r[3]) begin
+ mreq_n = 1'b0;
end
end
else begin
- if ((tstate[1] || (tstate[2] && !wait_n)) && write) begin
- nxt_wr_n = 1'b0;
- nxt_iorq_n = ~ iorq;
- nxt_mreq_n = iorq;
+ if (tstate[2]) begin
+ iorq_n = 1'b0;
end
- end // else: !if(T2write == 0)
- end // else: !if(mcycle[0])
- end // always @ *
-
- always @(negedge clk) begin
- if (!reset_n) begin
- rd_n <= #1 1'b1;
- wr_n <= #1 1'b1;
- iorq_n <= #1 1'b1;
- mreq_n <= #1 1'b1;
+ end
end
else begin
- rd_n <= #1 nxt_rd_n;
- wr_n <= #1 nxt_wr_n;
- iorq_n <= #1 nxt_iorq_n;
- mreq_n <= #1 nxt_mreq_n;
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
+ if (mreq_read == 1'b1) begin
+ if (tstate_r[1] || tstate_r[2]) begin
+ mreq_n = 1'b0;
+ rd_n = 1'b0;
+ end
+ end
+ else if (mreq_write == 1'b1) begin
+ if (tstate_r[1] || tstate_r[2]) begin
+ mreq_n = 1'b0;
+ if (tstate_r[2]) begin
+ wr_n = 1'b0;
+ end
+ end
+ end
+ else if (iorq_read == 1'b1) begin
+ if (tstate_rr[1] || tstate_r[2]) begin
+ iorq_n = 1'b0;
+ rd_n = 1'b0;
+ end
+ end
+ else if (iorq_write == 1'b1) begin
+ if (tstate_rr[1] || tstate_r[2]) begin
+ iorq_n = 1'b0;
+ wr_n = 1'b0;
+ end
+ end
+ end
+ end
always @(posedge clk) begin
if (!reset_n) begin
@@ -164,4 +175,3 @@ module tv80n (/*AUTOARG*/
end // always @ (posedge clk)
endmodule // t80n
-
diff --git a/cores/SamCoupe/vga_scandoubler.v b/cores/SamCoupe/vga_scandoubler.v
new file mode 100644
index 0000000..844bb04
--- /dev/null
+++ b/cores/SamCoupe/vga_scandoubler.v
@@ -0,0 +1,207 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 17:57:54 11/09/2015
+// Design Name:
+// Module Name: vga_scandoubler
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module vga_scandoubler (
+ input wire clkvideo,
+ input wire clkvga,
+ input wire enable_scandoubling,
+ input wire disable_scaneffect, // 1 to disable scanlines
+ input wire [2:0] ri,
+ input wire [2:0] gi,
+ input wire [2:0] bi,
+ input wire hsync_ext_n,
+ input wire vsync_ext_n,
+ output reg [2:0] ro,
+ output reg [2:0] go,
+ output reg [2:0] bo,
+ output reg hsync,
+ output reg vsync
+ );
+
+ parameter [31:0] CLKVIDEO = 12000;
+
+ // http://www.epanorama.net/faq/vga2rgb/calc.html
+ // SVGA 800x600
+ // HSYNC = 3.36us VSYNC = 114.32us
+
+ parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
+ parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
+
+ reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
+ reg [9:0] totalhor = 10'd0;
+
+ wire [2:0] rout, gout, bout;
+ // Memoria de doble puerto que guarda la información de dos scans
+ // Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
+ // puntos en negro que se pintan durante el HBlank
+ vgascanline_dport memscan (
+ .clk(clkvga),
+ .addrwrite(addrvideo),
+ .addrread(addrvga),
+ .we(1'b1),
+ .din({ri,gi,bi}),
+ .dout({rout,gout,bout})
+ );
+
+ // Para generar scanlines:
+ reg scaneffect = 1'b0;
+ wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
+ color_dimmed apply_to_red (rout, rout_dimmed);
+ color_dimmed apply_to_green (gout, gout_dimmed);
+ color_dimmed apply_to_blue (bout, bout_dimmed);
+ wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
+ wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
+ wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
+
+ // Voy alternativamente escribiendo en una mitad o en otra del scan buffer
+ // Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
+ // En "totalhor" mido el número de ciclos de reloj que hay en un scan
+ always @(posedge clkvideo) begin
+// if (vsync_ext_n == 1'b0) begin
+// addrvideo <= 11'd0;
+// end
+ if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
+ totalhor <= addrvideo[9:0];
+ addrvideo <= {~addrvideo[10],10'b0000000000};
+ end
+ else
+ addrvideo <= addrvideo + 11'd1;
+ end
+
+ // Recorro el scanbuffer al doble de velocidad, generando direcciones para
+ // el scan buffer. Cada vez que el video original ha terminado una linea,
+ // cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
+ // estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
+ // desde el mismo origen
+ // Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
+ // uso después para mostrar los píxeles a su brillo nominal, o con su brillo
+ // reducido para un efecto chachi de scanlines en la VGA
+ always @(posedge clkvga) begin
+// if (vsync_ext_n == 1'b0) begin
+// addrvga <= 11'b10000000000;
+// scaneffect <= 1'b0;
+// end
+ if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
+ addrvga <= {addrvga[10], 10'b000000000};
+ scaneffect <= ~scaneffect;
+ end
+ else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
+ addrvga <= {~addrvga[10],10'b000000000};
+ scaneffect <= ~scaneffect;
+ end
+ else
+ addrvga <= addrvga + 11'd1;
+ end
+
+ // El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
+ // del barrido de un scanline
+ reg hsync_vga, vsync_vga;
+
+ always @* begin
+ if (addrvga[9:0] < HSYNC_COUNT[9:0])
+ hsync_vga = 1'b0;
+ else
+ hsync_vga = 1'b1;
+ end
+
+ // El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
+ // bajada de la señal de sincronismo vertical original
+ reg [15:0] cntvsync = 16'hFFFF;
+ initial vsync_vga = 1'b1;
+ always @(posedge clkvga) begin
+ if (vsync_ext_n == 1'b0) begin
+ if (cntvsync == 16'hFFFF) begin
+ cntvsync <= 16'd0;
+ vsync_vga <= 1'b0;
+ end
+ else if (cntvsync != 16'hFFFE) begin
+ if (cntvsync == VSYNC_COUNT[15:0]) begin
+ vsync_vga <= 1'b1;
+ cntvsync <= 16'hFFFE;
+ end
+ else
+ cntvsync <= cntvsync + 16'd1;
+ end
+ end
+ else if (vsync_ext_n == 1'b1)
+ cntvsync <= 16'hFFFF;
+ end
+
+ always @* begin
+ if (enable_scandoubling == 1'b0) begin // 15kHz output
+ ro = ri;
+ go = gi;
+ bo = bi;
+ hsync = hsync_ext_n ^ ~vsync_ext_n;
+ vsync = 1'b1;
+ end
+ else begin // VGA output
+ ro = ro_vga;
+ go = go_vga;
+ bo = bo_vga;
+ hsync = hsync_vga;
+ vsync = vsync_vga;
+ end
+ end
+
+endmodule
+
+// Una memoria de doble puerto: uno para leer, y otro para
+// escribir. Es de 2048 direcciones: 1024 se emplean para
+// guardar un scan, y otros 1024 para el siguiente scan
+module vgascanline_dport (
+ input wire clk,
+ input wire [10:0] addrwrite,
+ input wire [10:0] addrread,
+ input wire we,
+ input wire [8:0] din,
+ output reg [8:0] dout
+ );
+
+ reg [8:0] scan[0:2047]; // two scanlines
+ always @(posedge clk) begin
+ dout <= scan[addrread];
+ if (we == 1'b1)
+ scan[addrwrite] <= din;
+ end
+endmodule
+
+module color_dimmed (
+ input wire [2:0] in,
+ output reg [2:0] out // out is scaled to roughly 70% of in
+ );
+
+ always @* begin // a LUT
+ case (in)
+ 3'd0 : out = 3'd0;
+ 3'd1 : out = 3'd1;
+ 3'd2 : out = 3'd1;
+ 3'd3 : out = 3'd2;
+ 3'd4 : out = 3'd3;
+ 3'd5 : out = 3'd3;
+ 3'd6 : out = 3'd4;
+ 3'd7 : out = 3'd5;
+ default: out = 3'd0;
+ endcase
+ end
+endmodule
+
\ No newline at end of file