From 77d90edde8226931b2c1a2653e25ea5860489974 Mon Sep 17 00:00:00 2001
From: antoniovillena <espineter@yahoo.com>
Date: Fri, 15 Jul 2016 02:32:15 +0200
Subject: [PATCH] =?UTF-8?q?A=C3=B1ado=20cambios=20SamCoup=C3=A9?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 cores/JupiterAce/T80.vhd                      | 1129 ---
 cores/JupiterAce/T80_ALU.vhd                  |  351 -
 cores/JupiterAce/T80_MCode.vhd                | 1971 ----
 cores/JupiterAce/T80_Pack.vhd                 |  215 -
 cores/JupiterAce/T80_Reg.vhd                  |  105 -
 cores/JupiterAce/T80a.vhd                     |  286 -
 cores/JupiterAce/fpga_ace.v                   |   67 +-
 cores/JupiterAce/jace_logic.v                 |    8 +-
 cores/JupiterAce/jupiter_ace.prj              |    4 +-
 cores/JupiterAce/jupiter_ace.v                |   72 +-
 cores/JupiterAce/jupiter_ace.xst              |   11 +-
 cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf     |   66 +-
 cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf  |   68 +-
 cores/JupiterAce/jupiter_ace_zxuno_v4.ucf     |   66 +-
 cores/JupiterAce/keyboard_for_ace.v           |   17 +-
 cores/JupiterAce/memorias.v                   |   22 +
 cores/JupiterAce/relojes.v                    |   40 +-
 cores/JupiterAce/rom.v                        |   36 -
 cores/JupiterAce/rom8k.asy                    |   21 -
 cores/JupiterAce/rom8k.gise                   |   33 -
 cores/JupiterAce/rom8k.mif                    | 8192 -----------------
 cores/JupiterAce/rom8k.ngc                    |    3 -
 cores/JupiterAce/rom8k.sym                    |   21 -
 cores/JupiterAce/rom8k.v                      |  158 -
 cores/JupiterAce/rom8k.veo                    |   65 -
 cores/JupiterAce/rom8k.xco                    |   93 -
 cores/JupiterAce/rom8k.xise                   |  368 -
 cores/JupiterAce/rom8k_flist.txt              |   15 -
 cores/JupiterAce/rom8k_xmdf.tcl               |   84 -
 cores/MasterSystem/src/sms.vhd                |   37 +-
 cores/MasterSystem/src/sms_zxuno_Ap.ucf       |   40 +-
 cores/MasterSystem/src/sms_zxuno_v2.ucf       |  157 +-
 cores/MasterSystem/src/sms_zxuno_v3.ucf       |  157 +-
 cores/MasterSystem/src/sms_zxuno_v4.ucf       |   48 +-
 cores/SamCoupe/SamCoupe_zxuno_Ap.ucf          |    8 +-
 cores/SamCoupe/SamCoupe_zxuno_v2.ucf          |    8 +-
 cores/SamCoupe/SamCoupe_zxuno_v3.ucf          |    8 +-
 cores/SamCoupe/SamCoupe_zxuno_v4.ucf          |    8 +-
 cores/SamCoupe/asic.v                         |   39 +-
 cores/SamCoupe/audio_management.v             |    2 +-
 cores/SamCoupe/multiboot.v                    |  307 +
 cores/SamCoupe/samcoupe.v                     |   17 +-
 ...scancode_to_speccy.v => scancode_to_sam.v} |    0
 cores/SamCoupe/timings.xcf                    |    5 +
 cores/SamCoupe/tld_sam.prj                    |    6 +-
 cores/SamCoupe/tld_sam.ut                     |    2 +-
 cores/SamCoupe/tld_sam.v                      |   56 +-
 cores/SamCoupe/tld_sam.xst                    |    8 +-
 cores/SamCoupe/{tv80n.v => tv80a.v}           |  106 +-
 cores/SamCoupe/vga_scandoubler.v              |  207 +
 50 files changed, 1189 insertions(+), 13624 deletions(-)
 delete mode 100644 cores/JupiterAce/T80.vhd
 delete mode 100644 cores/JupiterAce/T80_ALU.vhd
 delete mode 100644 cores/JupiterAce/T80_MCode.vhd
 delete mode 100644 cores/JupiterAce/T80_Pack.vhd
 delete mode 100644 cores/JupiterAce/T80_Reg.vhd
 delete mode 100644 cores/JupiterAce/T80a.vhd
 delete mode 100644 cores/JupiterAce/rom.v
 delete mode 100644 cores/JupiterAce/rom8k.asy
 delete mode 100644 cores/JupiterAce/rom8k.gise
 delete mode 100644 cores/JupiterAce/rom8k.mif
 delete mode 100644 cores/JupiterAce/rom8k.ngc
 delete mode 100644 cores/JupiterAce/rom8k.sym
 delete mode 100644 cores/JupiterAce/rom8k.v
 delete mode 100644 cores/JupiterAce/rom8k.veo
 delete mode 100644 cores/JupiterAce/rom8k.xco
 delete mode 100644 cores/JupiterAce/rom8k.xise
 delete mode 100644 cores/JupiterAce/rom8k_flist.txt
 delete mode 100644 cores/JupiterAce/rom8k_xmdf.tcl
 create mode 100644 cores/SamCoupe/multiboot.v
 rename cores/SamCoupe/{scancode_to_speccy.v => scancode_to_sam.v} (100%)
 create mode 100644 cores/SamCoupe/timings.xcf
 rename cores/SamCoupe/{tv80n.v => tv80a.v} (65%)
 create mode 100644 cores/SamCoupe/vga_scandoubler.v

diff --git a/cores/JupiterAce/T80.vhd b/cores/JupiterAce/T80.vhd
deleted file mode 100644
index 54f7ed2..0000000
--- a/cores/JupiterAce/T80.vhd
+++ /dev/null
@@ -1,1129 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic;
-		
-		SavePC      : out std_logic_vector(15 downto 0);
-		SaveINT     : out std_logic_vector(7 downto 0);
-		RestorePC   : in std_logic_vector(15 downto 0);
-		RestoreINT  : in std_logic_vector(7 downto 0);
-		
-		RestorePC_n : in std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, RestorePC_n, CLK_n)
-	begin
-			
-		if CLK_n'event and CLK_n = '1' then
-
-			if RESET_n = '0' then
-				PC <= (others => '0');  -- Program Counter
-				A <= (others => '0');
-				TmpAddr <= (others => '0');
-				IR <= "00000000";
-				ISet <= "00";
-				XY_State <= "00";
-				IStatus <= "00";
-				MCycles <= "000";
-				DO <= "00000000";
-
-				ACC <= (others => '1');
-				F <= (others => '1');
-				Ap <= (others => '1');
-				Fp <= (others => '1');
-				I <= (others => '0');
-				R <= (others => '0');
-				SP <= (others => '1');
-				Alternate <= '0';
-
-				Read_To_Reg_r <= "00000";
-				F <= (others => '1');
-				Arith16_r <= '0';
-				BTR_r <= '0';
-				Z16_r <= '0';
-				ALU_Op_r <= "0000";
-				Save_ALU_r <= '0';
-				PreserveC_r <= '0';
-				XY_Ind <= '0';
-
-			elsif RestorePC_n = '0' then
-				PC <= unsigned( RestorePC );
-				A <= RestorePC;
-				IStatus <= RestoreInt(1 downto 0);
-				
-			elsif ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-						F(Flag_S) <= I(7);
-						
-						if I = x"00" then 
-							F(Flag_Z) <= '1';
-						else
-							F(Flag_Z) <= '0';
-						end if;
-
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-						F(Flag_S) <= R(7);
-						
-						if R = x"00" then 
-							F(Flag_Z) <= '1';
-						else
-							F(Flag_Z) <= '0';
-						end if;
-						
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" and XY_State /= "00" else
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if RESET_n = '0' then
-				RFSH_n <= '1';
-				
-			elsif CEN = '1' then
-				if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-					RFSH_n <= '0';
-				else
-					RFSH_n <= '1';
-				end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
-	SavePC <= std_logic_vector( PC );
-	SaveINT <= "0000" & IntE_FF2 & IntE_FF1 & IStatus when MCycle = "001" and TState = "001" and Prefix = "00" and IntCycle = '0' and NMICycle = '0' else
-			"1111" & IntE_FF2 & IntE_FF1 & IStatus;	
-	
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if CLK_n'event and CLK_n = '1' then
-		
-			if RESET_n = '0' then
-				BusReq_s <= '0';
-				INT_s <= '0';
-				NMI_s <= '0';
-				OldNMI_n := '0';
-
-			elsif CEN = '1' then
-				BusReq_s <= not BUSRQ_n;
-				INT_s <= not INT_n;
-				if NMICycle = '1' then
-					NMI_s <= '0';
-				elsif NMI_n = '0' and OldNMI_n = '1' then
-					NMI_s <= '1';
-				end if;
-				OldNMI_n := NMI_n;
-			end if;
-			
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, RestorePC_n, CLK_n)
-	begin
-
-		if CLK_n'event and CLK_n = '1' then
-			if RESET_n = '0' then
-				MCycle <= "001";
-				TState <= "000";
-				Pre_XY_F_M <= "000";
-				Halt_FF <= '0';
-				BusAck <= '0';
-				NMICycle <= '0';
-				IntCycle <= '0';
-				IntE_FF1 <= '0';
-				IntE_FF2 <= '0';
-				No_BTR <= '0';
-				Auto_Wait_t1 <= '0';
-				Auto_Wait_t2 <= '0';
-				M1_n <= '1';
-			
-			elsif RestorePC_n = '0' then
-				MCycle <= "001";
-				TState <= "001";
-				NMICycle <= '0';
-				IntCycle <= '0';
-				IntE_FF1 <= RestoreINT(2);
-				IntE_FF2 <= RestoreINT(3);
-
-				Pre_XY_F_M <= "000";
-				Halt_FF <= '0';
-				BusAck <= '0';
-				No_BTR <= '0';
-				Auto_Wait_t1 <= '0';
-				Auto_Wait_t2 <= '0';
-
-			elsif CEN = '1' then
-				if T_Res = '1' then
-					Auto_Wait_t1 <= '0';
-				else
-					Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-				end if;
-				Auto_Wait_t2 <= Auto_Wait_t1;
-				No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-						(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-						(I_BTR and (not IR(4) or F(Flag_Z)));
-				if TState = 2 then
-					if SetEI = '1' then
-						IntE_FF1 <= '1';
-						IntE_FF2 <= '1';
-					end if;
-					if I_RETN = '1' then
-						IntE_FF1 <= IntE_FF2;
-					end if;
-				end if;
-				if TState = 3 then
-					if SetDI = '1' then
-						IntE_FF1 <= '0';
-						IntE_FF2 <= '0';
-					end if;
-				end if;
-				if IntCycle = '1' or NMICycle = '1' then
-					Halt_FF <= '0';
-				end if;
-				if MCycle = "001" and TState = 2 and Wait_n = '1' then
-					M1_n <= '1';
-				end if;
-				if BusReq_s = '1' and BusAck = '1' then
-				else
-					BusAck <= '0';
-					if TState = 2 and Wait_n = '0' then
-					elsif T_Res = '1' then
-						if Halt = '1' then
-							Halt_FF <= '1';
-						end if;
-						if BusReq_s = '1' then
-							BusAck <= '1';
-						else
-							TState <= "001";
-							
-							if NextIs_XY_Fetch = '1' then
-								MCycle <= "110";
-								Pre_XY_F_M <= MCycle;
-								if IR = "00110110" and Mode = 0 then
-									Pre_XY_F_M <= "010";
-								end if;
-							elsif (MCycle = MCycles) or
-								No_BTR = '1' or
-								(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') or
-								( MCycle = "111" and MCycles= "001" and Pre_XY_F_M = "001" ) then
-								M1_n <= '0';
-								MCycle <= "001";
-								IntCycle <= '0';
-								NMICycle <= '0';
-								if NMI_s = '1' and Prefix = "00" then
-									NMICycle <= '1';
-									IntE_FF1 <= '0';
-								elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-									IntCycle <= '1';
-									IntE_FF1 <= '0';
-									IntE_FF2 <= '0';
-								end if;
-							elsif (MCycle = "111") or
-								(MCycle = "110" and Mode = 1 and ISet /= "01") then
-								MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-							else
-								MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-							end if;
-						end if;
-					else
-						if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-							(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-							TState <= TState + 1;
-						end if;
-					end if;
-				end if;
-				if TState = 0 then
-					M1_n <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/cores/JupiterAce/T80_ALU.vhd b/cores/JupiterAce/T80_ALU.vhd
deleted file mode 100644
index 86fddce..0000000
--- a/cores/JupiterAce/T80_ALU.vhd
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/cores/JupiterAce/T80_MCode.vhd b/cores/JupiterAce/T80_MCode.vhd
deleted file mode 100644
index 15e2816..0000000
--- a/cores/JupiterAce/T80_MCode.vhd
+++ /dev/null
@@ -1,1971 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					--TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					--TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				--TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" or MCycle = "111" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" or MCycle = "111" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				else
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 7 =>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						Set_BusB_To(2 downto 0) <= "110";
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Set_Addr_To <= aXY;
-					when 4 =>
-						Write <= '1';
-					when others =>
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				else
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 7 =>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						Set_BusB_To(2 downto 0) <= "110";
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Set_Addr_To <= aXY;
-					when 4 =>
-						Write <= '1';
-					when others =>
-					end case;
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-                    TStates <= "101";
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "011";  -- "100"
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/cores/JupiterAce/T80_Pack.vhd b/cores/JupiterAce/T80_Pack.vhd
deleted file mode 100644
index d1b11e1..0000000
--- a/cores/JupiterAce/T80_Pack.vhd
+++ /dev/null
@@ -1,215 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic;
-
-		SavePC      : out std_logic_vector(15 downto 0);
-		SaveINT     : out std_logic_vector(7 downto 0);
-		RestorePC   : in std_logic_vector(15 downto 0);
-		RestoreINT  : in std_logic_vector(7 downto 0);
-		
-		RestorePC_n : in std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/cores/JupiterAce/T80_Reg.vhd b/cores/JupiterAce/T80_Reg.vhd
deleted file mode 100644
index 828485f..0000000
--- a/cores/JupiterAce/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/cores/JupiterAce/T80a.vhd b/cores/JupiterAce/T80a.vhd
deleted file mode 100644
index 5e1224e..0000000
--- a/cores/JupiterAce/T80a.vhd
+++ /dev/null
@@ -1,286 +0,0 @@
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		D			: inout std_logic_vector(7 downto 0);
-
-		SavePC      : out std_logic_vector(15 downto 0);
-		SaveINT     : out std_logic_vector(7 downto 0);
-		RestorePC   : in std_logic_vector(15 downto 0);
-		RestoreINT  : in std_logic_vector(7 downto 0);
-		
-		RestorePC_n : in std_logic
-		
-	);
-end T80a;
-
-architecture rtl of T80a is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
-	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
-	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
-	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
-	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
-	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
-	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
-	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
-	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
-			DInst => D,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n,
-			
-			SavePC => SavePC,
-			SaveINT => SaveINT,
-			RestorePC => RestorePC,
-			RestoreINT => RestoreINT,
-			
-			RestorePC_n => RestorePC_n );
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
-				DI_Reg <= to_x01(D);
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-    -- IORQ_n_i uses a different timming than MREQ.
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			IORQ_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" then
-				if TState = "001" then
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					IORQ_n_i <= '1';
-				end if;
-			else
-				if TState = "001" then
-					IORQ_n_i <= not IORQ;
-				end if;
-				if TState = "011" then
-					IORQ_n_i <= '1';
-				end if;
-			end if;
-		end if;
-	end process;
-end;
diff --git a/cores/JupiterAce/fpga_ace.v b/cores/JupiterAce/fpga_ace.v
index 3c8fa3e..9a88d70 100644
--- a/cores/JupiterAce/fpga_ace.v
+++ b/cores/JupiterAce/fpga_ace.v
@@ -22,17 +22,18 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module fpga_ace (
-    input wire clkram,
+   input wire clkram,
 	input wire clk65,
-    input wire clkcpu,
+   input wire clkcpu,
 	input wire reset,
 	input wire ear,
 	output wire [7:0] filas,
 	input wire [4:0] columnas,
 	output wire video,
-	output wire sync,
-    output wire mic,
-    output wire spk
+	output wire hsync,
+	output wire vsync,
+   output wire mic,
+   output wire spk
 	);
 	
 	// Los buses del Z80
@@ -40,24 +41,31 @@ module fpga_ace (
 	wire [7:0] DoutZ80;
 	wire [15:0] AZ80;
 	
+   // Señales de control, direccion y datos de parte de todas las memorias
 	wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
-    wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
-    wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
-    wire [7:0] sram_data, cram_data;
-    wire [9:0] sram_addr, cram_addr;
+   wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
+   wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
+   wire [7:0] sram_data, cram_data;
+   wire [9:0] sram_addr, cram_addr;
+    
+   // Señales para la implementación de la habilitación de escritura en ROM
+   wire enable_write_to_rom;
+   wire [7:0] dout_modulo_enable_write;
+   wire modulo_enable_write_oe;
 
 	// Copia del bus de direcciones para las filas del teclado
-    assign filas = AZ80[15:8];
+   assign filas = AZ80[15:8];
 
-    // Multiplexor para asignar un valor al bus de datos de entrada del Z80
-    assign DinZ80 = (rom_enable == 1'b1)?        dout_rom :
-                    (sram_enable == 1'b1)?       dout_sram :
-                    (cram_enable == 1'b1)?       dout_cram :
-                    (uram_enable == 1'b1)?       dout_uram :
-                    (xram_enable == 1'b1)?       dout_xram :
-                    (eram_enable == 1'b1)?       dout_eram :
-                    (data_from_jace_oe == 1'b1)? data_from_jace :
-                                                 sram_data | cram_data;  // By default, this is what the data bus sees
+   // Multiplexor para asignar un valor al bus de datos de entrada del Z80
+   assign DinZ80 = (rom_enable == 1'b1)?        dout_rom :
+                   (sram_enable == 1'b1)?       dout_sram :
+                   (cram_enable == 1'b1)?       dout_cram :
+                   (uram_enable == 1'b1)?       dout_uram :
+                   (xram_enable == 1'b1)?       dout_xram :
+                   (eram_enable == 1'b1)?       dout_eram :
+                   (modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
+                   (data_from_jace_oe == 1'b1)? data_from_jace :
+                                                sram_data | cram_data;  // By default, this is what the data bus sees
 
 	// Memoria del equipo
 	ram1k_dualport sram (
@@ -112,8 +120,11 @@ module fpga_ace (
 	/* La ROM */
 	rom the_rom(
 	   .clk(clkram),
+       .ce(rom_enable),
 	   .a(AZ80[12:0]),
-	   .dout(dout_rom)
+       .din(DoutZ80),
+	   .dout(dout_rom),
+       .we(~wr_n & enable_write_to_rom)
 		);
 	
 	/* La CPU */
@@ -155,7 +166,21 @@ module fpga_ace (
         .spk(spk),
         .mic(mic),
         .video(video),
-        .csync(sync)
+        .hsync_pal(hsync),
+		  .vsync_pal(vsync)
     );
+    
+    io_write_to_rom modulo_habilitador_escrituras (
+        .clk(clk65),
+        .a(AZ80),
+        .iorq_n(iorq_n),
+        .rd_n(rd_n),
+        .wr_n(wr_n),
+        .din(DoutZ80),
+        .dout(dout_modulo_enable_write),
+        .dout_oe(modulo_enable_write_oe),
+        .enable_write_to_rom(enable_write_to_rom)
+    );
+    
 endmodule
 
diff --git a/cores/JupiterAce/jace_logic.v b/cores/JupiterAce/jace_logic.v
index 78481da..2814ffd 100644
--- a/cores/JupiterAce/jace_logic.v
+++ b/cores/JupiterAce/jace_logic.v
@@ -50,7 +50,8 @@ module jace_logic (
     output reg spk,
     output reg mic,
     output wire video,
-    output wire csync
+    output wire hsync_pal,
+	 output wire vsync_pal
     );
     
     initial begin
@@ -62,6 +63,7 @@ module jace_logic (
     reg [8:0] cntpix = 9'd0;
     reg [8:0] cntscn = 9'd0;
     wire [17:0] cnt = {cntscn, cntpix};
+	 
     always @(posedge clk) begin
         if (cntpix != 9'd415)
             cntpix <= cntpix + 9'd1;
@@ -91,7 +93,9 @@ module jace_logic (
             hsync = 1'b1;
     end
     
-    assign csync = hsync & vsync;
+    //assign csync = hsync & vsync;
+	 assign hsync_pal = hsync;
+	 assign vsync_pal = vsync;
     
     reg viden; // VIDEN signal in schematic
     always @* begin
diff --git a/cores/JupiterAce/jupiter_ace.prj b/cores/JupiterAce/jupiter_ace.prj
index 894ba1c..579de23 100644
--- a/cores/JupiterAce/jupiter_ace.prj
+++ b/cores/JupiterAce/jupiter_ace.prj
@@ -3,11 +3,13 @@ verilog work "tv80_mcode.v"
 verilog work "tv80_alu.v"
 verilog work "tv80_core.v"
 verilog work "tv80n.v"
-verilog work "rom.v"
 verilog work "ps2_port.v"
 verilog work "memorias.v"
 verilog work "jace_logic.v"
+verilog work "io_write_to_rom.v"
+verilog work "vga_scandoubler.v"
 verilog work "relojes.v"
+verilog work "multiboot.v"
 verilog work "keyboard_for_ace.v"
 verilog work "fpga_ace.v"
 verilog work "jupiter_ace.v"
diff --git a/cores/JupiterAce/jupiter_ace.v b/cores/JupiterAce/jupiter_ace.v
index 18f3eca..6f3c3ff 100644
--- a/cores/JupiterAce/jupiter_ace.v
+++ b/cores/JupiterAce/jupiter_ace.v
@@ -6,7 +6,7 @@
 // 
 // Create Date:    17:18:12 11/07/2015 
 // Design Name: 
-// Module Name:    tld_jace_spartan6 
+// Module Name:    jupiter_ace 
 // Project Name: 
 // Target Devices: 
 // Tool versions: 
@@ -29,24 +29,32 @@ module jupiter_ace (
     output wire [2:0] r,
     output wire [2:0] g,
     output wire [2:0] b,
-    output wire csync,
+    output wire hsync,
+	 output wire vsync,
     output wire stdn,
-    output wire stdnb
+    output wire stdnb,
+    ///// SRAM pins (just to get the current video output setting) ////////////
+    output wire [20:0] sram_addr,
+    input wire [7:0] sram_data,
+    output wire sram_we_n
     );
     
-    wire clkram; // 50MHz (maybe less if needed) to clock internal RAM/ROM
+    wire clkram; // 26.666666MHz to clock internal RAM/ROM
     wire clk65;  // 6.5MHz main frequency Jupiter ACE
     wire clkcpu; // CPU CLK
+	 wire clkvga; // Twice the original pixel clock
     
     wire kbd_reset;
+    wire kbd_mreset;
     wire [7:0] kbd_rows;
     wire [4:0] kbd_columns;
     wire video; // 1-bit video signal (black/white)
     
-    // Trivial conversion from B/W video to RGB
-    assign r = {video,video,1'b0};
-    assign g = {video,video,1'b0};
-    assign b = {video,video,1'b0};
+    // Trivial conversion from B/W video to RGB for the scandoubler
+	 wire pal_hsync, pal_vsync; // inputs to the scandoubler
+    wire [2:0] ri = {video,video,1'b0};
+    wire [2:0] gi = {video,video,1'b0};
+    wire [2:0] bi = {video,video,1'b0};
     
     // Trivial conversion for audio
     wire mic,spk;
@@ -56,19 +64,27 @@ module jupiter_ace (
     // Select PAL
     assign stdn = 1'b0;  // PAL selection for AD724
     assign stdnb = 1'b1;  // 4.43MHz crystal selected
+
+    // Initial video output settings
+    reg [7:0] scandblr_reg; // same layout as in the Spectrum core, SCANDBLR_CTRL
     
     // Power-on RESET (8 clocks)
     reg [7:0] poweron_reset = 8'h00;
-    always @(posedge clk65)
+    assign sram_addr = 21'h008FD5;  // magic place where the scandoubler settings have been stored
+    assign sram_we_n = 1'b1;
+    always @(posedge clk65) begin
+        if (poweron_reset == 1'b0)
+           scandblr_reg <= sram_data;
         poweron_reset <= {poweron_reset[6:0],1'b1};
+    end
     
     cuatro_relojes system_clocks_pll (
         .CLK_IN1(clk50mhz),
-        .CLK_OUT1(clkram),  // for driving synch RAM and ROM = 26.6666 MHz
-        .CLK_OUT2(clk65),   // video clock = 6.66666 MHz
-        .CLK_OUT3(clkcpu),  // CPU clock = 0.5 video clock
-        .CLK_OUT4()         // Super CPU clock (just a test)
- );
+        .CLK_OUT1(clkram),  // for driving RAM and ROM = 26 MHz
+        .CLK_OUT2(clkvga),  // VGA clock: 2 x video clock
+        .CLK_OUT3(clk65),   // video clock = 6.5 MHz
+        .CLK_OUT4(clkcpu)   // CPU clock = 3.25 MHz
+    );
     
     fpga_ace the_core (
         .clkram(clkram),
@@ -79,7 +95,8 @@ module jupiter_ace (
         .filas(kbd_rows),
         .columnas(kbd_columns),
         .video(video),
-        .sync(csync),
+        .hsync(pal_hsync),
+		  .vsync(pal_vsync),
         .mic(mic),
         .spk(spk)
 	);
@@ -91,7 +108,30 @@ module jupiter_ace (
         .rows(kbd_rows),
         .columns(kbd_columns),
         .kbd_reset(kbd_reset),
-        .kbd_nmi()
+        .kbd_nmi(),
+        .kbd_mreset(kbd_mreset)        
     );
+	 
+	vga_scandoubler #(.CLKVIDEO(6500)) salida_vga (
+		.clkvideo(clk65),
+		.clkvga(clkvga),
+      .enable_scandoubling(scandblr_reg[0]),
+      .disable_scaneffect(~scandblr_reg[1]),
+		.ri(ri),
+		.gi(gi),
+		.bi(bi),
+		.hsync_ext_n(pal_hsync),
+		.vsync_ext_n(pal_vsync),
+		.ro(r),
+		.go(g),
+		.bo(b),
+		.hsync(hsync),
+		.vsync(vsync)
+   );	 
+   
+   multiboot return_to_main_core (
+      .clk_icap(clkvga),
+      .mrst_n(kbd_mreset)
+   );
 
 endmodule
diff --git a/cores/JupiterAce/jupiter_ace.xst b/cores/JupiterAce/jupiter_ace.xst
index f22e93a..29822f2 100644
--- a/cores/JupiterAce/jupiter_ace.xst
+++ b/cores/JupiterAce/jupiter_ace.xst
@@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
 set -xsthdpdir "xst"
 run
 -ifn jupiter_ace.prj
+-infer_ramb8 No
 -ofn jupiter_ace
 -ofmt NGC
 -p xc6slx9-2-tqg144
 -top jupiter_ace
--opt_mode Area
--opt_level 1
+-opt_mode Speed
+-opt_level 2
 -power NO
+-uc "timings.xcf"
 -iuc NO
 -keep_hierarchy No
 -netlist_hierarchy As_Optimized
 -rtlview Yes
 -glob_opt AllClockNets
 -read_cores YES
--write_timing_constraints NO
+-write_timing_constraints YES
 -cross_clock_analysis NO
 -hierarchy_separator /
 -bus_delimiter <>
@@ -25,8 +27,7 @@ run
 -dsp_utilization_ratio 100
 -lc Auto
 -reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
+-fsm_extract NO
 -fsm_style LUT
 -ram_extract Yes
 -ram_style Auto
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
index 14a1b53..41f557e 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P2"   | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"           LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P92"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P51"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P50"  | IOSTANDARD = LVCMOS33;
 
@@ -29,38 +29,38 @@ NET "dataps2"         LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
 #NET "mousedata"       LOC="P56"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 # SRAM
-#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>"                IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>"                IOSTANDARD = LVCMOS33;
 
-#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>"    LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>"    LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>"    LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>"    LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>"    LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>"    LOC="P100" | IOSTANDARD = LVCMOS33;
 
-#NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
 
 # SPI Flash
 #NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
index 3f0861a..dd9a00d 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P10"  | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P67"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P66"  | IOSTANDARD = LVCMOS33;
 
@@ -29,38 +29,38 @@ NET "dataps2"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
 #NET "mousedata"       LOC="P95"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 # SRAM
-#NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>"   LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>"    LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>"   LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>"   LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>"   LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>"   LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>"   LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>"   LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>"   LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>"                IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>"                IOSTANDARD = LVCMOS33;
 
-#NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>"    LOC="P99"  | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>"    LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>"    LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>"    LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>"    LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>"    LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>"    LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>"    LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>"    LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>"    LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>"    LOC="P104" | IOSTANDARD = LVCMOS33;
 
-#NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
 
 # SPI Flash
 #NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
@@ -86,6 +86,6 @@ NET "dataps2"         LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
 #NET "joyfire3"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
-# Otros
+
 
 
diff --git a/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
index 1c0ef86..01eb3b3 100644
--- a/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
+++ b/cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P10"  | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P93"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P92"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87" | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85" | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P66"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P67"  | IOSTANDARD = LVCMOS33;
 
@@ -29,38 +29,38 @@ NET "dataps2"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
 #NET "mousedata"       LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 # SRAM
-#NET "sram_addr<0>"    LOC="P141" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<1>"    LOC="P139" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<2>"    LOC="P137" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<3>"    LOC="P134" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<4>"    LOC="P133" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<5>"    LOC="P120" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<6>"    LOC="P118" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<7>"    LOC="P116" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<8>"    LOC="P114" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<9>"    LOC="P112" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<10>"   LOC="P104" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<11>"   LOC="P102" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<12>"   LOC="P101" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<13>"   LOC="P100" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<14>"   LOC="P111" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<16>"   LOC="P138" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<17>"   LOC="P140" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<18>"   LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<0>"    LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<1>"    LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<2>"    LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<3>"    LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<4>"    LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<5>"    LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<6>"    LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<7>"    LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<8>"    LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<9>"    LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<10>"   LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<11>"   LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<12>"   LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<13>"   LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<14>"   LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<15>"   LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<16>"   LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<17>"   LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<18>"   LOC="P142" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<19>"   LOC="P105" | IOSTANDARD = LVCMOS33;
+NET "sram_addr<20>"   LOC="P143" | IOSTANDARD = LVCMOS33;
 
-#NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<1>"    LOC="P127" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<2>"    LOC="P124" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<3>"    LOC="P123" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<4>"    LOC="P115" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<5>"    LOC="P117" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<6>"    LOC="P119" | IOSTANDARD = LVCMOS33;
-#NET "sram_data<7>"    LOC="P126" | IOSTANDARD = LVCMOS33;
+NET "sram_data<0>"    LOC="P132" | IOSTANDARD = LVCMOS33;
+NET "sram_data<1>"    LOC="P127" | IOSTANDARD = LVCMOS33;
+NET "sram_data<2>"    LOC="P124" | IOSTANDARD = LVCMOS33;
+NET "sram_data<3>"    LOC="P123" | IOSTANDARD = LVCMOS33;
+NET "sram_data<4>"    LOC="P115" | IOSTANDARD = LVCMOS33;
+NET "sram_data<5>"    LOC="P117" | IOSTANDARD = LVCMOS33;
+NET "sram_data<6>"    LOC="P119" | IOSTANDARD = LVCMOS33;
+NET "sram_data<7>"    LOC="P126" | IOSTANDARD = LVCMOS33;
 
-#NET "sram_we_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_we_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
 
 # SPI Flash
 #NET "flash_cs_n"      LOC="P38"  | IOSTANDARD = LVCMOS33;
diff --git a/cores/JupiterAce/keyboard_for_ace.v b/cores/JupiterAce/keyboard_for_ace.v
index 12deba5..ba412f0 100644
--- a/cores/JupiterAce/keyboard_for_ace.v
+++ b/cores/JupiterAce/keyboard_for_ace.v
@@ -25,12 +25,14 @@ module keyboard_for_ace(
     input wire [7:0] rows,
     output wire [4:0] columns,
     output reg kbd_reset,
-    output reg kbd_nmi
+    output reg kbd_nmi,
+    output reg kbd_mreset
     );
 
     initial begin
         kbd_reset = 1'b1;
         kbd_nmi = 1'b1;
+        kbd_mreset = 1'b1;
     end
 
     `include "mapa_teclado_es.vh"
@@ -85,7 +87,13 @@ module keyboard_for_ace(
                     shift_pressed <= ~is_released;
                 `KEY_LCTRL,
                 `KEY_RCTRL:
-                    ctrl_pressed <= ~is_released;
+                    begin
+                        ctrl_pressed <= ~is_released;
+                        if (is_extended)
+                            matrix[0][1] <= is_released;  // Right control = Symbol shift
+                        else
+                            matrix[0][0] <= is_released;  // Left control = Caps shift
+                    end
                 `KEY_LALT:
                     alt_pressed <= ~is_released;
                 `KEY_KPPUNTO:
@@ -113,7 +121,10 @@ module keyboard_for_ace(
                         matrix[7][0] <= is_released;
                     end
                 `KEY_BKSP:
-                    begin
+                    if (ctrl_pressed && alt_pressed) begin
+                        kbd_mreset <= is_released;                        
+                    end
+                    else begin
                         matrix[0][0] <= is_released;
                         matrix[4][0] <= is_released;
                     end
diff --git a/cores/JupiterAce/memorias.v b/cores/JupiterAce/memorias.v
index d59c279..45ce2cb 100644
--- a/cores/JupiterAce/memorias.v
+++ b/cores/JupiterAce/memorias.v
@@ -20,6 +20,28 @@
 //
 //////////////////////////////////////////////////////////////////////////////////
 
+module rom (
+    input wire clk,
+    input wire ce,
+    input wire [12:0] a,
+    input wire we,
+    input wire [7:0] din,
+    output reg [7:0] dout
+    );
+
+   reg [7:0] mem[0:8191];
+   integer i;
+   initial begin  // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
+      $readmemh ("ace.hex", mem, 0);
+   end
+
+   always @(posedge clk) begin
+     dout <= mem[a];
+     if (we == 1'b1 && ce == 1'b1)
+        mem[a] <= din;
+   end
+endmodule
+
 module ram1k (
 	input wire clk,
     input wire ce,
diff --git a/cores/JupiterAce/relojes.v b/cores/JupiterAce/relojes.v
index 592c2c2..4e24039 100644
--- a/cores/JupiterAce/relojes.v
+++ b/cores/JupiterAce/relojes.v
@@ -61,7 +61,7 @@ module cuatro_relojes
   output wire       CLK_OUT4
  );
 
-  wire clkin1,clkout0,clkout1,clkout2,clkout3;
+  wire clkin1,clkout0;
   // Input buffering
   //------------------------------------
   IBUFG clkin1_buf
@@ -76,47 +76,39 @@ module cuatro_relojes
   //    * Unused outputs are labeled unused
   wire [15:0] do_unused;
   wire        drdy_unused;
-  wire        locked_unused;
   wire        clkfbout;
   wire        clkfbout_buf;
-  wire        clkout4_unused;
-  wire        clkout5_unused;
 
   PLL_BASE
   #(.BANDWIDTH              ("OPTIMIZED"),
     .CLK_FEEDBACK           ("CLKFBOUT"),
     .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
     .DIVCLK_DIVIDE          (1),
-    .CLKFBOUT_MULT          (8),
+    .CLKFBOUT_MULT          (13),
     .CLKFBOUT_PHASE         (0.000),
-    .CLKOUT0_DIVIDE         (15),
+    .CLKOUT0_DIVIDE         (25),
     .CLKOUT0_PHASE          (0.000),
     .CLKOUT0_DUTY_CYCLE     (0.500),
-    .CLKOUT1_DIVIDE         (60),
-    .CLKOUT1_PHASE          (0.000),
-    .CLKOUT1_DUTY_CYCLE     (0.500),
-    .CLKOUT2_DIVIDE         (120),
-    .CLKOUT2_PHASE          (0.000),
-    .CLKOUT3_DIVIDE         (30),
-    .CLKOUT3_PHASE          (0.000),
-    .CLKOUT2_DUTY_CYCLE     (0.500),
     .CLKIN_PERIOD           (20.0),
     .REF_JITTER             (0.010))
   pll_base_inst
     // Output clocks
    (.CLKFBOUT              (clkfbout),
     .CLKOUT0               (clkout0),
-    .CLKOUT1               (clkout1),
-    .CLKOUT2               (clkout2),
-    .CLKOUT3               (clkout3),
-    .CLKOUT4               (clkout4_unused),
-    .CLKOUT5               (clkout5_unused),
-    .LOCKED                (locked_unused),
+    .CLKOUT1               (),
+    .CLKOUT2               (),
+    .CLKOUT3               (),
+    .CLKOUT4               (),
+    .CLKOUT5               (),
+    .LOCKED                (),
     .RST                   (1'b0),
      // Input clock control
     .CLKFBIN               (clkfbout_buf),
     .CLKIN                 (clkin1));
 
+  reg [2:0] clkdivider = 3'b000;
+  always @(posedge clkout0)
+   clkdivider <= clkdivider + 3'b001;
 
   // Output buffering
   //-----------------------------------
@@ -124,22 +116,20 @@ module cuatro_relojes
    (.O (clkfbout_buf),
     .I (clkfbout));
 
-
   BUFG clkout1_buf
    (.O   (CLK_OUT1),
     .I   (clkout0));
 
-
   BUFG clkout2_buf
    (.O   (CLK_OUT2),
-    .I   (clkout1));
+    .I   (clkdivider[0]));
 
   BUFG clkout3_buf
    (.O   (CLK_OUT3),
-    .I   (clkout2));
+    .I   (clkdivider[1]));
 
   BUFG clkout4_buf
    (.O   (CLK_OUT4),
-    .I   (clkout3));
+    .I   (clkdivider[2]));
 
 endmodule
diff --git a/cores/JupiterAce/rom.v b/cores/JupiterAce/rom.v
deleted file mode 100644
index 8145ce2..0000000
--- a/cores/JupiterAce/rom.v
+++ /dev/null
@@ -1,36 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    04:12:52 02/09/2014 
-// Design Name: 
-// Module Name:    rom 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module rom (
-    input wire clk,
-    input wire [12:0] a,
-    output reg [7:0] dout
-    );
-
-   reg [7:0] mem[0:8191];
-   integer i;
-   initial begin  // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
-      $readmemh ("ace.hex", mem, 0);
-   end
-
-   always @(posedge clk) begin
-     dout <= mem[a[12:0]];
-   end
-endmodule
diff --git a/cores/JupiterAce/rom8k.asy b/cores/JupiterAce/rom8k.asy
deleted file mode 100644
index cd471c3..0000000
--- a/cores/JupiterAce/rom8k.asy
+++ /dev/null
@@ -1,21 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 rom8k
-RECTANGLE Normal 32 32 544 672
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName addra[12:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName ena
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName clka
-PINATTR Polarity IN
-LINE Wide 576 80 544 80
-PIN 576 80 RIGHT 36
-PINATTR PinName douta[7:0]
-PINATTR Polarity OUT
-
diff --git a/cores/JupiterAce/rom8k.gise b/cores/JupiterAce/rom8k.gise
deleted file mode 100644
index 61efe22..0000000
--- a/cores/JupiterAce/rom8k.gise
+++ /dev/null
@@ -1,33 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="rom8k.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="rom8k.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="rom8k.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="rom8k.veo" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/cores/JupiterAce/rom8k.mif b/cores/JupiterAce/rom8k.mif
deleted file mode 100644
index ad2c368..0000000
--- a/cores/JupiterAce/rom8k.mif
+++ /dev/null
@@ -1,8192 +0,0 @@
-11110011
-00100001
-00000000
-00111100
-00111110
-11111100
-00011000
-00100000
-11011001
-11011101
-11001011
-00111110
-01011110
-11000011
-11101110
-00000011
-00101010
-00111011
-00111100
-01110011
-00100011
-11000011
-01011111
-00001000
-00101010
-00111011
-00111100
-00101011
-01010110
-11000011
-01011001
-00001000
-11100001
-01111110
-00110010
-00111101
-00111100
-11000011
-10101101
-00000000
-00100100
-01110111
-10111110
-00101000
-11111011
-10100100
-01100111
-00100010
-00011000
-00111100
-11111001
-00100001
-00001101
-00000001
-00011000
-00000011
-11000011
-00111010
-00000001
-00010001
-00100100
-00111100
-00000001
-00101101
-00000000
-11101101
-10110000
-11011101
-00100001
-00000000
-00111100
-11111101
-00100001
-11001000
-00000100
-11001101
-00100100
-00001010
-10101111
-00110010
-00000000
-00100111
-00100001
-00000000
-00101100
-01111101
-11100110
-10111111
-00001111
-00001111
-00001111
-00110000
-00000010
-00001111
-00001111
-00001111
-01000111
-10011111
-11001011
-00011000
-01000111
-10011111
-10101000
-11100110
-11110000
-10101000
-01110111
-00101100
-00100000
-11100111
-00010001
-11111111
-00101111
-00100001
-11111011
-00011111
-00000001
-00001000
-00000000
-11101101
-10111000
-11101011
-00111110
-01011111
-00001110
-00000111
-11001011
-01101111
-00101000
-00000011
-01110000
-00101011
-00001101
-11101011
-11101101
-10111000
-11101011
-01110000
-00101011
-00111101
-00100000
-11101110
-11101101
-01010110
-00011000
-00001001
-01010001
-01010101
-01001001
-11010100
-00000000
-00000000
-00000100
-10011011
-00000000
-11101101
-01111011
-00011000
-00111100
-11111011
-11000011
-11110010
-00000100
-01000001
-01000010
-01001111
-01010010
-11010100
-10011000
-00000000
-00000101
-10101101
-00000000
-11111101
-11100101
-11111101
-00100001
-10111001
-00000100
-00101010
-00110111
-00111100
-00100010
-00111011
-00111100
-00100001
-00111110
-00111100
-01111110
-11100110
-10110011
-11001011
-01010110
-01110111
-00101000
-00011010
-11001101
-10111001
-00000100
-10010000
-00000100
-10110011
-00001000
-01001011
-00010000
-00000101
-11010010
-00001101
-01101011
-00001000
-00010000
-00010110
-10110101
-00010101
-00010001
-00010000
-00110111
-00111100
-11000001
-00001000
-00001110
-00011010
-11011101
-11001011
-00111101
-01111110
-00100000
-00011011
-11001101
-00001000
-00011000
-01000101
-01010010
-01010010
-01001111
-11010010
-11001101
-10111001
-00000100
-00010001
-00010000
-00111101
-00111100
-10010110
-00001000
-10110011
-00001001
-10010101
-00001010
-00001110
-00011010
-11011101
-00110110
-00111101
-11111111
-00101010
-00110111
-00111100
-00000001
-00001100
-00000000
-00001001
-00100010
-00111011
-00111100
-11111101
-11100001
-00011000
-10001110
-11100000
-00100110
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-01001100
-00111100
-01001100
-00111100
-01001111
-00111100
-01010001
-00111100
-01000101
-00111100
-01011101
-00111100
-11111111
-00000000
-00001010
-01000110
-01001111
-01010010
-01010100
-11001000
-00000000
-00000000
-11111111
-00011111
-00000101
-10110101
-00010001
-01001001
-00111100
-00000000
-00000000
-00000000
-11110101
-00001000
-11110101
-11000101
-11010101
-11100101
-00000110
-00111110
-00010000
-11111110
-00100001
-00101011
-00111100
-00110100
-00100011
-00101000
-11111100
-11001101
-00010000
-00000011
-00100001
-00101000
-00111100
-11001011
-01000110
-00101000
-00100001
-10100111
-00101000
-00011110
-11111110
-00100000
-00111000
-00010100
-11001011
-01001110
-11000100
-00000111
-00001000
-11001011
-01010110
-00101000
-00000010
-11100110
-10011111
-11001011
-01011110
-00101000
-00000010
-11110110
-10000000
-11001101
-10010110
-00000001
-11001101
-11100110
-00000001
-11001101
-10000010
-00000010
-11100001
-11010001
-11000001
-11110001
-00001000
-11110001
-11111011
-11001001
-11111110
-00001101
-00100000
-00010100
-00100001
-00000000
-00100111
-00100010
-00100010
-00111100
-00100010
-00100000
-00111100
-10101111
-11001101
-10011000
-00000001
-00100001
-11100000
-00100110
-00100010
-00011110
-00111100
-11001001
-10100111
-11001000
-00001000
-00101010
-00100010
-00111100
-01111110
-10100111
-00101000
-00000110
-00010001
-00000000
-11011001
-00011001
-00110000
-00101000
-11101101
-01011011
-00100100
-00111100
-00100001
-10100000
-11011011
-00011001
-00110000
-00110100
-00101010
-00011100
-00111100
-00000001
-00100000
-00000000
-00001001
-11101101
-01010010
-11010101
-11010100
-00100001
-00000100
-11001101
-10110000
-00000010
-11010001
-11001101
-00101111
-00000100
-00100001
-00011110
-00111100
-00000110
-00000100
-11001101
-01000011
-00000100
-00010000
-11111011
-11001101
-00000010
-00000011
-01010100
-01011101
-00100011
-00100010
-00100010
-00111100
-00101011
-00101011
-00101000
-00000010
-11101101
-10111000
-00001000
-00010010
-00010011
-11101101
-01010011
-00100000
-00111100
-10101111
-11001001
-00100001
-11110000
-00000001
-00010110
-00000000
-01011111
-00011001
-01011110
-00011001
-11101001
-00100000
-00010011
-00001100
-00011110
-00001010
-00110111
-00011010
-01010000
-00000110
-10011100
-11001001
-00010101
-00010100
-11010011
-00100001
-00101000
-00111100
-10101110
-01110111
-11001001
-00101010
-00100000
-00111100
-00101011
-01111110
-10100111
-11001000
-00100010
-00100000
-00111100
-00100011
-01110111
-11001001
-00101010
-00100000
-00111100
-00100011
-11101101
-01011011
-00100010
-00111100
-10100111
-11101101
-01010010
-11001000
-00011001
-00100010
-00100000
-00111100
-01111110
-00101011
-01110111
-11001001
-00101010
-00100000
-00111100
-00100011
-00100010
-00100000
-00111100
-11001101
-00000010
-00000011
-01100010
-01101011
-00011011
-00011010
-10100111
-11001000
-11101101
-01010011
-00100000
-00111100
-01111000
-10110001
-00101000
-00000010
-11101101
-10110000
-00101011
-00110110
-00100000
-00100010
-00100010
-00111100
-00001100
-11001001
-11001101
-00000100
-00000010
-00101000
-00001000
-00000110
-00011111
-11001101
-00000100
-00000010
-00010000
-11111011
-11001001
-00101010
-00011110
-00111100
-11101101
-01011011
-00100100
-00111100
-10100111
-11101101
-01010010
-11001000
-11001101
-00100101
-00000010
-00101010
-00011110
-00111100
-00010001
-11100000
-11111111
-10101111
-00011001
-10111110
-00100000
-11111100
-00100010
-00011110
-00111100
-11001101
-11110100
-00000010
-00100010
-00100000
-00111100
-00111110
-10100000
-11001101
-01111110
-00000001
-00101010
-00100000
-00111100
-00101011
-00100010
-00100000
-00111100
-00101010
-00100000
-00111100
-00111010
-00101000
-00111100
-00011111
-00110110
-10010111
-00011111
-00110000
-00000010
-00110110
-11000011
-00011111
-11010000
-00110110
-11000111
-11001001
-11001101
-00010001
-00000010
-00101000
-00001000
-00000110
-00011111
-11001101
-00010001
-00000010
-00010000
-11111011
-11001001
-11001101
-10110000
-00000010
-11100000
-11100101
-11001101
-00100101
-00000010
-11100001
-11001101
-11101101
-00000010
-00011000
-11000110
-00100001
-00000000
-00100111
-11101101
-01011011
-00011110
-00111100
-10100111
-11101101
-01010010
-01000100
-01001101
-11101011
-00100011
-10101111
-11101101
-10110001
-00101011
-11001001
-00101010
-00100010
-00111100
-00101011
-00100010
-00100000
-00111100
-11001101
-00101100
-00000010
-00100000
-11111011
-11001001
-00100001
-00101000
-00111100
-11001011
-11101110
-11001011
-10000110
-11001001
-00100001
-00000000
-00100111
-11101101
-01011011
-00100100
-00111100
-11001101
-11111010
-00000111
-00100001
-11100000
-00100110
-00100010
-00100100
-00111100
-00110110
-00000000
-00101010
-00100100
-00111100
-00100010
-00011110
-00111100
-00100011
-00100010
-00100000
-00111100
-11001101
-10110000
-00000010
-00111110
-00100000
-00101011
-10111110
-00101000
-11111100
-00100011
-00100010
-00100010
-00111100
-11001001
-00101010
-00100010
-00111100
-11101101
-01011011
-00100000
-00111100
-10100111
-11101101
-01010010
-01000100
-01001101
-00011001
-11001001
-11001101
-00110110
-00000011
-01000111
-00101010
-00100110
-00111100
-10101101
-00101000
-00001011
-10101101
-00101000
-00000011
-10101111
-10111101
-11000000
-01101000
-00100110
-00100000
-00011000
-00001101
-00100101
-01111100
-11111110
-00011110
-00101000
-00000110
-10101111
-10111100
-00100000
-00000011
-00100110
-00000100
-01111101
-00100010
-00100110
-00111100
-11001001
-00000001
-11111110
-11111110
-11101101
-01010000
-01011010
-11001011
-00111010
-10011111
-11100110
-11011000
-11001011
-00111010
-00111000
-00000010
-00111110
-00101000
-11000110
-01010111
-01101111
-01111011
-11110110
-00000011
-00011110
-11111111
-00101111
-11100110
-00011111
-01010111
-00101000
-00001101
-01111101
-00011100
-00100000
-00010010
-11010110
-00001000
-11001011
-00111010
-00110000
-11111010
-01011111
-00100000
-00001001
-00101101
-11001011
-00000000
-00110000
-00000110
-11101101
-01111000
-00011000
-11100100
-00011110
-11111111
-01111011
-00111100
-11001000
-00100001
-01110110
-00000011
-00011001
-01111110
-11001001
-01110110
-01101000
-01111001
-00110110
-00110101
-01110100
-01100111
-01100011
-01100010
-01101010
-01110101
-00110111
-00110100
-01110010
-01100110
-01111000
-01101110
-01101011
-01101001
-00111000
-00110011
-01100101
-01100100
-01111010
-01101101
-01101100
-01101111
-00111001
-00110010
-01110111
-01110011
-00000000
-00100000
-00001101
-01110000
-00110000
-00110001
-01110001
-01100001
-00000000
-01010110
-01001000
-01011001
-00000111
-00000001
-01010100
-01000111
-01000011
-01000010
-01001010
-01010101
-00001001
-00001000
-01010010
-01000110
-01011000
-01001110
-01001011
-01001001
-00000011
-00110011
-01000101
-01000100
-01011010
-01001101
-01001100
-01001111
-00000100
-00000010
-01010111
-01010011
-00000000
-00100000
-00001101
-01010000
-00000101
-00001010
-01010001
-01000001
-00000000
-00101111
-01011110
-01011011
-00100110
-00100101
-00111110
-01111101
-00111111
-00101010
-00101101
-01011101
-00100111
-00100100
-00111100
-01111011
-01100000
-00101100
-00101011
-01111111
-00101000
-00100011
-01000101
-01011100
-00111010
-00101110
-00111101
-00111011
-00101001
-01000000
-01010111
-01111100
-00000000
-00100000
-00001101
-00100010
-01011111
-00100001
-01010001
-01111110
-00000000
-00101000
-00000101
-11001101
-01111110
-00000001
-11011001
-11001001
-01000111
-00101010
-00101001
-00111100
-01111100
-10110101
-01111000
-00101000
-00000001
-11101001
-00101010
-00011100
-00111100
-11101101
-01011011
-00100100
-00111100
-11101011
-00110111
-11101101
-01010010
-11101011
-11011100
-00100001
-00000100
-11111110
-00001101
-00101000
-00000100
-01110111
-00100011
-00011000
-00000110
-00100011
-01111101
-11100110
-00011111
-00100000
-11111010
-00100010
-00011100
-00111100
-11011001
-11001001
-11110101
-00100001
-00011100
-00111100
-11001101
-01000011
-00000100
-11110001
-00101010
-00100100
-00111100
-00010001
-00100000
-00100100
-10100111
-11101101
-01010010
-01000100
-01001101
-00100001
-11100000
-11111111
-00011001
-11101011
-11101101
-10110000
-00000110
-00100000
-00101011
-00110110
-00100000
-00010000
-11111011
-11001001
-01111110
-11010110
-00100000
-01110111
-00100011
-00110000
-00000001
-00110101
-00100011
-11001001
-11101011
-01011110
-00010110
-00000000
-00100001
-00000000
-00111100
-00011001
-11101011
-11010111
-11111101
-11101001
-01001000
-01000101
-01010010
-11000101
-10101010
-00000000
-00000100
-01100010
-00000100
-11101101
-01011011
-00110111
-00111100
-11010111
-11111101
-11101001
-01000011
-01001111
-01001110
-01010100
-01000101
-01011000
-11010100
-01011111
-00000100
-00000111
-01001101
-00000100
-00110011
-01000011
-01010101
-01010010
-01010010
-01000101
-01001110
-11010100
-01110010
-00000100
-00000111
-01001101
-00000100
-00110001
-01000010
-01000001
-01010011
-11000101
-01111111
-00000100
-00000100
-01001101
-00000100
-00111111
-01001101
-00000100
-00111110
-01001101
-00000100
-00111001
-01010000
-01000001
-11000100
-10001001
-00000100
-00000011
-11110101
-00001111
-00000001
-00100111
-10111011
-10011000
-00000100
-01000001
-00001000
-00010001
-10110110
-00000100
-11011000
-00010010
-00001010
-00001110
-00011010
-00100001
-00111110
-00111100
-01111110
-11100110
-10111011
-01110111
-11111101
-11101001
-00000000
-11101000
-11111111
-10111000
-00000100
-11100001
-11100001
-01011110
-00100011
-01010110
-00100011
-11100101
-11101011
-01011110
-00100011
-01010110
-00100011
-11101011
-11101001
-11001000
-00000100
-00000001
-00001011
-00000000
-11101101
-01011011
-00111011
-00111100
-00101010
-00110111
-00111100
-00001001
-11101101
-01010010
-00111000
-00000010
-11100111
-00000010
-00000001
-00000000
-00000000
-11001101
-10001100
-00001111
-11001101
-11100100
-00000100
-00011000
-11010101
-00111110
-11111110
-11011011
-11111110
-00011111
-11011000
-00111110
-01111111
-11011011
-11111110
-00011111
-11011000
-11100111
-00000011
-11001101
-10111001
-00000100
-10001100
-00000101
-00000110
-00000101
-00110110
-00000101
-01110110
-00010010
-11110111
-11111111
-01001100
-01001001
-01001110
-11000101
-10100000
-00000100
-00000100
-11000011
-00001110
-11000110
-00000100
-00111101
-00000110
-11101110
-00001000
-10000011
-00010010
-00000111
-00000000
-01001111
-00000101
-01110110
-00010010
-11110001
-11111111
-10101001
-00000110
-11101110
-00001000
-10000011
-00010010
-00000111
-00000000
-01100100
-00000101
-01110110
-00010010
-11100011
-11111111
-00011011
-00000110
-00011010
-00001100
-10000011
-00010010
-00000011
-00000000
-10110110
-00000100
-01111000
-00000101
-01110110
-00010010
-11010011
-11111111
-00111000
-00000101
-00111010
-00111110
-00111100
-11001011
-01110111
-00100000
-00001110
-11001011
-01100111
-00100000
-00001010
-11001101
-00001000
-00011000
-00100000
-01001111
-01001011
-10100000
-00111110
-00001101
-11001111
-11111101
-11101001
-01010001
-00000101
-11011111
-00011011
-00011010
-00101111
-11011101
-10100110
-00111110
-11100110
-01000000
-00010011
-00101000
-00000100
-11010111
-00010001
-01001110
-00001111
-11000011
-10111111
-00000100
-01100110
-00000101
-11011111
-11011101
-11001011
-00111110
-01110110
-00100000
-11110100
-11111101
-11101001
-01010010
-01000101
-01010100
-01011001
-01010000
-11000101
-10001011
-00000101
-00000110
-01111010
-00000101
-11001101
-11101010
-00000010
-11001101
-01110110
-00000010
-00110110
-10111111
-00011000
-00010000
-01010001
-01010101
-01000101
-01010010
-11011001
-00000101
-00000101
-00000101
-10001110
-00000101
-11001101
-11011000
-00000010
-11001101
-01110110
-00000010
-00100001
-00101000
-00111100
-11001011
-11000110
-11001011
-10101110
-11001011
-01101110
-00101000
-11111100
-11001101
-00100101
-00000010
-11111101
-11101001
-01010111
-01001111
-01010010
-11000100
-01110111
-00000101
-00000100
-10101101
-00000101
-11011111
-00100001
-11111110
-00100111
-00000110
-11111101
-00110110
-00100000
-00101011
-00010000
-11111011
-11010101
-11101011
-11010111
-11010001
-11001101
-11100001
-00000101
-00000100
-00000101
-00101000
-00000011
-00000001
-11111111
-00000000
-00100001
-00000001
-00100111
-01110001
-00100011
-00111110
-11111100
-10111001
-00110000
-00000001
-01001111
-00001100
-11010101
-11000101
-11101011
-11101101
-10110000
-11000001
-11010001
-00001101
-11001101
-11011010
-00000111
-11111101
-11101001
-00011110
-00100000
-00101010
-00100100
-00111100
-00100010
-00011110
-00111100
-00000001
-00000000
-00000000
-00100011
-01111110
-10111011
-00101000
-11111011
-10100111
-00101000
-00001110
-11100101
-00000011
-00100011
-01111110
-10100111
-00101000
-00000011
-10111011
-00100000
-11110111
-11010001
-10101111
-10111000
-11001001
-11010101
-11001101
-10110000
-00000010
-11100010
-00010100
-00000110
-11101101
-01011011
-00100100
-00111100
-11001101
-11111010
-00000111
-00100010
-00100100
-00111100
-11010001
-00011000
-11001101
-11101011
-11000001
-00000001
-00000000
-00000000
-00110111
-11001001
-00011101
-00000110
-11001101
-11011111
-00000101
-01010000
-01011001
-11010111
-11111101
-11101001
-01010110
-01001100
-01001001
-01010011
-11010100
-10101010
-00000101
-00000101
-00101111
-00000110
-00111110
-00001101
-11001111
-00001110
-00000000
-00011000
-00001110
-01000110
-01001001
-01001110
-11000100
-00101100
-00000110
-00000100
-00111111
-00000110
-11001101
-11011111
-00000101
-00111000
-01000110
-00101010
-00110011
-00111100
-01111110
-00100011
-01100110
-01101111
-01111110
-11100110
-00111111
-00101000
-00101111
-10101001
-00101000
-00000100
-01111001
-10100111
-00100000
-00101000
-11010101
-11100101
-11001101
-11101000
-00010101
-10110001
-00101000
-00010111
-01000001
-00011010
-11001101
-00000111
-00001000
-00010011
-10101110
-11100110
-01111111
-00100011
-00100000
-00010010
-00010000
-11110011
-11010001
-00010011
-11010111
-11010001
-11001101
-11011010
-00000111
-11111101
-11101001
-11001101
-11111011
-00010111
-01110110
-11001101
-11100100
-00000100
-11100001
-11010001
-00101011
-01111110
-00101011
-01101110
-01100111
-10110101
-00100000
-11000100
-11000011
-10001010
-00000110
-00010001
-00000000
-00000000
-11010111
-11111101
-11101001
-01000101
-01011000
-01000101
-01000011
-01010101
-01010100
-11000101
-00111100
-00000110
-00000111
-10011100
-00000110
-11011111
-11000011
-10111111
-00000100
-01001110
-01010101
-01001101
-01000010
-01000101
-11010010
-10011001
-00000110
-00000110
-10101011
-00000110
-11001101
-11011111
-00000101
-00111000
-11011010
-11000101
-11010101
-11001101
-01001100
-00000111
-00100000
-00000101
-00010001
-00000110
-00010000
-00011000
-01011000
-11011111
-00010001
-00000000
-00000000
-11010111
-00010001
-00000000
-01000101
-11000001
-11000101
-00001010
-11111110
-00101101
-00100000
-00000011
-00010110
-11000101
-00000011
-11010111
-01010000
-01011001
-00101011
-00101011
-11001101
-00100011
-00000111
-00100011
-00110100
-00101011
-00110000
-11111000
-11111110
-11111110
-00100000
-00111101
-11001101
-00100011
-00000111
-00110000
-11111011
-11000110
-00110000
-11001101
-01111011
-00000111
-00100000
-00000100
-00011110
-00000000
-00011000
-00001110
-11100110
-11011111
-11111110
-01000101
-00100000
-00100111
-11100101
-11001101
-01001100
-00000111
-11011111
-11100001
-00100000
-00011111
-11001101
-01000000
-00000111
-00101000
-00001111
-00100011
-01111110
-11100110
-01111111
-10000011
-11111010
-00011100
-00000111
-00101000
-00010000
-10101110
-11100110
-01111111
-10101110
-01110111
-00010001
-01010101
-00010000
-11010111
-11010001
-11000001
-11001101
-11011010
-00000111
-11111101
-11101001
-11100001
-11100001
-11011111
-11011111
-11000011
-10001010
-00000110
-00011010
-00010011
-11010110
-00110000
-11011000
-11111110
-00001010
-00111111
-11011000
-01001111
-01111110
-11100110
-11110000
-11000000
-01111001
-00101011
-00101011
-00001110
-00000011
-11101101
-01101111
-00100011
-00001101
-00100000
-11111010
-00110101
-00101011
-10111111
-11001001
-00000110
-00000110
-10101111
-11001101
-00101100
-00000111
-11000000
-00010000
-11111001
-00100011
-01110000
-11001001
-11010111
-11001101
-10111001
-00000100
-01101011
-00001000
-10010110
-00001000
-01001011
-00010000
-00101101
-01001010
-00001100
-01101011
-00001000
-10101001
-00001101
-11010010
-00001000
-11010010
-00001101
-00011111
-00001110
-10001000
-00000110
-10001000
-00000110
-11111111
-00001000
-10001010
-00000111
-11111111
-00001000
-11011111
-00001000
-10010100
-00001101
-11111111
-00001000
-01111001
-00001000
-10000101
-00001000
-00001110
-00011010
-11011111
-00011010
-11111110
-00100000
-11001000
-10100111
-11001001
-01000011
-01001111
-01001110
-01010110
-01000101
-01010010
-11010100
-10101000
-00000110
-00000111
-11000011
-00001110
-00001001
-00001110
-01101011
-00001000
-11010010
-00001000
-10010110
-00001000
-10111000
-00000111
-10000011
-00010010
-00011011
-00000000
-10000101
-00001000
-10001010
-00000100
-10010110
-00001000
-10101000
-00001100
-01111001
-00001000
-11111111
-00001000
-10001010
-00000100
-10010110
-00001000
-10101000
-00001100
-11101110
-00001101
-11011111
-00001000
-01110110
-00010010
-11011001
-11111111
-11011111
-00001000
-10110110
-00000100
-10111010
-00000111
-11011111
-01111011
-11001101
-00000111
-00001000
-11000110
-11010000
-00110000
-00010100
-11111110
-00001010
-00111000
-00000110
-11000110
-11101111
-00110000
-00001100
-11000110
-00001010
-11011101
-10111110
-00111111
-00110000
-00000101
-00010110
-00000000
-01011111
-11010111
-00110111
-11000011
-00100001
-00001100
-01100010
-01101011
-00000011
-00001001
-11100101
-11011101
-11001011
-00111110
-01100110
-11001100
-01111111
-00001001
-11001101
-10110000
-00000010
-11010001
-10100111
-11101101
-01010010
-01000100
-01001101
-00101010
-00011110
-00111100
-00100011
-11101011
-00111000
-00000101
-00101000
-00000010
-11101101
-10110000
-10100111
-11101101
-01010010
-11101011
-01111010
-10110011
-11001000
-00110110
-00100000
-00100011
-00011011
-00011000
-11110111
-11100110
-01111111
-11111110
-01100001
-11011000
-11111110
-01111011
-11010000
-11100110
-01011111
-11001001
-01010110
-01001001
-11010011
-10001001
-00000111
-00000011
-00011010
-00001000
-11011101
-11001011
-00111110
-10100110
-11111101
-11101001
-01001001
-01001110
-01010110
-01001001
-11010011
-00010111
-00001000
-00000101
-00101010
-00001000
-11011101
-11001011
-00111110
-11100110
-11111101
-11101001
-01000110
-01000001
-01010011
-11010100
-00100111
-00001000
-00000100
-00111001
-00001000
-11111101
-00100001
-10111001
-00000100
-11111101
-11101001
-01010011
-01001100
-01001111
-11010111
-00110110
-00001000
-00000100
-01001000
-00001000
-11111101
-00100001
-11001000
-00000100
-11111101
-11101001
-00101010
-00111011
-00111100
-00101011
-01000110
-00101011
-01001110
-00100010
-00111011
-00111100
-11001001
-00101011
-01011110
-00100010
-00111011
-00111100
-11001001
-01110010
-00100011
-00100010
-00111011
-00111100
-11001001
-01000100
-01010101
-11010000
-01000101
-00001000
-00000011
-01101101
-00001000
-11011111
-11010111
-11010111
-11111101
-11101001
-01000100
-01010010
-01001111
-11010000
-01101010
-00001000
-00000100
-01111011
-00001000
-11011111
-11111101
-11101001
-01010011
-01010111
-01000001
-11010000
-01111000
-00001000
-00000100
-10000111
-00001000
-11011111
-11001101
-01001110
-00001000
-11010111
-01010000
-01011001
-11010111
-11111101
-11101001
-01000011
-11000000
-10000100
-00001000
-00000010
-10011000
-00001000
-11011111
-00011010
-01011111
-00010110
-00000000
-11010111
-11111101
-11101001
-01000011
-10100001
-10010101
-00001000
-00000010
-10100111
-00001000
-11011111
-11001101
-01001110
-00001000
-01111001
-00010010
-11111101
-11101001
-11000000
-10100100
-00001000
-00000001
-10110101
-00001000
-11011111
-11101011
-01011110
-00100011
-01010110
-11010111
-11111101
-11101001
-10100001
-10110010
-00001000
-00000001
-11000011
-00001000
-11011111
-11001101
-01001110
-00001000
-11101011
-01110001
-00100011
-01110000
-11111101
-11101001
-00111110
-11010010
-11000000
-00001000
-00000010
-11010100
-00001000
-11011111
-11000001
-11010101
-11000101
-11111101
-11101001
-01010010
-10111110
-11010001
-00001000
-00000010
-11100001
-00001000
-11000001
-11010001
-11000101
-11010111
-11111101
-11101001
-00111111
-01000100
-01010101
-11010000
-11011110
-00001000
-00000100
-11110000
-00001000
-11011111
-11010111
-01111010
-10110011
-11000100
-00010000
-00000000
-11111101
-11101001
-01010010
-01001111
-11010100
-11101101
-00001000
-00000011
-11000011
-00001110
-11010010
-00001000
-10000101
-00001000
-11011111
-00001000
-10000101
-00001000
-10110110
-00000100
-01001111
-01010110
-01000101
-11010010
-11111110
-00001000
-00000100
-11000011
-00001110
-11010010
-00001000
-01101011
-00001000
-11011111
-00001000
-10000101
-00001000
-10110110
-00000100
-01010000
-01001001
-01000011
-11001011
-00010001
-00001001
-00000100
-00100111
-00001001
-11001101
-01001101
-00001001
-11111101
-11101001
-01010010
-01001111
-01001100
-11001100
-00100100
-00001001
-00000100
-00110101
-00001001
-11001101
-01001101
-00001001
-11101011
-00101010
-00110111
-00111100
-11101101
-01010010
-11010010
-11010111
-00000100
-01100010
-01101011
-00100011
-00100011
-11101101
-10110000
-11101101
-01010011
-00111011
-00111100
-11111101
-11101001
-11001101
-01001110
-00001000
-00001011
-11001011
-00100001
-11001011
-00010000
-00000011
-00000011
-00110000
-00000010
-11100111
-00000111
-00101010
-00111011
-00111100
-11101101
-01000010
-11100101
-01011110
-00100011
-01010110
-11010111
-11100001
-11001001
-01010100
-01011001
-01010000
-11000101
-00110010
-00001001
-00000100
-01110000
-00001001
-11001101
-01001110
-00001000
-11011111
-11001101
-01111111
-00001001
-11111101
-11101001
-00011010
-01001111
-00010011
-00011010
-01000111
-00010011
-01111000
-10110001
-11001000
-00011010
-00010011
-00001011
-11001111
-00011000
-11110111
-00111100
-10100011
-01101101
-00001001
-00000010
-10001111
-00001001
-00100001
-11111111
-00100111
-00100010
-00011010
-00111100
-11111101
-11101001
-00100011
-10111110
-10001100
-00001001
-00000010
-10011110
-00001001
-11011111
-11011111
-11101101
-01011011
-00011010
-00111100
-11010111
-00100001
-11111111
-00100111
-10100111
-11101101
-01010010
-11101011
-11010111
-11111101
-11101001
-10101110
-01001001
-00001010
-00000001
-11000011
-00001110
-10001101
-00001001
-01101011
-00001000
-00001101
-00001100
-10001000
-00000110
-11100001
-00001001
-11111111
-00001000
-01001010
-00001010
-10011100
-00001001
-01101110
-00001001
-01110011
-00001010
-10110110
-00000100
-01010101
-10101110
-10110010
-00001001
-00000010
-11000011
-00001110
-10001000
-00000110
-10001101
-00001001
-11100001
-00001001
-01110110
-00010010
-11101000
-11111111
-00100011
-11010011
-11001111
-00001001
-00000010
-11000011
-00001110
-11110111
-00001001
-00010010
-00001001
-00010010
-00001001
-00110110
-00001110
-00011010
-00001100
-10001101
-00010010
-11110011
-11111111
-10110110
-00000100
-10100011
-11100000
-00001001
-00000001
-11000011
-00001110
-10001010
-00000100
-10010110
-00001000
-11000100
-00001100
-11111111
-00001000
-00000111
-00001010
-01011100
-00001010
-10110110
-00000100
-00001001
-00001010
-11011111
-01111011
-11000110
-00110000
-11111110
-00111010
-00111000
-00000010
-11000110
-00000111
-01011111
-11010111
-11111101
-11101001
-01000011
-01001100
-11010011
-11110110
-00001001
-00000011
-00011111
-00001010
-11001101
-00100100
-00001010
-11111101
-11101001
-00010001
-11111111
-00100110
-00101010
-00100100
-00111100
-00000001
-00100000
-00000000
-00001001
-00101011
-11101101
-10111000
-11101101
-01000011
-00101111
-00111100
-00100001
-00000000
-00100100
-00100010
-00011100
-00111100
-00010011
-11101011
-00100010
-00100100
-00111100
-11000011
-11111010
-00000111
-01010011
-01001001
-01000111
-11001110
-10011011
-00001001
-00000100
-01001100
-00001010
-11011111
-11001011
-00010010
-00011110
-00101101
-00111000
-00001100
-11111101
-11101001
-01001000
-01001111
-01001100
-11000100
-00011100
-00001010
-00000100
-01011110
-00001010
-11011111
-00101010
-00011010
-00111100
-00101101
-00101000
-00000100
-00100010
-00011010
-00111100
-01110011
-11111101
-11101001
-01010011
-01010000
-01000001
-01000011
-11000101
-01011011
-00001010
-00000101
-01110101
-00001010
-00111110
-00100000
-11001111
-11111101
-11101001
-01010011
-01010000
-01000001
-01000011
-01000101
-11010011
-01110010
-00001010
-00000110
-10000101
-00001010
-11011111
-00011011
-11001011
-01111010
-00100000
-11101101
-00111110
-00100000
-11001111
-00011000
-11110110
-01000011
-11010010
-10000010
-00001010
-00000010
-10010111
-00001010
-00111110
-00001101
-11001111
-11111101
-11101001
-01000101
-01001101
-01001001
-11010100
-10010100
-00001010
-00000100
-10100101
-00001010
-11011111
-01111011
-11001111
-11111101
-11101001
-01000110
-10101110
-10100010
-00001010
-00000010
-10110001
-00001010
-00101010
-00111011
-00111100
-00101011
-11001011
-01111110
-11001011
-10111110
-00101000
-00000011
-00111110
-00101101
-11001111
-00011110
-00000000
-01111110
-00111101
-11111110
-01001001
-00110000
-00000100
-11111110
-00111100
-00110000
-00000100
-00110110
-01000001
-00111100
-01011111
-00111110
-01000000
-10010110
-00111000
-00001001
-01000111
-00000100
-00111110
-00101110
-11001111
-00111110
-00110000
-00010000
-11111011
-00111110
-01000000
-10111110
-10011111
-00101011
-10110110
-00101011
-10110110
-00101011
-10110110
-00100011
-00100011
-00101000
-00010010
-10101111
-11001101
-00110010
-00000111
-11000110
-00110000
-11001111
-00100011
-01111110
-11111110
-01000000
-00100000
-11100101
-00111110
-00101110
-11001111
-00011000
-11100000
-01111011
-10100111
-00100000
-00000101
-00111110
-00100000
-11001111
-00011000
-00001011
-11010110
-01000001
-01101111
-10011111
-01100111
-00111110
-01000101
-11001111
-11001101
-00001110
-00011000
-11011111
-11011111
-11111101
-11101001
-01000001
-11010100
-10101110
-00001010
-00000010
-00011011
-00001011
-11011111
-11001101
-01001110
-00001000
-01111001
-11001101
-00101000
-00001011
-00100010
-00011100
-00111100
-11111101
-11101001
-11000110
-00100000
-01101111
-00100110
-00000001
-00101001
-00101001
-00101001
-00101001
-00101001
-00010110
-00000000
-01111011
-11100110
-00011111
-01011111
-00011001
-11101101
-01011011
-00100100
-00111100
-11101101
-01010010
-00011001
-11011000
-11100111
-00001001
-01010000
-01001100
-01001111
-11010100
-00011000
-00001011
-00000100
-01001100
-00001011
-11001101
-01001110
-00001000
-11011111
-11011101
-01110011
-00110000
-11001011
-00111011
-11001011
-00010001
-00111110
-00010110
-10010011
-11011111
-11011101
-01110011
-00101111
-11001011
-00111011
-11001011
-00010001
-11001101
-00101000
-00001011
-01111110
-11100110
-01111000
-11111110
-00010000
-01111110
-00101000
-00000010
-00111110
-00010000
-01011111
-00010110
-10000111
-01111001
-11100110
-00000011
-01000111
-00101000
-00000111
-00101111
-11000110
-00000010
-11001110
-00000011
-01010111
-01000011
-01111001
-00001111
-00001111
-00001111
-10011111
-11001011
-01011001
-00100000
-00000100
-10101011
-00000111
-10011111
-10101000
-10100010
-10101011
-01110111
-11111101
-11101001
-01000010
-01000101
-01000101
-11010000
-01001001
-00001011
-00000100
-11000011
-00001110
-00010010
-00001001
-01001011
-00010000
-01111101
-10000101
-00001000
-01111010
-00001101
-00001110
-00011010
-11011111
-11001101
-01001110
-00001000
-00100001
-11111001
-00000000
-00001001
-00101100
-11110011
-00111110
-01111111
-11011011
-11111110
-00001111
-00110000
-00010001
-11001101
-11001001
-00001011
-00011011
-01111010
-11010011
-11111110
-11001101
-11001001
-00001011
-10110011
-11000010
-10101111
-00001011
-11111011
-11111101
-11101001
-11100111
-00000011
-01000101
-01001100
-00010000
-11111110
-00000101
-00001101
-11000010
-11001011
-00001011
-11001001
-01001001
-01001110
-01001011
-01000101
-11011001
-10010111
-00001011
-00000101
-11011101
-00001011
-11001101
-00110110
-00000011
-01011111
-00010110
-00000000
-11010111
-11111101
-11101001
-01001001
-11001110
-11011010
-00001011
-00000010
-11101101
-00001011
-11001101
-01001110
-00001000
-00010110
-00000000
-11101101
-01011000
-11010111
-11111101
-11101001
-01001111
-01010101
-11010100
-11101010
-00001011
-00000011
-11111111
-00001011
-11001101
-01001110
-00001000
-11011111
-11101101
-01011001
-11111101
-11101001
-01000001
-01000010
-11010011
-11111100
-00001011
-00000011
-11000011
-00001110
-01101011
-00001000
-10010100
-00001101
-10110110
-00000100
-00110000
-10111101
-00001100
-00001100
-00000010
-00011100
-00001100
-11011111
-01111010
-10110011
-11111110
-00000001
-00111110
-00000000
-01010111
-00010111
-01011111
-11010111
-11111101
-11101001
-00110000
-10111100
-00011001
-00001100
-00000010
-00110000
-00001100
-11011111
-11001011
-00010010
-00011000
-11101100
-00110000
-10111110
-00101101
-00001100
-00000010
-00111100
-00001100
-11011111
-01111010
-10110011
-00101000
-11100000
-11001011
-00010010
-00111111
-00011000
-11011011
-10111101
-00111001
-00001100
-00000001
-11000011
-00001110
-11100001
-00001101
-00011010
-00001100
-10110110
-00000100
-10111110
-01001001
-00001100
-00000001
-01011000
-00001100
-11011111
-11010101
-11011111
-11100001
-11001101
-10011001
-00001100
-00011000
-11000000
-10111100
-01010101
-00001100
-00000001
-11000011
-00001110
-10000101
-00001000
-01010110
-00001100
-10110110
-00000100
-01010101
-10111100
-01100100
-00001100
-00000010
-01110100
-00001100
-11001101
-01001110
-00001000
-11011111
-11101011
-10100111
-11101101
-01000010
-00011000
-10100011
-01000100
-10111100
-01110001
-00001100
-00000010
-10000101
-00001100
-11011111
-11010101
-11001101
-01001110
-00001000
-11011111
-11100001
-10100111
-11101101
-01010010
-00101000
-11100110
-00011001
-11101011
-11001101
-10011001
-00001100
-11011111
-00011000
-10001000
-01111100
-10101010
-11111010
-10100000
-00001100
-11101101
-01010010
-11001011
-00010100
-11001001
-01010101
-10101010
-10000010
-00001100
-00000010
-10101010
-00001100
-11011111
-11001101
-01001110
-00001000
-00100001
-00000000
-00000000
-00111110
-00010000
-00101001
-11101011
-11101101
-01101010
-11101011
-00110000
-00000100
-00001001
-00110000
-00000001
-00010011
-00111101
-00100000
-11110010
-11101011
-00011000
-00101111
-11000110
-00001100
-11011111
-11011001
-11011111
-11010101
-11011111
-11100001
-01111100
-10110101
-00111110
-00100001
-00100000
-00000011
-11101011
-00111110
-00010001
-11011001
-01000111
-10101111
-01100111
-01101111
-01001111
-11101101
-01101010
-10011111
-10100111
-11101101
-01010010
-10011001
-00110000
-00000001
-00011001
-00111111
-11011001
-11101011
-11101101
-01101010
-11101011
-11101101
-01101010
-11011001
-00010000
-11101011
-11101011
-11010111
-11011001
-11100101
-11010111
-11010001
-11010111
-11111101
-11101001
-00101111
-01001101
-01001111
-11000100
-10100111
-00001100
-00000100
-11000011
-00001110
-10000101
-00001000
-11010010
-00001000
-11101001
-00010010
-00001101
-00001100
-01001011
-00010000
-00000000
-11111111
-00001000
-01101011
-00001000
-11101001
-00010010
-01100000
-00001110
-11010010
-00001000
-00001101
-00001100
-10001100
-00001101
-11011111
-00001000
-10010100
-00001101
-10000101
-00001000
-11011111
-00001000
-10010100
-00001101
-10000101
-00001000
-10110110
-00000100
-00101010
-00101111
-01001101
-01001111
-11000100
-11111111
-00001100
-00000101
-11000011
-00001110
-11111111
-00001000
-11010010
-00001000
-11101001
-00010010
-00001101
-00001100
-11111111
-00001000
-01101011
-00001000
-11011111
-00001000
-01100000
-00001110
-11010010
-00001000
-00001101
-00001100
-10101000
-00001100
-01110110
-00010010
-11000001
-11111111
-10101111
-00110000
-00001101
-00000001
-11000011
-00001110
-00000000
-00001101
-10000101
-00001000
-01111001
-00001000
-10110110
-00000100
-01001101
-01001111
-11000100
-01010000
-00001101
-00000011
-11000011
-00001110
-00000000
-00001101
-01111001
-00001000
-10110110
-00000100
-10101010
-01100000
-00001101
-00000001
-11000011
-00001110
-10101000
-00001100
-01111001
-00001000
-10110110
-00000100
-00101010
-10101111
-01101100
-00001101
-00000010
-11000011
-00001110
-00110001
-00001101
-10000101
-00001000
-01111001
-00001000
-10110110
-00000100
-01010101
-00101111
-01001101
-01001111
-11000100
-01111001
-00001101
-00000101
-11000011
-00001110
-11000100
-00001100
-01111001
-00001000
-10110110
-00000100
-11000011
-00001110
-00101110
-00001100
-10000011
-00010010
-00000011
-00000000
-10101001
-00001101
-10110110
-00000100
-01001110
-01000101
-01000111
-01000001
-01010100
-11000101
-10001011
-00001101
-00000110
-10101011
-00001101
-00000001
-00000010
-00000000
-00011000
-00001111
-01000100
-01001110
-01000101
-01000111
-01000001
-01010100
-11000101
-10101000
-00001101
-00000111
-10111100
-00001101
-00000001
-00000100
-00000000
-00101010
-00111011
-00111100
-10100111
-11101101
-01000010
-01111000
-10011110
-01110111
-00100011
-00001101
-00100000
-11111001
-11111101
-11101001
-10101011
-10111001
-00001101
-00000001
-11010100
-00001101
-11011111
-11010101
-11011111
-11100001
-00011001
-11101011
-11010111
-11111101
-11101001
-10101101
-11010001
-00001101
-00000001
-11000011
-00001110
-10101001
-00001101
-11010010
-00001101
-10110110
-00000100
-01000100
-10101011
-11100000
-00001101
-00000010
-11110000
-00001101
-11011111
-11010101
-11001101
-01001110
-00001000
-11011111
-11010101
-11011111
-11101011
-00001001
-11101011
-11010111
-11000001
-11100001
-11101101
-01001010
-11101011
-11010111
-11111101
-11101001
-00110001
-10101011
-11101101
-00001101
-00000010
-00001011
-00001110
-11011111
-00011000
-00001001
-00110010
-10101011
-00001000
-00001110
-00000010
-00010101
-00001110
-11011111
-00010011
-00010011
-00011000
-00010100
-00110001
-10101101
-00010010
-00001110
-00000010
-00100001
-00001110
-11011111
-00011000
-00001001
-00110010
-10101101
-00011110
-00001110
-00000010
-00101011
-00001110
-11011111
-00011011
-00011011
-11010111
-11111101
-11101001
-01001111
-11010010
-00101000
-00001110
-00000010
-00111000
-00001110
-11011111
-11001101
-01001110
-00001000
-01111011
-10110001
-01011111
-01111010
-10110000
-01010111
-11010111
-11111101
-11101001
-01000001
-01001110
-11000100
-00110101
-00001110
-00000011
-01001101
-00001110
-11011111
-11001101
-01001110
-00001000
-01111011
-10100001
-01011111
-01111010
-10100000
-01010111
-11010111
-11111101
-11101001
-01011000
-01001111
-11010010
-01001010
-00001110
-00000011
-01100010
-00001110
-11011111
-11001101
-01001110
-00001000
-01111011
-10101001
-01011111
-01111010
-10101000
-01010111
-11010111
-11111101
-11101001
-01001101
-01000001
-11011000
-01011111
-00001110
-00000011
-11000011
-00001110
-00010010
-00001001
-00010010
-00001001
-01100101
-00001100
-01110001
-00010010
-00001111
-00000000
-01001101
-01001001
-11001110
-01110100
-00001110
-00000011
-11000011
-00001110
-00010010
-00001001
-00010010
-00001001
-01010110
-00001100
-10000011
-00010010
-00000011
-00000000
-10000101
-00001000
-01111001
-00001000
-10110110
-00000100
-01000100
-01000101
-01000011
-01001001
-01001101
-01000001
-11001100
-10000110
-00001110
-00000111
-10100101
-00001110
-11011101
-00110110
-00111111
-00001010
-11111101
-11101001
-10111010
-10100010
-00001110
-00000001
-10000101
-00010000
-11000011
-00001110
-01001011
-00010000
-00001010
-00001110
-00011010
-00100001
-00111110
-00111100
-01111110
-11110110
-01000100
-01110111
-11111101
-11101001
-11101001
-11111111
-11101011
-11000011
-10111010
-00000100
-01000011
-01010010
-01000101
-01000001
-01010100
-11000101
-10101110
-00001110
-00000110
-11000011
-00001110
-01001011
-00010000
-00100000
-10101011
-00000101
-11111011
-00001110
-10001000
-00000110
-01001110
-00001111
-10000000
-00000100
-10110011
-00001000
-01101011
-00001000
-10110011
-00001000
-01001110
-00001111
-01100000
-00000100
-10000101
-00001000
-11000001
-00001000
-10011001
-00000100
-10010110
-00001000
-01011111
-00001111
-00010001
-00010000
-11101100
-00001111
-01001110
-00001111
-10110110
-00000100
-11111101
-00001110
-11001101
-00101110
-00001111
-11011111
-00011010
-00111101
-11111110
-00111111
-00111000
-00000010
-11100111
-00000110
-11000110
-00001000
-01001111
-00000110
-00000000
-11001101
-10001100
-00001111
-00011010
-01001111
-00101010
-00110111
-00111100
-11010101
-11001101
-10011110
-00001111
-11010001
-00011010
-01000111
-00010011
-00011010
-11001101
-00000111
-00001000
-01110111
-00100011
-00010000
-11110111
-00100010
-00111001
-00111100
-00101011
-11001011
-11111110
-11111101
-11101001
-11011101
-11001011
-00111110
-01010110
-00101000
-00000010
-11100111
-00001100
-00101010
-00110111
-00111100
-11101101
-01011011
-00111001
-00111100
-10101111
-11101101
-01010010
-11101011
-01110011
-00100011
-01110010
-01100111
-01101111
-00100010
-00111001
-00111100
-11001001
-10101100
-11001111
-00001110
-00000001
-11000011
-00001110
-10000011
-00001111
-01100000
-00000100
-00101001
-00001110
-11000001
-00001000
-10110110
-00000100
-01000011
-10101100
-01001101
-00001111
-00000010
-11000011
-00001110
-01001011
-00010000
-00000001
-01110110
-00001111
-01100000
-00000100
-00011111
-00001110
-10100101
-00001000
-10110110
-00000100
-01000001
-01001100
-01001100
-01001111
-11010100
-01011110
-00001111
-00000101
-01111000
-00001111
-11001101
-01001110
-00001000
-00101010
-00110111
-00111100
-11001101
-10011110
-00001111
-11111101
-11101001
-11000011
-00001110
-01001011
-00010000
-00000010
-01110110
-00001111
-10110110
-00000100
-00100001
-00011110
-00000000
-11000101
-00001001
-11101101
-01001011
-00111011
-00111100
-00001001
-11000001
-00111000
-00000011
-11101101
-01110010
-11011000
-11100111
-00000001
-11101011
-00100001
-00101000
-00000000
-11001101
-10001111
-00001111
-00101010
-00110111
-00111100
-00001001
-00100010
-00110111
-00111100
-00101010
-00111011
-00111100
-11100101
-00001001
-00100010
-00111011
-00111100
-11100011
-11100101
-10100111
-11101101
-01010010
-01000100
-01001101
-11100001
-11010001
-11001000
-00101011
-00011011
-11101101
-10111000
-00100011
-11001001
-01010110
-01000001
-01010010
-01001001
-01000001
-01000010
-01001100
-11000101
-01110101
-00001111
-00001000
-10000101
-00010000
-11110000
-00001111
-01001110
-00001111
-10110110
-00000100
-01000011
-01001111
-01001110
-01010011
-01010100
-01000001
-01001110
-11010100
-11001110
-00001111
-00001000
-10000101
-00010000
-11110101
-00001111
-01001110
-00001111
-10110110
-00000100
-11011100
-11111110
-00011000
-00000010
-11010101
-11111111
-11010111
-11111101
-11101001
-11100011
-11111111
-11101011
-01011110
-00100011
-01010110
-11010111
-11111101
-11101001
-01001100
-01001001
-01010100
-01000101
-01010010
-01000001
-11001100
-11100001
-00001111
-01000111
-00001000
-00010001
-00010001
-00010000
-01001110
-00001111
-10110110
-00000100
-00000010
-11111111
-11111111
-00010011
-00010000
-00000110
-00000001
-11100001
-01011110
-00100011
-01010110
-00100011
-11100101
-11010111
-00010000
-11110111
-11111101
-11101001
-01000001
-01010011
-01000011
-01001001
-11001001
-00000101
-00010000
-01000101
-11000011
-00001110
-01001011
-00010000
-00100000
-10101011
-00000101
-00001001
-00001110
-10010110
-00001000
-00001110
-00011010
-11011101
-11001011
-00111110
-01110110
-00101000
-11100011
-11001101
-10111001
-00000100
-00010001
-00010000
-01001011
-00010000
-01001110
-00001111
-01011111
-00001111
-10110110
-00000100
-00000001
-11010110
-11111111
-01001101
-00010000
-11100001
-01011110
-00010110
-00000000
-00000110
-00000001
-00011000
-11000100
-00001000
-00010001
-01100100
-00010000
-10000101
-00001000
-01001110
-00001111
-01001110
-00001111
-10110110
-00000100
-00000100
-11111111
-11111111
-01100110
-00010000
-00000110
-00000010
-00011000
-10101011
-01000100
-01000101
-01000110
-01001001
-01001110
-01000101
-11010010
-00100111
-00010000
-00000111
-10000101
-00010000
-10000101
-00010000
-01100000
-00000100
-01001011
-00010000
-00001100
-10000011
-00001111
-01110110
-00010010
-00110100
-11111110
-11100110
-11111111
-11001101
-11110000
-00001111
-11010000
-00001110
-01101011
-00001000
-10110011
-00001000
-01100000
-00000100
-00101001
-00001110
-11000001
-00001000
-00010011
-00001110
-10011010
-00010000
-10110110
-00000100
-10011100
-00010000
-11011111
-11000011
-11000011
-00001110
-01000011
-01000001
-01001100
-11001100
-01110011
-00010000
-00000100
-10101001
-00010000
-11011111
-11101011
-11101001
-01000100
-01001111
-01000101
-01010011
-10111110
-11110100
-00010000
-01000101
-00001000
-00010001
-11101000
-00010000
-11011000
-00010010
-00001100
-11001101
-00010000
-01001011
-00010000
-11001101
-01011111
-00001111
-00010001
-00010000
-11110000
-00001111
-01001110
-00001111
-01001011
-00010000
-00001010
-10110110
-00000100
-11000011
-00001110
-01101011
-00001000
-00101001
-00001110
-10110101
-00010101
-01100000
-00000100
-11100001
-00001101
-00011111
-00001110
-01001110
-00001111
-01100000
-00000100
-10000101
-00001000
-11000001
-00001000
-10110110
-00000100
-00000101
-11000101
-11111111
-10111000
-00000100
-01000011
-01001111
-01001101
-01010000
-01001001
-01001100
-01000101
-11010010
-10100110
-00010000
-00001000
-10000101
-00010000
-00001000
-00010001
-01100000
-00010001
-01100000
-00000100
-01001011
-00010000
-00001011
-10000011
-00001111
-01110110
-00010010
-10110001
-11111101
-11100011
-11111111
-11011101
-11001011
-00111110
-01110110
-00100000
-00000010
-11100111
-00000100
-11001101
-11110000
-00001111
-01101011
-00001000
-10110011
-00001000
-01001110
-00001111
-01110110
-00010010
-01111000
-11111111
-01010010
-01010101
-01001110
-01010011
-10111110
-10110011
-00010000
-01000101
-00001000
-00010001
-01000000
-00010001
-11011000
-00010010
-00001011
-10000101
-00001000
-01011111
-00001111
-11001101
-00010000
-00010001
-00010000
-01000010
-00010001
-01001110
-00001111
-01001011
-00010000
-00001010
-10110110
-00000100
-00000101
-11011110
-11111111
-10111000
-00000100
-11100001
-11010101
-11101011
-11010111
-01000010
-01001011
-11010001
-11010101
-00011011
-00011011
-11001101
-10011110
-00010101
-11010001
-11000101
-11000011
-11000011
-00001110
-01001001
-01001101
-01001101
-01000101
-01000100
-01001001
-01000001
-01010100
-11000101
-00100100
-00010001
-00001001
-11000011
-00001110
-10000000
-00000100
-10110011
-00001000
-10110011
-00001000
-00001110
-00011010
-11011111
-11101011
-11001011
-11110110
-11111101
-11101001
-01010110
-01001111
-01000011
-01000001
-01000010
-01010101
-01001100
-01000001
-01010010
-11011001
-01011111
-00010001
-00001010
-10000101
-00010000
-10110101
-00010001
-10000000
-00000100
-10110011
-00001000
-00010011
-00001110
-01001110
-00001111
-10001000
-00000110
-01011111
-00001111
-01100000
-00000100
-00010001
-00010000
-00110101
-00111100
-01101011
-00001000
-10110011
-00001000
-01001110
-00001111
-11000001
-00001000
-10110110
-00000100
-01000100
-01000101
-01000110
-01001001
-01001110
-01001001
-01010100
-01001001
-01001111
-01001110
-11010011
-01111100
-00010001
-00001011
-10101101
-00010001
-00101010
-00110011
-00111100
-00100010
-00110001
-00111100
-11111101
-11101001
-11101101
-01010011
-00110011
-00111100
-11111101
-11101001
-01001001
-11000110
-11100000
-00010011
-01000010
-00001000
-00010001
-10000011
-00010010
-01100000
-00000100
-01001011
-00010000
-00000010
-10000011
-00001111
-10110110
-00000100
-01010111
-01001000
-01001001
-01001100
-11000101
-10111111
-00010001
-01000101
-00001000
-00010001
-10001000
-00010010
-11011000
-00010010
-00000001
-01100000
-00000100
-01001011
-00010000
-00000100
-10000011
-00001111
-10110110
-00000100
-01000101
-01001100
-01010011
-11000101
-11010100
-00010001
-01000100
-00001000
-00010001
-01110001
-00010010
-11011000
-00010010
-00000010
-10000011
-00001111
-00100101
-00010010
-01100000
-00000100
-00101001
-00001110
-01001011
-00010000
-00000010
-10110110
-00000100
-01010100
-01001000
-01000101
-11001110
-11101011
-00010001
-01000100
-00001000
-00010001
-10100100
-00010010
-11011000
-00010010
-00000010
-00100101
-00010010
-10110110
-00000100
-01000010
-01000101
-01000111
-01001001
-11001110
-00000110
-00010010
-01000101
-00001000
-00010001
-10011111
-00010010
-01100000
-00000100
-01001011
-00010000
-00000001
-10110110
-00000100
-11000011
-00001110
-01101011
-00001000
-01100000
-00000100
-10000101
-00001000
-11100001
-00001101
-00011111
-00001110
-10000101
-00001000
-11000001
-00001000
-10110110
-00000100
-11000011
-00001110
-01100000
-00000100
-11100001
-00001101
-00011111
-00001110
-01001110
-00001111
-10110110
-00000100
-01010010
-01000101
-01010000
-01000101
-01000001
-11010100
-00011001
-00010010
-01000110
-00001000
-00010001
-01110110
-00010010
-11011000
-00010010
-00000100
-10000101
-00001000
-00110111
-00010010
-00100101
-00010010
-10110110
-00000100
-01010101
-01001110
-01010100
-01001001
-11001100
-01001011
-00010010
-01000101
-00001000
-00010001
-10001101
-00010010
-11011000
-00010010
-00000001
-00110111
-00010010
-10110110
-00000100
-00000010
-01110101
-11111111
-01111000
-00010010
-00000010
-11001110
-11111111
-01111000
-00010010
-11100001
-01011110
-00100011
-01010110
-00011001
-11000011
-10111010
-00000100
-00000010
-00111001
-11111111
-10001111
-00010010
-00000010
-01000110
-11111111
-10001111
-00010010
-00000010
-11001111
-11111111
-10001111
-00010010
-11001101
-01001110
-00001000
-01111000
-10110001
-00101000
-11100010
-11100001
-00100011
-00100011
-11000011
-10111010
-00000100
-00000000
-01110100
-11111111
-10111001
-00000100
-00000000
-01011101
-11111111
-10111001
-00000100
-01000100
-11001111
-01100010
-00010010
-01000010
-00001000
-00010001
-00100011
-00010011
-01100000
-00000100
-01001011
-00010000
-00000011
-10110110
-00000100
-01001100
-01001111
-01001111
-11010000
-10101010
-00010010
-01000100
-00001000
-00010001
-00110010
-00010011
-11011000
-00010010
-00000011
-00110111
-00010010
-10110110
-00000100
-00101011
-01001100
-01001111
-01001111
-11010000
-10111100
-00010010
-01000101
-00001000
-00010001
-00111100
-00010011
-01110110
-00010010
-11101010
-11111111
-11011010
-00010010
-11011111
-11100001
-01111110
-00100011
-11100101
-10010011
-10110010
-00101000
-01001010
-11100111
-00000101
-11001001
-10101010
-00010001
-00000001
-11101011
-00010010
-11000001
-11010001
-11010101
-11000101
-11010111
-11111101
-11101001
-01001001
-10100111
-11101000
-00010010
-00000010
-11111001
-00010010
-00100001
-00000100
-00000000
-00011000
-00001001
-11001010
-11110110
-00010010
-00000001
-00000100
-00010011
-00100001
-00000110
-00000000
-00111001
-01011110
-00100011
-01010110
-11010111
-11111101
-11101001
-01001100
-01000101
-01000001
-01010110
-11000101
-00000001
-00010011
-00000101
-00011000
-00010011
-11000001
-11100001
-11100001
-11100101
-11100101
-11000101
-11111101
-11101001
-00000000
-10000100
-11111111
-00100101
-00010011
-11001101
-01001110
-00001000
-11011111
-11100001
-11010101
-11000101
-11100101
-11111101
-11101001
-00000010
-10000101
-11111111
-00110100
-00010011
-00010001
-00000001
-00000000
-00011000
-00000110
-00000010
-10001101
-11111111
-00111110
-00010011
-11011111
-11000001
-11100001
-10100111
-11101101
-01011010
-01111010
-11010001
-00110111
-11101010
-01011000
-00010011
-11010101
-11100101
-00000111
-00110000
-00000001
-11101011
-11001101
-10011001
-00001100
-00111111
-00110000
-00000010
-11100001
-11100001
-11000101
-10011111
-11000011
-10010100
-00010010
-10101000
-11010100
-00010011
-01000001
-00001000
-00010001
-01111001
-00010011
-01001011
-00010000
-00101001
-01100000
-00000100
-10000101
-00001000
-10000011
-00001111
-10011111
-00010011
-10000101
-00001000
-11000001
-00001000
-10110110
-00000100
-11111111
-11100101
-11111111
-01111011
-00010011
-11100001
-01011110
-00100011
-01010110
-00010011
-11000011
-01111100
-00010010
-00101110
-10100010
-01100000
-00010011
-01000010
-00001000
-00010001
-10010110
-00010011
-01001011
-00010000
-00100010
-01110110
-00010010
-11010110
-11111111
-11111111
-11101110
-11111111
-10011000
-00010011
-11010001
-11001101
-01111001
-00001001
-11010101
-11111101
-11101001
-10100001
-00010011
-11011111
-11010101
-11001101
-11100001
-00000101
-01100010
-01101011
-00001001
-01111110
-11100001
-10111101
-00101000
-00001010
-11101011
-11010111
-00010001
-01111000
-00000101
-11001101
-00010101
-00011000
-00011000
-11101001
-11010101
-11000101
-00101010
-00110111
-00111100
-11001101
-10011110
-00001111
-11000001
-11010001
-11010101
-11000101
-11101011
-11101101
-10110000
-11000001
-01010000
-01011001
-11010111
-11010001
-11001101
-11011010
-00000111
-11111101
-11101001
-11011011
-11001111
-00010010
-01000001
-11010111
-00010011
-11011101
-11001011
-00111110
-10110110
-11111101
-11101001
-11011101
-00010101
-00010011
-00000001
-11100011
-00010011
-11011101
-11001011
-00111110
-11110110
-11111101
-11101001
-01000101
-01011000
-01001001
-11010100
-10000111
-00010011
-00000100
-10111000
-00000100
-01010010
-01000101
-01000100
-01000101
-01000110
-01001001
-01001110
-11000101
-11101111
-00010011
-00001000
-11111111
-00010011
-11001101
-00101110
-00001111
-00101010
-00110001
-00111100
-01011110
-00100011
-01010110
-11101011
-00100011
-00100010
-00000101
-00100111
-11100101
-11001101
-11000000
-00010101
-00100010
-00001101
-00100111
-11101101
-01000011
-00000111
-00100111
-11101101
-01010011
-00001011
-00100111
-00101010
-00110111
-00111100
-11101101
-01010010
-11000010
-11011010
-00010100
-11010001
-11010111
-11001101
-10111001
-00000100
-00010000
-00010110
-00111101
-00000110
-00001110
-00011010
-11011111
-00100001
-10101111
-11000011
-00011001
-11010010
-11001111
-00010100
-11101011
-00100010
-00000011
-00100111
-11001101
-11000000
-00010101
-00100010
-00000001
-00100111
-11100101
-11101101
-01010011
-00001001
-00100111
-01111000
-10110001
-11101101
-01011011
-00000111
-00100111
-00101000
-00000100
-01111010
-10110011
-00101000
-01111101
-11100001
-11101101
-01001011
-00001101
-00100111
-11101101
-01000010
-11101011
-00011001
-00100010
-00000111
-00100111
-00101010
-00001011
-00100111
-00011001
-11101101
-01001011
-00001001
-00100111
-10100111
-11101101
-01000010
-00100010
-00001011
-00100111
-00000001
-00101110
-00000000
-00001001
-11001011
-01111100
-00100000
-00001011
-11101101
-01001011
-00111011
-00111100
-00001001
-00111000
-01010100
-11101101
-01110010
-00110000
-01010000
-00101010
-00000011
-00100111
-11100101
-00101011
-00101011
-01000110
-00101011
-01001110
-00101010
-00000101
-00100111
-11100101
-00101011
-00101011
-01110000
-00101011
-01110001
-11100001
-00011001
-11000001
-10100111
-11101101
-01000010
-00100010
-00000101
-00100111
-11101101
-01011011
-00000001
-00100111
-00101010
-00001001
-00100111
-10100111
-11101101
-01010010
-01000100
-01001101
-11010101
-11000101
-11001101
-11011100
-00010100
-00101010
-00001011
-00100111
-11000001
-00001001
-01000100
-01001101
-11100001
-11000101
-11001101
-10011110
-00001111
-11101011
-00101010
-00001101
-00100111
-11101101
-01001011
-00001011
-00100111
-00001001
-11000001
-11000101
-11100101
-11101101
-10110000
-11010001
-11000001
-11001101
-11011100
-00010100
-11001101
-11111000
-00010100
-11111101
-11101001
-00101010
-00110001
-00111100
-11101101
-01011011
-00000101
-00100111
-00011011
-01110011
-00100011
-01110010
-11100111
-00001011
-00101010
-00110111
-00111100
-10100111
-11101101
-01000010
-00100010
-00110111
-00111100
-00101010
-00111011
-00111100
-11101101
-01000010
-00100010
-00111011
-00111100
-11101101
-01010010
-11001000
-11000101
-01000100
-01001101
-11100001
-00011001
-11101101
-10110000
-11001001
-00000001
-00110001
-00111100
-11001101
-01010111
-00010101
-11001101
-01010111
-00010101
-00000001
-01000000
-00111100
-00101010
-00110111
-00111100
-00110111
-11101101
-01000010
-11011000
-00001010
-00010111
-00000011
-00110000
-11111011
-00000011
-00000011
-11001101
-01010111
-00010101
-00000011
-11001101
-01010111
-00010101
-11001101
-11111011
-00010101
-11000011
-00001110
-00011100
-10000101
-00010000
-00010110
-00001000
-00010001
-00010011
-10110101
-00010001
-00011000
-00000000
-00000000
-00100001
-11111001
-11111111
-00001001
-01001110
-00100011
-01000110
-00101011
-00001001
-01000100
-01001101
-00011000
-11001101
-11001101
-01010111
-00010101
-11001101
-01001000
-00010101
-00011000
-11000101
-11001101
-01010111
-00010101
-00000011
-11001101
-01010111
-00010101
-00011000
-10111100
-11001101
-01010111
-00010101
-00100001
-10110110
-00000100
-10100111
-11101101
-01010010
-11001000
-11001101
-10011110
-00010101
-00011000
-11110001
-00001010
-01011111
-00000011
-00001010
-01010111
-00001011
-11001101
-01101000
-00010101
-11101011
-01111011
-00000010
-00000011
-01111010
-00000010
-00000011
-11001001
-00101010
-00000001
-00100111
-10100111
-11101101
-01010010
-01100010
-01101011
-11010000
-00101010
-00001001
-00100111
-11101101
-01010010
-00110000
-00001100
-00101010
-00001101
-00100111
-11101101
-01010010
-00111000
-00010011
-00101010
-00001011
-00100111
-00011001
-11001001
-00101010
-00000011
-00100111
-11101101
-01010010
-00101010
-00000111
-00100111
-11011000
-00101010
-00000101
-00100111
-00011001
-11001001
-00101010
-00000001
-00100111
-00011001
-11101101
-01011011
-00001101
-00100111
-10100111
-11101101
-01010010
-11001001
-00011011
-00011010
-00010111
-11010000
-00011011
-00011011
-00011010
-01101111
-00100110
-00000000
-00111100
-00100000
-00000110
-00001010
-01101111
-00000011
-00001010
-01100111
-00000011
-00001001
-01000100
-01001101
-11001001
-10110111
-00010101
-11011111
-11101011
-11001101
-11100111
-00010101
-11101011
-11010111
-11111101
-11101001
-11100101
-01011110
-00100011
-01010110
-11001101
-11111011
-00010101
-00001000
-00010001
-00001011
-10000101
-00010000
-00001000
-00000000
-00000000
-00000001
-00000000
-00000000
-00011000
-00000111
-11100001
-11100101
-00100011
-00100011
-01001110
-00100011
-01000110
-11100001
-11100101
-00101011
-00101011
-00101011
-00101011
-01010110
-00101011
-01011110
-00011001
-11101011
-11100001
-00101011
-01111100
-11111110
-00111100
-01111110
-11001011
-10110111
-00111000
-00000010
-11000110
-00000010
-00101011
-00101011
-00101011
-00111101
-00100000
-11111100
-11001001
-00100011
-11100101
-11100001
-01111110
-00100011
-11100101
-01100110
-01101111
-10110100
-11001000
-11101101
-01010010
-11100001
-00100011
-00100000
-11110000
-11010101
-00010110
-00000000
-01011110
-00011001
-11010001
-11101001
-11000011
-00001110
-00011111
-00001110
-00101001
-00001110
-10110011
-00001000
-10000000
-00000100
-10110011
-00001000
-11000001
-00001000
-10110110
-00000100
-11001101
-10111001
-00000100
-00111101
-00000110
-00001110
-00011010
-11011111
-00100001
-10101111
-11000011
-00011001
-11011000
-11100111
-00001101
-01000110
-01001111
-01010010
-01000111
-01000101
-11010100
-11111100
-00010011
-00000110
-00111010
-00010110
-00101010
-00110001
-00111100
-11101101
-01011011
-00110011
-00111100
-10100111
-11101101
-01010010
-11000010
-11011010
-00010100
-11001101
-00100000
-00010110
-00100001
-11111011
-11111111
-00011001
-00100010
-00111001
-00111100
-11011101
-11001011
-00111110
-11010110
-11100111
-11111111
-01000101
-01000100
-01001001
-11010100
-00110111
-00010110
-00000100
-01100000
-00010110
-11001101
-00100000
-00010110
-11011101
-11001011
-00111110
-11011110
-00011000
-00001100
-01001100
-01001001
-01010011
-11010100
-01011101
-00010110
-00000100
-01110010
-00010110
-11001101
-00100000
-00010110
-00111110
-00001101
-11001111
-11011101
-11001011
-00111110
-01011110
-11010101
-11000100
-11011000
-00000010
-11000001
-00001010
-01011111
-00000011
-00001010
-01010111
-00001011
-11001101
-11111011
-00010101
-11000011
-00001110
-00001011
-00001000
-00010001
-00001101
-10000101
-00010000
-00011111
-00000000
-00000000
-11100111
-00001110
-00100001
-00000010
-00000000
-00011000
-00011000
-11010101
-00100001
-00000010
-00000000
-00001001
-01111110
-00100011
-01100110
-01101111
-00101011
-00101011
-00101011
-01101110
-01111101
-00000111
-10011111
-01100111
-11001101
-00001110
-00011000
-11010001
-00100001
-00000100
-00000000
-00001001
-11100101
-11000101
-11001101
-11100100
-00010111
-11010001
-11000001
-11001101
-11100100
-00010111
-11011101
-00110110
-00010100
-00000001
-11011101
-00110110
-00010110
-00010000
-11001101
-00001000
-00010111
-00111000
-00000110
-11011101
-00110101
-00010110
-11110010
-11000111
-00010110
-11011101
-11001011
-00111110
-01011110
-00100000
-00010000
-00111000
-00101000
-00100001
-00100110
-00111100
-00110110
-00000000
-01111110
-10100111
-00101000
-11111100
-11001101
-11100100
-00000100
-00011000
-11011011
-11110101
-11011101
-11001011
-00111110
-10011110
-11000101
-11001101
-10111001
-00000100
-01111000
-00000101
-00000110
-00000101
-00001110
-00011010
-11011101
-11001011
-00111110
-11011110
-11001101
-11011000
-00000010
-11000001
-11110001
-00110000
-11000001
-11011101
-11001011
-00111110
-10011110
-11111101
-11101001
-00111010
-00010100
-00111100
-00110010
-00010101
-00111100
-11011101
-00110110
-00010011
-00000101
-00001010
-01011111
-00000011
-00001010
-01010111
-00000011
-11001101
-11111011
-00010101
-10000011
-00010010
-01000000
-01110001
-00010010
-01000100
-10100100
-00010010
-01001000
-10011111
-00010010
-00110111
-10001101
-00010010
-01000010
-10001000
-00010010
-00111000
-01110110
-00010010
-00111100
-00100011
-00010011
-00101011
-00110010
-00010011
-00110110
-00111100
-00010011
-00110011
-11101000
-00010000
-00101001
-01000000
-00010001
-00100110
-00010001
-00010000
-00111011
-01100100
-00010000
-01000111
-01001011
-00010000
-01010001
-01111001
-00010011
-01100010
-10010110
-00010011
-01100011
-10110110
-00000100
-01010100
-00000000
-00000000
-11001101
-11100001
-00010111
-11011101
-00110101
-00010011
-00100000
-10110111
-10100111
-11001001
-00101010
-00010100
-00111100
-01100101
-00101100
-00011000
-00001100
-00101010
-00010100
-00111100
-01100101
-00100101
-00011000
-00000101
-00101010
-00010100
-00111100
-00101101
-01100101
-00100010
-00010100
-00111100
-11011101
-00110110
-00010011
-00000001
-11011101
-00110101
-00010110
-00011000
-11010111
-11001101
-11011010
-00010111
-11010111
-00010001
-10110011
-00001001
-11001101
-11000001
-00010111
-11001101
-00010101
-00011000
-00011000
-11001011
-11001101
-11011010
-00010111
-11010111
-11001101
-11011010
-00010111
-11010111
-00010001
-10101111
-00001010
-00011000
-11101011
-00001010
-11110101
-11001101
-11100001
-00010111
-11110001
-11001111
-00111110
-00100000
-11001111
-00011000
-10110010
-11001101
-00001000
-00011000
-00001101
-00111011
-10001101
-00110111
-11001001
-00111110
-00101001
-00011000
-00000010
-00111110
-00100010
-11110101
-11000101
-11001101
-11100001
-00010111
-11010001
-11001101
-01111001
-00001001
-01000010
-01001011
-11110001
-11001111
-10100111
-11001001
-00111010
-00010101
-00111100
-10100111
-11111000
-11000101
-01000111
-00111110
-00001101
-11001111
-00000100
-00000101
-00101000
-00000101
-00111110
-00100000
-11001111
-00010000
-11111011
-11011101
-00110110
-00010101
-11111111
-11000001
-11001001
-00001010
-01011111
-00000011
-00001010
-01010111
-00000011
-11001001
-11001101
-11000001
-00010111
-11101011
-00101011
-01111110
-11001011
-01111111
-00100000
-00000101
-11001101
-11101000
-00010101
-00011000
-00001011
-11101011
-11001101
-10100010
-00010101
-00010011
-00011010
-01101111
-00010011
-00011010
-01100111
-00011001
-01111110
-11100110
-01111111
-11001111
-11001011
-01111110
-00100011
-00101000
-11110111
-00111110
-00100000
-11001111
-11001001
-11100011
-11001101
-11111011
-00010111
-11100011
-11001001
-00010001
-10110011
-00001001
-11010101
-11101011
-11010111
-11010001
-11000101
-11001101
-10111111
-00000100
-00011011
-00011000
-00011101
-00011000
-11000001
-11000001
-11001001
-11111101
-11100101
-11100101
-11111101
-11100001
-00100001
-10010010
-00011000
-11100101
-00100001
-00000000
-11100000
-11001011
-01111001
-00101000
-00000010
-00100110
-11111100
-00010011
-11111101
-00101011
-11110011
-10101111
-00000110
-10010111
-00010000
-11111110
-11010011
-11111110
-11101110
-00001000
-00101100
-00100000
-00000001
-00100100
-00100000
-11110010
-00000110
-00101011
-00010000
-11111110
-11010011
-11111110
-01101001
-00000001
-00001000
-00111011
-00010000
-11111110
-01111001
-11010011
-11111110
-00000110
-00111000
-11000011
-10001010
-00011000
-01111001
-11001011
-01111000
-00010000
-11111110
-00110000
-00000100
-00000110
-00111101
-00010000
-11111110
-11010011
-11111110
-00000110
-00111010
-11000010
-01011001
-00011000
-00000101
-10101111
-11001011
-00010101
-11000010
-01011100
-00011000
-00011011
-11111101
-00100011
-00000110
-00101110
-00111110
-01111111
-11011011
-11111110
-00011111
-11010000
-01111010
-11111110
-11111111
-11010000
-10110011
-00101000
-00001011
-11111101
-01101110
-00000000
-01111100
-10101101
-01100111
-10101111
-00110111
-11000011
-01101101
-00011000
-01101100
-00011000
-11110101
-11111101
-11100001
-00001000
-00000110
-00111011
-00010000
-11111110
-10101111
-11010011
-11111110
-00111110
-01111111
-11011011
-11111110
-00011111
-11111011
-11010010
-11110000
-00000100
-00001000
-11001001
-11110011
-11111101
-11100101
-11100101
-11111101
-11100001
-00100001
-10010010
-00011000
-11100101
-01100001
-00001000
-10101111
-01001111
-11000000
-00101110
-00000000
-00000110
-10111000
-11001101
-00010001
-00011001
-00110000
-11110110
-00111110
-11011111
-10111000
-00110000
-11110010
-00101100
-00100000
-11110001
-00000110
-11001111
-11001101
-00010101
-00011001
-00110000
-11100111
-01111000
-11111110
-11011000
-00110000
-11110100
-11001101
-00010101
-00011001
-11010000
-11001101
-11111100
-00011000
-11010000
-00111111
-11000000
-00011000
-00010001
-00001000
-00110000
-00000101
-11111101
-01110101
-00000000
-00011000
-00000101
-11111101
-01111110
-00000000
-10101101
-11000000
-11111101
-00100011
-00011011
-00001000
-11001101
-11111100
-00011000
-11010000
-01111010
-10110011
-00100000
-11100111
-01111100
-11111110
-00000001
-11001001
-00101110
-00000001
-00000110
-11000111
-11001101
-00010001
-00011001
-11010000
-00111110
-11100010
-10111000
-11001011
-00010101
-11010010
-11111110
-00011000
-01111100
-10101101
-01100111
-00110111
-11001001
-11001101
-00010101
-00011001
-11010000
-00111110
-00010100
-00111101
-00100000
-11111101
-10100111
-00000100
-11001000
-00111110
-01111111
-11011011
-11111110
-00011111
-11010000
-10101001
-11100110
-00010000
-00101000
-11110011
-01111001
-00101111
-01001111
-00110111
-11001001
-01010011
-01000001
-01010110
-11000101
-01101111
-00010110
-00000100
-11000011
-00001110
-00010000
-00011010
-01001111
-00011010
-10110110
-00000100
-01000010
-01010011
-01000001
-01010110
-11000101
-00110011
-00011001
-00000101
-11000011
-00001110
-00111101
-00011010
-01001111
-00011010
-10110110
-00000100
-01000010
-01001100
-01001111
-01000001
-11000100
-01000011
-00011001
-00000101
-11000011
-00001110
-00111101
-00011010
-01110100
-00011010
-10111000
-00011010
-10110110
-00000100
-01010110
-01000101
-01010010
-01001001
-01000110
-11011001
-01010011
-00011001
-00000110
-11000011
-00001110
-00010000
-00011010
-01110001
-00010010
-00001111
-00000000
-01000010
-01010110
-01000101
-01010010
-01001001
-01000110
-11011001
-01100110
-00011001
-00000111
-11000011
-00001110
-00111101
-00011010
-01110100
-00011010
-10111110
-00011010
-10110110
-00000100
-01001100
-01001111
-01000001
-11000100
-01111000
-00011001
-00000100
-11000011
-00001110
-00010000
-00011010
-00001110
-00011010
-00101010
-00110111
-00111100
-00100010
-00001110
-00100011
-11101011
-00100001
-11001100
-11111111
-00111001
-10100111
-11101101
-01010010
-00100010
-00001100
-00100011
-11001101
-10111001
-00000100
-01110100
-00011010
-10111000
-00011010
-00001110
-00011010
-11101101
-01001011
-00110111
-00111100
-00100001
-01010000
-00111100
-00100010
-00000001
-00100111
-00100011
-00100010
-00001001
-00100111
-00101010
-00100101
-00100011
-00001001
-00100010
-00110111
-00111100
-00100001
-10101111
-11000011
-00001001
-00100010
-00001011
-00100111
-11101101
-01011011
-00101001
-00100011
-00011001
-11101101
-01011011
-01001100
-00111100
-00100010
-01001100
-00111100
-11000101
-11010101
-11101101
-01110011
-00001101
-00100111
-11001101
-00000100
-00010101
-11000001
-11100001
-11001011
-01111110
-00100011
-00101000
-11111011
-00100011
-00100011
-01110001
-00100011
-01110000
-00101010
-00110111
-00111100
-00000001
-00001100
-00000000
-00001001
-00100010
-00111011
-00111100
-11111101
-11101001
-11000011
-00001110
-01001011
-00010000
-00100000
-10101011
-00000101
-00001110
-00011010
-11001101
-00101110
-00001111
-11011111
-00111110
-00100000
-00010010
-00010001
-00001100
-00100111
-00100001
-11111111
-00100111
-11001101
-11111010
-00000111
-11111101
-11101001
-11111011
-00011000
-11000011
-00001110
-11110011
-00011001
-00001110
-00011010
-10101111
-00110010
-00000001
-00100011
-00100001
-01010001
-00111100
-00100010
-00001110
-00100011
-11101011
-00101010
-00110111
-00111100
-10100111
-11101101
-01010010
-00100010
-00001100
-00100011
-00101010
-01001100
-00111100
-00100010
-00010000
-00100011
-00100001
-00110001
-00111100
-00010001
-00010010
-00100011
-00000001
-00001000
-00000000
-11101101
-10110000
-11111101
-11101001
-11000011
-00001110
-11110011
-00011001
-00010001
-00010000
-00001100
-00100011
-11000001
-00001000
-00010001
-00010000
-00001110
-00100011
-11000001
-00001000
-10110110
-00000100
-01010001
-00011010
-00111010
-00000010
-00100011
-10100111
-00101000
-01011111
-00101010
-00001100
-00100011
-01111100
-10110101
-00101000
-01011000
-11100101
-00010001
-00011001
-00000000
-00100001
-00000001
-00100011
-01001010
-11001101
-00100000
-00011000
-11010001
-00101010
-00001110
-00100011
-00001110
-11111111
-11001101
-00100000
-00011000
-11111101
-11101001
-01110110
-00011010
-00010001
-00011001
-00000000
-00100001
-00011010
-00100011
-01001010
-00110111
-11001101
-10100111
-00011000
-00110000
-11110011
-00010001
-00011010
-00100011
-00011010
-10100111
-00100000
-00001011
-11001101
-00001000
-00011000
-00001101
-01000100
-01101001
-01100011
-01110100
-10111010
-00011000
-00001010
-11001101
-00001000
-00011000
-00001101
-01000010
-01111001
-01110100
-01100101
-01110011
-10111010
-00100001
-00000001
-00100011
-00000001
-00001011
-00001011
-00011000
-00000010
-00011010
-11001111
-00011010
-10111110
-00100000
-00000001
-00001101
-00100011
-00010011
-00010000
-11110101
-00100000
-11000010
-11111101
-11101001
-11100111
-00001010
-10111010
-00011010
-00000110
-11111111
-00011000
-00010010
-11000000
-00011010
-00100001
-00010010
-00100011
-00010001
-00101011
-00100011
-00000110
-00001000
-00011010
-00010011
-10111110
-00100011
-00100000
-11101000
-00010000
-11111000
-00101010
-00001100
-00100011
-11101101
-01011011
-00100101
-00100011
-01111100
-10110101
-00101000
-00000100
-11101101
-01010010
-00111000
-11010111
-00101010
-00001110
-00100011
-01111100
-10110101
-00100000
-00000011
-00101010
-00100111
-00100011
-00001110
-11111111
-11001011
-00011000
-11001101
-10100111
-00011000
-00110000
-11000100
-11111101
-11101001
-00000001
-00001111
-00111100
-10101111
-00000010
-00001101
-00100000
-11111100
-00101010
-00111011
-00111100
-00010001
-11111100
-11111111
-00101011
-01001110
-01110111
-00011001
-00100011
-00100010
-00111011
-00111100
-00101011
-01000110
-01110111
-01111001
-00001111
-10101000
-11100110
-01111111
-10101000
-00110010
-00000010
-00111100
-11001011
-10111000
-11001011
-10111001
-11101101
-01000011
-00000000
-00111100
-00100011
-11101011
-00011001
-11001001
-00111110
-00001001
-10111000
-00110000
-00000001
-01000111
-00001110
-00000100
-00100011
-00100011
-00100011
-10101111
-11101101
-01100111
-00101011
-00001101
-00100000
-11111010
-00100011
-00010000
-11110001
-11000110
-11111011
-11100101
-01111110
-10001000
-00100111
-01110111
-00100011
-00111000
-11111001
-11100001
-11001001
-11000101
-11100101
-00000110
-00000100
-10100111
-00111110
-00000000
-10011110
-00100111
-01110111
-00100011
-00010000
-11111000
-11100001
-11000001
-11001001
-00001110
-00000001
-11100101
-11010101
-11000101
-01111001
-11100110
-00001111
-01000111
-10101001
-01001111
-00001111
-00001111
-10000001
-00001111
-10000000
-01001111
-00000110
-00000100
-10101111
-11000101
-11010101
-11100101
-10000110
-00100111
-01101111
-00011010
-00100110
-00000000
-01010100
-11001011
-00010100
-10100111
-00101000
-00011011
-01011111
-11001011
-00111001
-00110000
-00001000
-01111101
-10000011
-00100111
-01101111
-01111100
-10001010
-00100111
-01100111
-00001100
-00001101
-00101000
-00001010
-01111011
-10000111
-00100111
-01011111
-01111010
-10001111
-00100111
-01010111
-00011000
-11100110
-11101011
-11100001
-01110011
-01111010
-11010001
-11000001
-00010011
-00100011
-00010000
-11001100
-11000001
-11010001
-11100001
-11001001
-01000110
-10101101
-10001001
-00011001
-00000010
-11000011
-00001110
-00001111
-00011101
-00001110
-00011010
-00011000
-00000111
-01000110
-10101011
-10100011
-00011011
-00000010
-10110011
-00011011
-11001101
-11110100
-00011010
-01111001
-10010000
-11110101
-00110000
-00000110
-11101011
-11101101
-01000100
-11011101
-01110000
-00000000
-01000111
-11000100
-00100010
-00011011
-11110001
-00110000
-00000001
-11101011
-00000110
-00000010
-11011101
-01001110
-00000010
-11001011
-00010001
-11011100
-01000011
-00011011
-11101011
-00010000
-11111000
-11001101
-01010011
-00011011
-00011011
-00011010
-11000110
-01101000
-11001011
-00011000
-11011101
-01110000
-00000010
-11000100
-01000011
-00011011
-00011010
-10100111
-00100000
-00011001
-11011101
-00110101
-00000000
-11011101
-00110101
-00000000
-11010101
-01100010
-01101011
-00101011
-00000001
-11111111
-00000011
-10110110
-11101101
-10101000
-00010000
-11111011
-11101011
-01110000
-11010001
-00100000
-11100101
-11111101
-11101001
-01010100
-01011101
-11010101
-00000001
-00000100
-00000000
-11101101
-10110000
-11100001
-00011011
-00011010
-10100111
-00101000
-00010001
-11111110
-00010000
-10011111
-00111100
-00111100
-01000111
-11011101
-10000110
-00000000
-00110010
-00000000
-00111100
-11001101
-00100010
-00011011
-00011000
-11101011
-00111010
-00000000
-00111100
-00111101
-11111110
-10111111
-00111100
-00110000
-00010011
-11111110
-10000000
-00110000
-00001101
-01000111
-00111010
-00000010
-00111100
-01001111
-00010111
-10101001
-11100110
-10000000
-10101000
-00010010
-11111101
-11101001
-11100111
-00001000
-00000001
-00000000
-00000100
-01110001
-00100011
-00010000
-11111100
-11111101
-11101001
-01000110
-10101010
-10110000
-00011011
-00000010
-01001101
-00011100
-11001101
-11110100
-00011010
-10101111
-10111000
-10011111
-10100001
-00101000
-11100111
-11100101
-00000001
-00000010
-00111100
-11000101
-00000110
-00000011
-01001110
-00100011
-11100011
-00100011
-11001101
-01010101
-00011011
-11100011
-00010000
-11110110
-11101101
-01001011
-00000000
-00111100
-01111000
-10000001
-11010110
-01000010
-00110010
-00000000
-00111100
-11100001
-11010001
-00011000
-10001110
-01000110
-10101111
-01001010
-00011100
-00000010
-01111101
-00011100
-11001101
-11110100
-00011010
-10101111
-10111000
-00101000
-10111001
-10111001
-00101000
-10110100
-00010011
-00010011
-00011010
-00011011
-00011011
-11000110
-00000001
-00100111
-00001000
-11101011
-11001101
-01000011
-00011011
-11101011
-11100101
-00010001
-00010000
-00111100
-00000001
-00000100
-00000000
-11101101
-10110000
-11101011
-00101011
-00000110
-00000101
-11010101
-01111110
-00101011
-01011110
-00001000
-01001111
-00001000
-00001100
-00001101
-00100000
-00000011
-01011111
-00011000
-00011011
-11000101
-00000110
-00000010
-00010110
-00010000
-11001011
-00100011
-00010111
-11001011
-00010010
-00110000
-11111001
-00010100
-10010001
-00100111
-00011100
-00110000
-11111011
-00010101
-00100000
-11111000
-10000001
-00100111
-00011101
-00010000
-11101001
-11000001
-01001011
-11010001
-00001100
-00001101
-00101000
-00010111
-11100101
-00101011
-00101011
-11001101
-01010101
-00011011
-11010101
-00010001
-11111011
-11111111
-00011001
-00010001
-00000011
-00111100
-01111001
-00010010
-11001101
-01010011
-00011011
-11010001
-11100001
-00100011
-00000100
-00010000
-10111000
-00101010
-00000000
-00111100
-01111100
-10010101
-11000110
-01000000
-00100001
-00001000
-00111100
-01000111
-00111010
-00001011
-00111100
-10100111
-00100000
-00000011
-00000101
-00000101
-00101011
-11011101
-01110000
-00000000
-11010001
-11000011
-00000100
-00011100
-01000110
-01001110
-01000101
-01000111
-01000001
-01010100
-11000101
-01111010
-00011100
-00000111
-00010001
-00011101
-11011111
-01111010
-10100111
-00101000
-00000010
-11101110
-10000000
-01010111
-11010111
-11111101
-11101001
-01001001
-01001110
-11010100
-00001110
-00011101
-00000011
-00100100
-00011101
-00101010
-00111011
-00111100
-00101011
-00010001
-00000000
-00000000
-01111110
-00000111
-11111110
-10000010
-00111000
-00010100
-10101111
-00101011
-11001101
-00110010
-00000111
-00100011
-11101011
-01000100
-01001101
-00101001
-00101001
-00001001
-00101001
-01001111
-00000110
-00000000
-00001001
-11101011
-00011000
-11100110
-00101011
-00101011
-01110010
-00101011
-01110011
-00010001
-10010100
-00001101
-11000011
-10111111
-00000100
-01010101
-01000110
-01001100
-01001111
-01000001
-11010100
-00100001
-00011101
-00000110
-01011011
-00011101
-11011111
-11101011
-00000001
-00000000
-00010000
-01010001
-01011001
-00101001
-01111011
-10001111
-00100111
-01011111
-01111010
-10001111
-00100111
-01010111
-11001011
-00010001
-00010000
-11110011
-11010111
-00010110
-01000110
-01011001
-11010111
-00101011
-00101011
-11001101
-01000000
-00000111
-11111101
-11101001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00010000
-00010000
-00010000
-00010000
-00000000
-00010000
-00000000
-00100100
-00100100
-00000000
-00000000
-00000000
-00000000
-00000000
-00100100
-01111110
-00100100
-00100100
-01111110
-00100100
-00000000
-00001000
-00111110
-00101000
-00111110
-00001010
-00111110
-00001000
-01100010
-01100100
-00001000
-00010000
-00100110
-01000110
-00000000
-00010000
-00101000
-00010000
-00101010
-01000100
-00111010
-00000000
-00001000
-00010000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000100
-00001000
-00001000
-00001000
-00001000
-00000100
-00000000
-00100000
-00010000
-00010000
-00010000
-00010000
-00100000
-00000000
-00000000
-00010100
-00001000
-00111110
-00001000
-00010100
-00000000
-00000000
-00001000
-00001000
-00111110
-00001000
-00001000
-00000000
-00000000
-00000000
-00000000
-00000000
-00001000
-00001000
-00010000
-00000000
-00000000
-00000000
-00111110
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00011000
-00011000
-00000000
-00000000
-00000010
-00000100
-00001000
-00010000
-00100000
-00000000
-00111100
-01000110
-01001010
-01010010
-01100010
-00111100
-00000000
-00011000
-00101000
-00001000
-00001000
-00001000
-00111110
-00000000
-00111100
-01000010
-00000010
-00111100
-01000000
-01111110
-00000000
-00111100
-01000010
-00001100
-00000010
-01000010
-00111100
-00000000
-00001000
-00011000
-00101000
-01001000
-01111110
-00001000
-00000000
-01111110
-01000000
-01111100
-00000010
-01000010
-00111100
-00000000
-00111100
-01000000
-01111100
-01000010
-01000010
-00111100
-00000000
-01111110
-00000010
-00000100
-00001000
-00010000
-00010000
-00000000
-00111100
-01000010
-00111100
-01000010
-01000010
-00111100
-00000000
-00111100
-01000010
-01000010
-00111110
-00000010
-00111100
-00000000
-00000000
-00000000
-00010000
-00000000
-00000000
-00010000
-00000000
-00000000
-00010000
-00000000
-00000000
-00010000
-00010000
-00100000
-00000000
-00000100
-00001000
-00010000
-00001000
-00000100
-00000000
-00000000
-00000000
-00111110
-00000000
-00111110
-00000000
-00000000
-00000000
-00010000
-00001000
-00000100
-00001000
-00010000
-00000000
-00111100
-01000010
-00000100
-00001000
-00000000
-00001000
-00111100
-01001010
-01010110
-01011110
-01000000
-00111100
-00111100
-01000010
-01000010
-01111110
-01000010
-01000010
-01111100
-01000010
-01111100
-01000010
-01000010
-01111100
-00111100
-01000010
-01000000
-01000000
-01000010
-00111100
-01111000
-01000100
-01000010
-01000010
-01000100
-01111000
-01111110
-01000000
-01111100
-01000000
-01000000
-01111110
-01111110
-01000000
-01111100
-01000000
-01000000
-01000000
-00111100
-01000010
-01000000
-01001110
-01000010
-00111100
-01000010
-01000010
-01111110
-01000010
-01000010
-01000010
-00111110
-00001000
-00001000
-00001000
-00001000
-00111110
-00000010
-00000010
-00000010
-01000010
-01000010
-00111100
-01000100
-01001000
-01110000
-01001000
-01000100
-01000010
-01000000
-01000000
-01000000
-01000000
-01000000
-01111110
-01000010
-01100110
-01011010
-01000010
-01000010
-01000010
-01000010
-01100010
-01010010
-01001010
-01000110
-01000010
-00111100
-01000010
-01000010
-01000010
-01000010
-00111100
-01111100
-01000010
-01000010
-01111100
-01000000
-01000000
-00111100
-01000010
-01000010
-01010010
-01001010
-00111100
-01111100
-01000010
-01000010
-01111100
-01000100
-01000010
-00111100
-01000000
-00111100
-00000010
-01000010
-00111100
-11111110
-00010000
-00010000
-00010000
-00010000
-00010000
-01000010
-01000010
-01000010
-01000010
-01000010
-00111110
-01000010
-01000010
-01000010
-01000010
-00100100
-00011000
-01000010
-01000010
-01000010
-01000010
-01011010
-00100100
-01000010
-00100100
-00011000
-00011000
-00100100
-01000010
-10000010
-01000100
-00101000
-00010000
-00010000
-00010000
-01111110
-00000100
-00001000
-00010000
-00100000
-01111110
-00001110
-00001000
-00001000
-00001000
-00001000
-00001110
-00000000
-01000000
-00100000
-00010000
-00001000
-00000100
-01110000
-00010000
-00010000
-00010000
-00010000
-01110000
-00010000
-00111000
-01010100
-00010000
-00010000
-00010000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-11111111
-00011100
-00100010
-01111000
-00100000
-00100000
-01111110
-00000000
-00000000
-00111000
-00000100
-00111100
-01000100
-00111110
-00000000
-00100000
-00100000
-00111100
-00100010
-00100010
-00111100
-00000000
-00000000
-00011100
-00100000
-00100000
-00100000
-00011100
-00000000
-00000100
-00000100
-00111100
-01000100
-01000100
-00111110
-00000000
-00000000
-00111000
-01000100
-01111000
-01000000
-00111100
-00000000
-00001100
-00010000
-00011000
-00010000
-00010000
-00010000
-00000000
-00000000
-00111100
-01000100
-01000100
-00111100
-00000100
-00111000
-01000000
-01000000
-01111000
-01000100
-01000100
-01000100
-00000000
-00010000
-00000000
-00110000
-00010000
-00010000
-00111000
-00000000
-00000100
-00000000
-00000100
-00000100
-00000100
-00100100
-00011000
-00100000
-00101000
-00110000
-00110000
-00101000
-00100100
-00000000
-00010000
-00010000
-00010000
-00010000
-00010000
-00001100
-00000000
-00000000
-01101000
-01010100
-01010100
-01010100
-01010100
-00000000
-00000000
-01111000
-01000100
-01000100
-01000100
-01000100
-00000000
-00000000
-00111000
-01000100
-01000100
-01000100
-00111000
-00000000
-00000000
-01111000
-01000100
-01000100
-01111000
-01000000
-01000000
-00000000
-00111100
-01000100
-01000100
-00111100
-00000100
-00000110
-00000000
-00011100
-00100000
-00100000
-00100000
-00100000
-00000000
-00000000
-00111000
-01000000
-00111000
-00000100
-01111000
-00000000
-00010000
-00111000
-00010000
-00010000
-00010000
-00001100
-00000000
-00000000
-01000100
-01000100
-01000100
-01000100
-00111100
-00000000
-00000000
-01000100
-01000100
-00101000
-00101000
-00010000
-00000000
-00000000
-01000100
-01010100
-01010100
-01010100
-00101000
-00000000
-00000000
-01000100
-00101000
-00010000
-00101000
-01000100
-00000000
-00000000
-01000100
-01000100
-01000100
-00111100
-00000100
-00111000
-00000000
-01111100
-00001000
-00010000
-00100000
-01111100
-00000000
-00001110
-00001000
-00110000
-00110000
-00001000
-00001110
-00000000
-00001000
-00001000
-00001000
-00001000
-00001000
-00001000
-00000000
-01110000
-00010000
-00001100
-00001100
-00010000
-01110000
-00000000
-00110010
-01001100
-00000000
-00000000
-00000000
-00000000
-00000000
-00111100
-01000010
-10011001
-10100001
-10100001
-10011001
-01000010
-00111100
-11111111
-01011000
-00011101
-00000000
diff --git a/cores/JupiterAce/rom8k.ngc b/cores/JupiterAce/rom8k.ngc
deleted file mode 100644
index 703ae17..0000000
--- a/cores/JupiterAce/rom8k.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$36640<,[o}e~g`n;"2*726&;$?,)?40528456789:;<=>?0123456789:;<=>?0123476789:;<L>?8121475789:;<=>?012;05=789=3<=H?330E456A?1;H<K><012E4565K;>:J5?;31237127;>2:O==;02;34A>382:;=:?ID@D2BCDAL<:<HH;>C81G5CDB;=H>99HJ7B0A<4EB<M229K<7EE51020?;=>;7=>=C1C652360M2N99<:47635662MLK=<=6N0@11=FED9KO==<>M530A111689;;89>4010G7D02<93<N:O703D:G1@2?:>9>4O77@CG<1CC0MI;NLJ<DD@6770A9L?:;::?419346E08M>M<I<:25737F27L<?9O5:;3222453D8J29O9>?01201CBE80I;=I;:42A74>67<9;;<;:?10764036=<:;?<>;54721132=8??98;:547610329=:;<=;:5077102739:H<5>IC3AE456>8:;H>9?L0BA145678::H>>HLC12175678;?>8=M=54204=648=:0<=K;344360>>89<;<N>?545@766D;J>8<N=L0222<57?K9:;?=M?0B20466D8::88=5?1@63E=B?<=2HOK<<BGGF67?28=KH<=;?5467<520992:8=:<102@152E<8:;NLL;0:22G5608:?<4=M>063@0457JMO9<:6>C0D334@6<8;8O=>701:07F17?9I;?:>?1163?547NHL>O<L=3B6E742C?8?8HKL:02CE@CB3K;:3M8OJBB2G@A@CJ>:IH46JAB@1@16<8;>=O9H:3177AA7708NI=<??1DDA<527;HN=:9M=2EA30=7?J=?>==>=D4630553<91;>5>=010;474FI9KJMLO?030;4=4?:H2;>5<N8@CBEDG?892;<?ON810BED4?09:?<6>=FDGG1<D0MMK>J4M84@2EF070>?I>O8J804F555DCLOKI8H>>A11774EFK?O=?5:?;1134D>DK1:94NM?0023GF678:H:O5>;85:@5=2D8::94N>;4167452>01I?<;??052846478K:;<=>?01A0G4E7MOI;J==?0111A63008I;O>H?FB@E46678OIHO=<?012305=7;K2H?N>I373G550A>M:2NO6N0GA1GD>A:M9<II>93B3G46G7;MK;I8=>0E5FF7E382:?8=>L1E5E20?6N8:<9KJ6655@05B0N??2=K>?36D3G56?8J:;4=>L01:3G55?NO>;7=:;41:1@032:O:3O5:;0B6;41E?989;=N:L3227A03AK1;O9>H=23204446;:LM<9>4063BE16799>;==>?012355778<>:<<>>55231572<9:;<9??01234062=<::9=?:419330328=;O989I0633F01AK9::J=>>36A347@4K<=3<==>C1D@4F5388:8<K9<06274>6?8HN>5;79A@;G70G10H2>I?LI9473=GD3K:KJ5N<?13210105MJ?:>;7N91374627393HO>?K322F45>?0H>H<N>;2567466099I;>IM?090:BAE?:M?MO=6=DBA05FE?9=:0<O;<FGDEGA@0N9:2I4J:9B134<@AN::M<=>?DG2344@58H=8;?K933D05@@6NJ2:8=5?B60@571?>J?NH9<?8B@67<47MJ:JJH>72E6FA1?5KHLN84>M46@B614C0?LN9L>;0:2@604C>8:;4<>M4413042789:88=OI22203160;>L3?5>:0B1755668;LJ5?<;4163?5E40=:;<N:;0BG3354D89::8>M>C123B7E4LJ:;<==7062045?78LI;?=L70123416<8J3MO4>705:;2A778<=<<98=24@71FCD;K:3:=<I09623CE>JK:3==7?EGAF1015<91;ON6;C16;<F>3<1>3496L8013F033JOLO;9>?05A;6GE7K18O98:7492;056D9M>?<6>LDE541CE1?0NO8;9J7GD6FF03?>=9OH?K11G40=75?;2J9>7?A1123340?;?H:<:?;1F311E79<;;>IH921:76A?D0<2I?O7LDCC0E2G7>H3NN==9C64F2@7E::8=:HK9D5284@B>><<9=;>M3@635527LMN9O5><0DF@<F6D=19I=O=<11F1GA>D1;?>=8>:452G7>7)8=:0==>MCD7B054DM8HNNO8KF@DAGGD1J?;3H?=L42AFA=6C1JH2IN7<2EF7EF0B1?O=8=5>08;24327<99H<N>?816;=F>?8J>;?8?>117504@38H?3;=>?14165545;;;8?OJ;0:33F0?EIMN:H>><4133156D8M:8<=?>2D42<4GFN1HNJ5H703C13=E4K1:=?>??2B63?47099N3;<;;04A6<37C8:3H;H9J6065FADB?8N;8=7;A42@G6648:8:<4;>7@;;A16<98I<J?==23024126;1HIJ=>MC1D2GA1EN9O;<=>J3GDE5F5?NOLM<==:5GF24567<91:=I>?7153457B8>:;<=JL1G6:451>8>I;?N>LF2:@456EN:NH<=9?712EG553<9:?<6?<0C56<<5D1=2345?74E23BG>6=;39N9=<F0:35A4C=:HH;9L:4107511E=:2?==:?;01110>7892;<=>?01:3656789:;<=>?0123456789:;<=>?0123656789:;<=>?006856<NFY__6LJKR@>26?699=1:?7GAPTV9EABUJ5;96=0>4:30>LHW]]0jhi|n<0094;733891EC^ZT;cg`wd;9;0;2<74128LQQVR\3xomij}eba?57<76=:0=9??0123106789:;<=>?0123456789:;<=>?0123456389>;9=>?0027456789:;8=5>5C;0<=25L=239?H;35:717B3N?2;8L>LCB47<@B4;>239=M:0E27E72DK:;2><L;0:34G3?489:HH=9?0123B55>;:9;<=7708735D67K9:;9::LCB0B=557K9I8<N>L0133?4<NFY__6zkn<183:46<93CE\XZ5wd`?4?69<91:O>M8C0D@4560;J:H?K>?0B34756DN=9;?9>?06D@7F>5L<?9J?><547EG54A:<;?<6?L530F<F3>K0;<<IK?62AB@6?D;=22?86;4773076099N;9<6J2917E=36K;8I==:?;0A54566;8;:>KM:844EG023>J>>9>O>401F5<37L?8NOL<>5@F050CA=L>>8<O6C5285F>3<9;?>I8KB131447E=K<H<9><03F4@C66;939H8:71C37<4D2==>;N<:?2C@505=6KK<>5?;=D0GE125D=1;OJLJ=FG0@E@7E9KO=O<8:01G5G4368K<H=:??B67@14C382;HJ<>M545E56@6:J>H<:<L0B5E4<27K8I:O=>I1003656A98:9??H>11004657J<>;7<J832@30<658:?M:9J8D67E347C<>>:O>:;BGAB=F@68JH2:K??405E360AJJ;??9>4211325>30J;349>L1E6;0=6D8KI?4=M;C5A3GFED;M>;456L89A;4F2D<J;;?><<41914163819:<9H:49:255E?9;N>856>1327B2E6NJ:;<5?K54760=E30=:;896;09:74>47I92;<=ON012;456781:;<=>?8121456789:;<=>?2323E545I;:9<5>?012345273;:HO=7;45634=6D0J:;<NO;01:755EEIO9MI9??110FGC2?89:;<NM?116705578=:0>?J:01A@01E7K9:?89672531745E<;8;?OK=A1C@AF14?<>;9LL>0474FD06KLO98=5=5G@E@622L;LIII=;54;41@@?J1>O4>9=F347@050>1INHIL:896;ACE?J8>;<H9;0:0;476F8;:3>56NA92B<56?89:;>?>?01234567898J4=O=012B4D67:18;4=>=8963?7>1:<>;9>>N0B6;44GC10?:<HLJ2EABB=6481>;<<>?81334647<;:8?=>?C1;0716<:1N8>;6IB5F37GBBL12H=:?;FD501DB7>>H=9OK>BGG:2GGB1?39<;77ADA6=41D<9194H:=7D::047D<KI8<;<>1667GGC48K>I>8:I5540=22BL832<597CB677@5FKJ;:<6<5IORVP?BNI5;1<3??;38JJUSS2MCI0<4?>0386?IR\Y__6IAN<083:47<:3E^X][[:EMA84<76=:0>O7=E9D;G641ILON;>JI2B2G7254N:9M=?MM33D;G7>E;=2:8=L?C527@7CE9=:88=5=C552B513:9:H4<?K55:34=568=9>996;0B6@<F>7K1>?O5?>216010478J2:?I;;0:0@<C5D8>L8?OM<E0G033@BI9=OM<KI00:@<G6B>H:8O=MN6G2B724DKH>H>:L=9G63?7BE11OJ?;<M6372F443I?I?4L:N443;FDB3:J2?:I:;0DA:75D3>H==>4O=115:416<;9?>4=;:4@DB2567L>;;<N=<0B3615EDK::H<;O;3@G;GFE4IL=;<=;:DE744367<918<;:?7B5351279<:;=9??513355739=;;=9?:55361172==;>=9??15361172==;?<6=?8223110AJJ?9?=?;93G5110D;18?<L>M3G1G3657<8;N;?>;23D44525;9:;4=:?;22@4=>?89HO99=?4G2045479::?45L?5DF345670OI3>I;;FB3@<5B28>I;;OM>0528746?11:>;9?;41A3077299=;<9M?43675=4ALHLNJ468416345E78JHO85:?05A205=49?<<O<HL36365527<=N2O=;8407301E7<12;O=>;81:;4F25==;;<==914;325738298<NM?92;3G<679=:;<N>;0123G574993>:=>?01277703:=K8?O>MAD236=22=9>;7>=?CDCB75?D80:94=>?C10;45GB08H2<=>?1@C74545>;:>>9LMB956@566<9:;<9>432A@256?99I2=57?015A2D>4I89JJLJL921374E088>;?IMKCBA34567:1<MI=>I4190=17B1L:>J?6;09AA4G>1?H?IO56K20:G5=430=?JO>KJEE7B7457>1O2=L6>A@@74>5>MJKN>?LME115AD0D<89J===IED004=6?=0NJJ?K;8232F75F:99J?=:?00661C273:KHOKMM48GAG360;02O5N8LE9:06<47818OM4L?41A0F=G?8;;=?LKN48GA<347:=:0?OM72223756A8;KJ4H>M31@1302600:299>N51F606658023<==>74A3=36>=1;>8=5<C21:43E7;J98<N=LDC::75??8:9;=57?0123456DK:9;ON>6322@GF54:LK3O>=;0:1@76E7;J:8O>=?C2A6756499;;?>>?11064177<9IH?>>LC42075EDK:9;O4>L0263?6E3902M<<K;1G12GF248:IJM>M;28D@556AKHO:<<>M03A375578K>9?=6<B116B16<;JL?JK=ICG233=6D<;9MO?:=02770524K9:O9=>L010G12@2;J9;<KML02A2G64A<918HNM?0B06@C3CN<8;<=>7D9DA@=67I03J54O<E3DFB@26<M::I=M?062@756D<::?<6=J98;31C5EM:HJ8=9>07G116>A<M:<IHJJE42@52C?1HK;5<>I763254>099NO5<:?;2GE=0BD1=;2=<9M981AA6ECN;??J99I8D;0F033<9O>98M:F502764E8H<H49M;A5287C26NJIH>OK:73AGBA@>=<3><KK=C8767C401:2<HKH=D146B5B0;;2N?:L<B6@@05=4N=LH<>??74607F568:?<J>M?3B2@B2>6K9:;J8;;F2:@45D5;;89<==I11D3@C?3829MOKH=CG0FG4CD9J9<<>>71B23B567K9LM?=>;822G115698;:==>?012F7F6789n0?~;?0ddd776*==:08=;M2BA2440AL1KO5<>;03AF1467<9>HIL998C:AE5>BIMH9<9=;2E63BC538J>;8=5;0@0G77>3?8O:M<>JA7C0<D55;J<;><:<7831=@6?1?HMO?L9022365?>?K?JNI8;0:6756E0K>;;?89I46534F67KJ;MO<KL15D4467D89N>J<M?0E716674;9L>856L8B63?122MLLO;I672DF27=?4JJHI<9J;97445C72:>=859K<92@G4215?8>M997=E9GG316<<=L;:K9J44367GE?<JKMH=HL7@4A02>D98O:=59JFDAB3G?21<>8H;JJ3G@EA45B<91?9>M<9922F@4AJL8II?KK87DB@F37?H:9<L<74323<<268?K94;67A0@AED45:H2?<6:92GF3B673N;:=:;H<82DG2<5A9=L?NK=ICC@BAD6?LKON948KBGG7<50DN;KN95:?;540<627LK<IN56;C977=2CD98LJ858;6G756C67;O334=7?CE1;3@4E;<:<NNM>C5280311<?=N9OHN322A1473=<HO94H:EG73A1G4M?;:J<K>101A=G4E0JL:?5OKF4CE05=308;9>==:54:35C6?<=2??=>>C6A15477:O;8O=6?8017703AKO;:O==L20230C3382>38?7?2GG34CDEILH9==6J4B@2=D0?0;HN>L6N8C4E6110;;8=NNO7BD6644E78M>;79LJ9@12F0CD18<N<?K<AD1:FDD1;H<>J?J7E8;75G1EI?>2IO9MA0::F1D?N<K;:9>44EAE7GB?N:H;8L>796;60234<=H<9>9>145GGF?E1M><>K;643GFG4G19??>58>J4197A50DL<:88KLJC5GA6174?>8;<HK=F6;;<@GE=1>M9?LN3EF5@4?7>;9?8<MJE6274>2A8ML>=K97D0@2<1@4M;>?IL?>42G70464I8;:J8O8D8427214?<N>=4L;07323G273=L;I4>NF3G4<CDEJL8H>H6K23A54761>;NI>HH<A7CB1CC308?>HLKNB9A:6CC1I=:08K6?31734646::;;<=6<03034544MHON:OJME3045GEEMMH;=9;>1G:745670OL>8=5:0477456789:;<=>?0136116289:;<<;?0423456789::<=??42234577<9;;<9>;0:73F<608;:988=:70074=>>;>K>;=<;0322EC6BN9I3I>=J6D7626C5J=;8HOH=1163?07C8=;O;;;I2EFA01?6IMKH<:O>003F<4>3MK:O?8>K85D@2GE?LJ<::K:J37FAB16<=;>;H=6K000EA5058?>OJN=IC003<6@A8=3MJ=M?7923076DK9=IN=<88463442A<91>?<<LE@312C@?IL<J5<=?472364>>J=NI:8KK6E:57<56MH;J4I9M93C6E0>C:H<?<6;<8G616CG4;:N3;967CCA:@7C31O>8<OJ=3810A4>7L>82<OKICG0573CD?>IMM=:?;4663110>HN3:O8>AE:A=A079:3=;8>9D76:F2BB>ML?=>;>8632G4639MNM;O9>352811ED8=N38=?<751074@?8JI<O:??346E5F7D<M:;<=?<F12002E7:MLM<K:95B1305=2==;>H=:L723@4F608JI;8<=<0E7@45@B;<LHO=:?292G457B0;:3<9=L56:2G5E382?>98;:50771032==;>8=>;0123456789:;<=>?0122053689::<8;?107315668=>;78;ID0DEBC6A:899<K;:55:7G=7C=<?HN=HK5DD34F6789:I<>=KC222GF6599>MO9>4594A2<?7=?H>O=:<89;34DBEI<2H8L;=707@1062:>L=JKL624212F56=:H<;HH64196=<@E;9:><=<61E26=12F;J>3O4;M77C23F639>I9I<7?1C2A6D>299>;N87L25374>3E<J8?8O;;8173BDEA11L34OKM0C23@50DMJI99=LM132655DE98::=<7I6G@6EF273<H=9N?I46F:=20BLMK><::L142765?608:34>:=0B414A5?=9::N<6J46F02G@E8=:09OL:3C0G@7@2NM;IHN:I16D32A17082IM5=;D5G13DB5LKL9><6L8CCF0F3C8K8M8=5:FB62@0@AK=;O;=>800135467N:9:<>;8C9A34A3AKO:;?8;I8G23F0BA?MNM<==;0:4310>489:=<57:45:3443?:>?H<=6LC8:01A2D8J9;O=JK822;B567882;<=8?0D63?343K;L;N9;>09A:6@12<=<>><<;90323C@6;8<9;K<:2C376155<>3?9<>7480G=16<>>>>9L;665C1BD4DKK:94I<L1B604A>F=<;;<8;I01@B7476;9:;<=>?2337A174<91=M<>727@605>51?2:?><J1207GCC2992;5?=I51;34=6C>O;I8;>?23@@BF5C8O2?<69?032244C381:M=N:?3BA44F64?J:I<N>7C22@466389>?;==M012E5C6489894L:?;627AF648JI:NH7<91234G278;:HON>JC123756488H98?M?70F344E38:N8J=M?352835GB0=>O<NH7E30G<<2D1:88=::K0B5B3A>0LLL?>O=N0CCAB03B=>;<NL>LBD@@05=09J:NOI9KC153451?8:>?<:><CG1EAC@79J:HNK;<01DE12>78>::INJ>0B27066382=:O96>6BA7B5D1=;K;<N<N9D5242>ELK:;MI6N4BA072@AKL?3ON?<D64:2@66=K>;7:?I3B2375D3L:I?8==K11D3456589L?;KH<FB@6417789>;O=JJ0623G5579J:H<9>472075423?0?J=<H:7GG70<>3?9L?9KH=07A:A@C0118H8;6?B5727524K<L;>:=?41941C6?M:?3J5=JB5142<65=KIJHO9L0E6:EACEN=N3:4H:D27B0G37L;:3M88J68674>12NLN::;6NECCF4=BBNMN3I==836@GA=57:=KN4N>MFD11235DILHNI46K3CFE0F273><9<57M8GAF66>7:8K<?O7?A043G76D::8HO5><011F75BCI:9;<>L7C@@5@F17;=:0;N:?09@0GC2DNJI8OO>?C0A344E7;O;:J<?I2G1GF1678J2:>5>L2E624177?<>:8=58CG450364K=?=N:JK57@4@GB01>>?;8;J4D77507A0<3N98H:547@ACGF;L>I>L=;0:5FA5D7J:<:??O=F9;G<GC>I;NJN8>N6766G24E:M<;N9:;09@FB527?L2:<?767E63?2@FJJL2INO=23@23C@0M0LHHN7L31A2G324=OH998;M242A51?AMH;>J?99FE@0616<?OO:H:?=264F=0EEM>?M9H;I9724@2@EL?OM99KIB037=@??=:<I?9;67D1E42@A<91<JK=IC6D04@2?K1I8NKMIF22BBF61=L:;<?>M547345>5L<?9>=<?333075129;;?<66?7C:33DBFJKK?89>?C1GF6=C58;L9;56J4B33FAGEJL88JH?>BD31B@46K<3MOO:?;92GE@D?M1I=<I8M9@71<ACDM;<>N?8<516G4<E?KLNO=O:90G4570509:??>9H=F528<4311K2?NOJND1@;A7G3;O3OJN8K6BCB3D>AKK>O8>JMF6:57FDFN?><MI=82G0A05=?9?N9:K>NEB63FF57IJKI<>:<85F4G2E7L8>N<>K;A1FA<D61?JK2NN:?BG2@5523822:;8LM6B6345BD1L;3:I8>9@GGB1@5>>NO;:7J3GFG21D1L1=OI9>=E265B3B38M>;75?NDEC2E72C8;H==5<L46GA031C0=K2OK:9AC24F<E0LLK?9??<02;AF005<:<??9>483627AE4<0LJ;IJ8EG;F3233M9LO8IJ8655FG@1CMH<;9I<N4DDGBAB>9><MN58J419;05E6L<??<9>L1E766777;9=>9???31161777;9=>;<?L3C1G77E7;9L:5>MJCB174>>3>;O39=O60240@2@E1;?H;>6;6BC64A63L?:2J?L;2B1:4G5>813H??:JD026002731>H;;:95BAA7<CE:HIM=NO73DDA2<@5>1L=IK8>A@:45G@5JHLN4O:MFCD43F0E;=:04;=NEGGE<375>8>O?H7;01:BF@@?KJ8:8>JNBD7:BFDEM<23487MA9A5G0B1>L<88=5780F6103ANO:9>?=?347616@DJ9L>JK<I09325556:9I?=?7:7567<1@48=LMI<<;0::;@@E4>1289?6=0@4F26>>N1N>=:K:C4F:F0@E>09I4=6;255@2A16?92:M>99C063?=?781<:=H=L6E75605AN8;<MO?92GA3BF>A:;8?;<JNC82E4F54=;I3I96NCBD4047<03CE\XZ5dhlb82<768;047GAPTV9`lhe4>0;2<=48;MVPUSS2me~xl28:1<27>>=G\^[YY4kotva82<76=:04N7756@577420;8::;H79@:G0F46<;;>O?H7085F=G4?1HLJ4O87E5533G55M1?I8=5639;@3=E6:8H;I9KJD202=5@E>J>=JOH6C66F7=GC=KI=OK=9F8G67GD6:JKN?4L;0:;7550C=0>99H:?C64;36E48M<O5OL>6560A67??MO948OI1E021524M>;3;<K=8E63?<3A?MI2;97<08;5@030L>=?9:;;7D047=73L8;O4N<:E6642734J;H9==L:4EF1516<11=IO:??65:7<F7E8KLM==8=02136F6A:>:;>>>I0100B127M>:;>=674B1G3A@6<91245JLB03630GB19;:N;<9ABCBA@GAM:;;O?>?112@<737>M?:<9M?205B76??>:;?<677EDG5EC0BLHN2NK<<AC@1=D0C0;:<J8L68BD0E=7AJK2?55H?B7A254@0:>2OOH:?;8A@7C?1JK:H5;L<0B5G2D148JL;;OK<2DCEGD4A9O=M5;99E64EB@57IHI9J?66C528=AG5;?22M;O=022F2526;<>:M>7;D42640628=:34>K?5E665516<8>;J<?=FDA205=>LLH;<N>>5DAA5A5A8<:HH=>=CB1@4F5D;>89?K?<33017445:;:9>?=>022A1033823N9I>8F@:E<=BCJKLO:HH:C1635A7CJ0?M;:JK46GEE54BN:H=;IJ864F;BD1B=O>;74H6CG01G5>?0H29:?668@2BAC4?>O2=M?:=2837E06C<J?>=OK7690;=5G5I?=N>9>49GAF@@6D8=H9H=7L0B7@535E1OI35OM?434@<31D1J9;JKMNA2A332@4:?28=<JM419B63@1>?<3I;<J77456=>>J<I<>?L6B4F:A7D?J;N2HKJL25GE<6230<?M8?7LA0774>G51OK=4K8<0BA00D@E<KH9H:KID7D361E7<>L28?L628:203?789I;8OH64@@:50273H8MJL>;C3152753JLN9NLLJ9@DF=3639;;?<=:<01675563988MJ?=IE@GAADCAN=:0M9>969F6@00C><O9HH9NE@A725@4:KO85=O<C3A@7A4FK8N;;=<ID9612CCEMHL=8=5N5566G10>==>N>H8:39CAE<27L9:8:??<087;660A=HO=N8?=BD:173G?<KKNM?8;0:C5=3?C983?>O993G;@77G0JM?<:>M?62G0GD2AI=88N?LIA51A6<BF?:H95?L?1863?D1E>K99M9J<5@737046==N2=9>;22F;4A4?N>=:O;6>452265?7>==NM86K8B:1<16<IHLMN>:J3G44<F45?O:>5N79B5D:6F@61J?IO>OL8C::B=0F;1K9NL>L114A=GG4<91JNL6JE@20GC@F1?<JM56NA0234176K?<I:;<:C12;65D51<?>=L69633;==?F:82?<6OMB@A@ADBEI:OJM>=6A3217D5?0LKN4OON07@6E775:;83O>:;43337054=MOMMH:?;@@@6265<8K?:=>601A34564K:9:O>K?31A0G55609:98N>?19;@45CFJ99;ON=?3528EF4DI8:I>5<=0@3F0616>LI:;???B3;G3C2>KK=:44;6533460C71<O8I5HM090305=FK=22O<K9AB20GA>BLKI;I8H?BB3375?2;8334:;LDE77@G7AJK3I4<MM744207B?3HNO^L2?>89B@ATF48:556OKDSC?548e3HNO^L2>2;2==>GCL[K7=?07;@FGVD:6611JHI\N<3<;?DBCZH68255NDEPB818?3HNO^L2:>99B@ATF4?437LJKR@>4:==FLMXJ0507;@FGVD:>611JHI\M<1<:?DBCZK6:<374AEFQF9766k1JHI\M<0094;?<IMNYN1?=>99B@ATE48437LJKRC>1:==FLMXI0>07;@FGVG:3611JHI\M<4<;?DBCZK6=255NDEPA828?3HNO^O27>99B@ATE404?<6OJ8B@F<FBEJ?O<:?>9B8@57163:9:8MOL7BG;;=3>7MHO3IKO;6C;BA=CB0KHJ?O:?;@D2=70019L3<;>K4D0@E534MOHIJ5O=CC@;2<2F<K:N>5;?80D2G1GA1<>2O>:N429BHI273K:;;<>854014477<J;2>>>>222FG533?>2:O==?4GDE45E68J;8>K>>0C27GF6D;=:0N=8NDDD4G642?:H;OHJN36F0EG>D?1NN49H8957GA55>M<;<9H>?FB7B@F1>NM?J8=5M08;14D750;=H8L7;9B17E246M92><L<L60200@@E19H;5K6=48AA35?A81OH>:6;0:@24566N9L;<N=;0117=57589>3O=>L01AEAF6789:;8=?J02230547;:9M?NM?0163?G40>93O4H7I66CFB11BN0;2>:<:D1543076?<;:IH9:0057<1D0=MNOJNH79BG3116<J?<J9N6;44@B04E>LH;8=86<65A@40>BNH8?I>6:55736@2EK:>H<<;;99505AED<91IO>>>1BG521EF:O:IN5:>00:B02?5NL9:=:<M69C6G6D3=>N>OIKJ59DF6@73N=<?<6LKE71;0@G1L:HJ8H?7E9F4<FB>?O?2HL9=2C30164E1LOI>NH>37CA53B1MH=?I=:?;CFFA340K8H8<;L7FC@;@533IJ>J=<LN595E7=B>0MIO>9M>0CC@=503I>IN>OL72528FC37<J=O8N::114E516A=>?9=<>L4B4G7G@EMO2NIN6>512@B2>38=?::LKJE9@17>DR:11IY^QFNGM74>E7<9:94KJ?4B67G561M>8;<=>J4BA;05E?892;<=OK9@@:@3368:KM:O6?2CF316273J:?>9:>9123=50A8J:;=4>;04;00677<<99NN;?41C74467<KN=546>7B13116?9=:0O=6ND5AAA1G>10ON;KMN54:A=D2FL083H;>;D7F:=2C0N>8OJ;7=D5CE1@3DKOO:8=5L0BF@=F@7;L;H<:>?321E4C5CK9L8<NL<02:3@=15;OLM<KMI4G@34CE3?;<?;=L;0:A24<E10K>>=58?8C4A=0C0?=;O<?=814F321649932<;><D1D@77GFN9;8<9M>3B63?F76K<:;ON?L7400EF@FJ?=:8IJ<405730>6>92;59<;E@CBG5?2812:8<>?7162416<K::9<9HL0123546D9OI8<:H>04A3356B89:;<=>?4153644D8>2M?=>?0113302?<91H?;<<0G:F@3DFJOI84HL:2BCEBFB0:M>I>OHJ39GGEC>AKHL;ON8?F5G;EC>A0K<?<6M<D6A0=C57N<9MJNM<9GDE75@4L8I<ON<MF55@<7@D<>I3>4HL1203F2@2K>I3=I:?;B63676E9<II;HM74B@61A54L=:;<8>;94@:=0D6IH2J4OJ78B27072E==:855:;B528G27A9>;IM=6<D3AE17>4;O=O?IL>A4644265=:;>4:8J98;57C>B98N:9N?NC0GF05=D00K<O:=?4CF47A4710;<H=:NDE6E6<E5K1=<=97L11;00433:1O<4K>912;E4A6382I2>L:?31@7G1679J>?58??323145@2L;HO?=LJ50133@B2<JLO===LC5:3714C19>;7NM>1161=47A8M>389=ND5350@EF;LI:J9M;81676AE0K=9;;OH?23@2=5540J=J>9>4CB1G10358K?<J>ML0GG0GA5AKOL>IKHI2B2EG5E3N9H?9>HLBG3E6C@D<88;8;>8419@G6B0N>::ON=KFB33GF4C=>9H?<:IF3G0BA6A8:N8<>>8C16:5557?<=OML<?79274>ED01I84OM70123GF5DN899>>>N4967<1ED09>3O<LIDD1042@58H9H<>>719A@4@273JNM>H=?5B13G7609JNH<:ML723@75E4<>=H?4=L83;34557I>LM<>J8F0066166:=:0OH=8946500G1LLI;=HJJC51B@G7?8L?;JK8:A8F;2DEB0=NH>IOL2GD7077589IH8=5LFB2@4F6389:?<=??3@207F75<0;?9<>?11A34567<;>3>97>49D2416489:M4KM>2:AKAFMXD@INB^KPTXRF0>EKCH>0OAEM9:ALIHOS\LN:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN?<6J?542744DD1=98<=?741234533=<:=:>J?C52711779<;;;I?8DB2@<F45N8OM;=:?;E372FE38::H997963D;<F75898MHOON844EE56D:9;I<=6>001357778M;;O=:?4528@751MON8;89971F@FG50M:H>INM<B@A;<G@4N:2IO>L=DE6@GG@4N8==N=L?2DDA05=C<8HO9H;I731FF6009=???9?LEC@;A=11K18=4?JND717=220><I:;9:=E5156=3382N>9KM?40F63A67899:<>;8C12E55D2<O:8<=>?1DA3456DN9I;?I9I4B2@@F6?<9>;7I9;5576572B1:2N5NKIBGFG5<268<>>9:H86G;600@?9<>2J;JKD@561F@0>KHOJ9>4D92BGFE?9O8O>4;>F05G11G>08:2:>7I64D72427==2;<;J?AD201D25:9?>;OKJ419G@63DI<H<8I9=800AE7649=;JJ5?JDG@3FF47<O><8<>ND4:5B3EC?OK94OK;A3A74>BCK9<?=<>>D5260474?>=;==>?35535F23;=?;=5:;CCG5=21D:LNO9=KM741A11273MON88O:06@B04D29<:?OO=JA5:4<117=LN?8<K;5B:1GD14JL2>HOO8B27F3AE1:?1OEL2?>99GMD:6294=7IGN<0<5?AOE49437IGM<083:3=CAK6:2;5KO@>3:==CGH6:6=09;EMB84813MEI0=07;EMA84<76?1OCO2>>528A13>IOH:9:MM735BADE2N;NH5H96245@F2400H8O;KKJA76F2D37NL<3I9KJ5E7E05=B>=HI<:M74560<FED;H8OO>LN904@FC30:13J4HM:A84F22G6=M:389KL98CE<<2382O=95MJ001G5737==;;O=::41:@12?70:K:9?<<C40610B7:OHNNH=75524BA6>KJ>;7H8I18;;15E5;82248;N9CA556E2JKI==9>:B9A6@140M;;3JOK:CEA:A0@E9H99?9>4E6DBG=C4K=N3:IOKFB1E@C63;0N3J=MLCE2;664B9?H>?>MLA0@BF55F;:ON>KM?419F<F@6>0;9:57=012365D6098ON4=721@FA6D4>L8JML>?F23BG7EDKLO3J?HN73D74>C?MOKI;=7I47CA<36?;=H9N;=>6D1B416FM:HM;?6804061033<JN>J8J8F651G@273LHH4?:<0C0745678:IM?HHI11@3055789LMJN><0BA;5A3A8O;NJN>>CG0370370=:0INO:EE@2F@EFMK><=HJ69CCB7253>LH;MK<NB1DAG@45NLLJ;?6L6971@=D1<HLM8=5JCBA3<1E?KJ2H45>LC9675775NM98<H>J0B24451A=J9HO=LIFG1EB47>M9:N;9>;0:GF34>3N;39;;?82C74A4@A:=O=4>O=81:GB@44LH9=<?<<110156DD:;92NH>6AG63?@C0N>8:=KH>05D65F44L<2H9I=:CC4:@2CCI9?HH4;:73544032=J=>59;JE5;@26=BFH90ICL;0:D345E41OLMON<LD3@2B6@689>I99<?0B226A358=>;=<J=D1@76F5D18IIO?J?B163?C741=:NJ=>74E56037F=<=;4?7;DB;@@730JKI><<8;9BG230EEJ92;H::L9BA3516<N:L8O=>;BD1EG6@5<9:;<9H<C223G5E7KOL8JN><0E:644238::;<N>=0110G174<91M88;:DC3AACDBN??MJ=>;8DFAEF>1I892=>>9E3F:BFD?1=2=5>:9435GB23C89=?<6H;E3@B1<7E=<=>ONHJ7777A5>6?:?>:?6:B763<@1D8>>9NL6L3@C@6AD>>L:2IK:?;G7@G75?=OI<=<?<B81B@6GBKL?;9=>MCE660154><KO>9H994CG6C11?1O:NO=L8528B33E81;<<KL92353F5C60K<H>>;92DGBA4DBIO:JII6K70GABG4A:O2<>NL<6D0;05=A?:N;<N?LE153BF67K>>I<K9?06D37567NO89ONM?7B117C@AK9:IJKM7F2DE4F7382L<89??2G20G4B4;O;;8KM<CB23751B8:HO8:MIF123G=640J9HJNM=32D0B554K1>;7K6IBG6FF4D100IHH9MNA9;@F7>E;;>:<HH<160@@7G791:O;5<J9G6525>1KK9=?9>4F8C44@B3M=;84IHLEE72@A370:?OHK7I4D55@GB?9:NJ45?828F@3@>BI1H:<:>N419E=DC5;HN3=L:L33A54D44=89M8=K?CEF34A549M=:>???32024573;8;9<=>645274>@>K0?N8?;?9061446>N:?O8=<IAE6E4F03<:IINK<78@5A65?5LMLII:7>837B@1273OK9<=>L70A7FG2>I<O=?H:6B92E<2>DL<?2<>6:F1;026@CKOLM<=>?001;B=>DL=:0JI98E3F65773KMNH?IMK0BFE35D0>:K94O9:2DFF6F>F=HOI<<;;C047@7158KOI8=5ID@DF3A@D=0L?H=L?FB7;A1ED;OH3H=<<F@D5@71EJLH38<7J19DG@GDA9L??NKL;0:DF=@@E>>I?9>KID4DAA0B>KJ3:?;J<18D4=012=H2=;::>8B@413EE?L=N;=;K5E63?CCBK=;M;IM<09D0BCC4NL>:OO6;15370062JJ?><O==C0A5=4CDM:LHIHKM5103316<NOH=<O<I89AG<56F;1;<;>;I3DG1F344;=2=:=:<0E@AE<0DK:<M>>=9B9A5=6B1<91MJI9IC2G6E734M;K:?IL683A4@1260KKO9KMM8C27GDCCN<NHI<;9A5202757LLI:7J=4GOF4?LHN\V:;;6GAIU]352=NF@^T<?94IOKW[5503@DBXR>;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D1<AGC_S=L8;HLJPZ6D?2CEEYQ?D69JJLRX8L=0ECG[_1D4?LHN\V;;;6GAIU]252=NF@^T=?94IOKW[4503@DBXR?;7:KMMQY6=>1BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1<AGC_S<L8;HLJPZ7D?2CEEYQ>D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D1<AGC_S?L8;HLJPZ4D?2CEEYQ=D69JJLRX:L=0ECG[_3D4?LHN\V9;;6GAIU]052=NF@^T??94IOKW[6503@DBXR=;7:KMMQY4=>1BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1<AGC_S>L8;HLJPZ5D?2CEEYQ<D69JJLRX;L=0ECG[_2D5?LHN\VK=7D@FT^@5?IIFLLN<7AAHIBCOg>Kfbfx]i}fooa8Ilhhz_oydaa3:L246=I9890B<<<;O307>H6<:1E=8=4N040?K70;2D:4>5A1808J75<F;287C<63:L046=I;890B><<;O107>H4<:1E?8<4N508J24<F180B4h4NC]AQVVNFVZYC]]8;OGWSJTL:2E@=6^;;QCQPd=WAGUIY^GKXc9SMKYE]ZDJAHm4R@OA53YT:VY9=>5\IL]@KIJN[@EESNFJCJ48WJSUKL=0__XNL^C4?VTQIEUI86]\R@68WVTE<2^R\H:l;T2,fimXelgTkh`jr`vlv*pfd`n%o~z}/scnhjiwS9W%~lc!r.q0[lhn|'xja"jr`o-`u4:'xja9m4U1-ahnYjmdUlick}aumq+sgkam$hy| r`ookjv\9T$ym` }/r1\mkos&{kf#i~}al,gt7~5&{kf8n5Z0.`ooZkbeVmnbh|ntnp,rdjnl'ixx!}alnlku]5U'xja#| s2]jjlr)zhg$h}|nm/fs6}4)zhg?o6[?/cnh[hcjWnoeio{os-ueioc&jy~"|nmmmlt^5Z&{kf"!|3^kmmq(uid%o|ob.er1|7(uidk0Y^K]_@NJEVe<]ZOYS[G\ICNF7>PDK01]EHYPTXRF7>QBI:1\IOl4WSKWAZ@NZZ^h7Z\FTD]NKACXIj1\^DZJ_LMGAZD6l2RB@D@W-YFA$5(6(Z^^N->!1!CPGLO13QY_@DL8;YQW[BHCj2RTOB\J_HLEK3=_lkUBhk5Wdi]SvlkQm{ybcc??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmm<>gcl{k#<$64aefqe-7.12koho'11+:?dbczh":=$74aefqe-75!11jhi|n(3+;?dbczh"8%55ndepb,1/?3hno~l&:)99b`atf ?#37ljkr`*4-==flmxj$5'7;`fgvd.>!11jhi|n<1<:?dbczh6:<374aefqe9766k1jhi|n<0094;?<imnym1?=>99b`atf48437ljkr`>1:==flmxj0>07;`fgvd:3611jhi|n<4<;?dbczh6=255ndepb828?3hno~l27>99b`atf40437ljkrc*3-==flmxi$<'6;`fgvg.68 30mij}b)32-<=flmxi$<<&8:cg`wd/: 20mij}b)1*<>gcl{h#8$64aefqf-3.02kohl'6(:8eabuj!="46okds`+<,><imnyn%7&b:cg`wd;9;0;2?m4bmi\i`kXoldTz9Q<,!Zjhlh(JEYI-Ijndpbpjt'9;$?86mck`68gime?2nieyk}r69gmkg/8 =0hd`n(0+4?aoii!8";6jfn`*0-2=cagk#8$94dhlb,0/03mcem%8&7:fjjd.0!01oeco37;2=3>bnfk";%:5kio`+5,1<l`di$?'8;ekmf-5.?2nbbo&;)69gmkd/= =0hd`m(7+4?aoij!="56jfnc>4>58?3me~xl&?)99gkprf 8#37iazt`*1-==cg|~j$>'7;emvpd.3!11ocxzn(4+;?air|h"=%55kotvb,2/?3me~xl2?>99gkprf48437iazt`>1:==cg|~j0>07;emvpd:3611ocxzn<4<;?air|h6=2l5kotvb82<7611ocxzn<6<;?air|k";%55kotva,4/?3me~xo&=)99gkpre :#37iaztc*7-==cg|~i$8'7;emvpg.1!11ocxzm(6+;?air|k6;2l5kotva82<7611nhdh=nff0?`hf;2oeni5fnkg`padn|lxyh6gajdawwgosm{x37cilbtko`f=ulhno~hml(1+`?wbflmxnon&>)e9q`dbczlih$<>&d:pgeabumji#=<'k;sfb`atbkj":>$m4recg`wcdk!8"o6|kaefqafe/; i0~iokdsg`g-2.k2xomij}eba+1,e<zmkohklc)4*g>tcimnyinm'7(a8vagcl{oho%6&c:pgeabumji#5$h4recg`wcdk5;96=09;sgdg`g13{olohl:;smn<n473{ef4f"mlj]nahY`mgU}8R=#NNLF(KIIM:oh7ab8j.ahnYjmdUlicQy4^1/fYoizUyijmjb<2/gZnf{Vxnknkn=1.`[hcjW}s{i0=#c^pppwgjWk7; nQ}supbiZg:8%iT~~zPtxrf9V_IK%iTdl}Piohfgqcuz4:'oR~}il]w}uc:9%iTecg{b^tbh86+kVxnmiQxievk[g;?$jUyiljPwhfwlZg:0%iTy~kPsndwafe:8%iThd}nbmg\sdtiWkb}Snacl<2/gZoia}UmeakPn`of9wij0b$fek"l_vpjp`YjgmoTn0Y]IUG\BLTT\%iT{g{e^ol``Yf5^XBXHQIISQW(fYj}qU{e}kciog\wqg`mz7; nQgar]pkcrbkjUdyy~zt^pfcvYe59&hSeo|_lgn[jssx|~T~hi|_c?3(fYkghnTecg{_gkoa87+kVbjRcjm^mvpussW{olRo20-a\swosmVnn|yfPb<:2=7*dW~xbxhQkeqvk[d;?908'oRfns^pppg;7$jUcm~Q}suc>4)eXagcmRxnl<2/gZnf{Vg~tRaztqww[wc`{Vh6<!mPh`q\ip~Xg|~{yyQ}efq\e86+kVkohoPwhfwl874$jUjhi|m_vkgpm;6;%iTdl}PsndwafeXagz~xR|jgr]b95*dWmommxb{_ecwe86+kVxiRklc<2/gZgkofxbxec21-a\`lufjeoT{l|a_cju[wgiol7; nQxrhvf[roc|aUi15"l_vpjp`Ypam~cSl37,b]qadbXllzdRl280;1(fYeq}oTdtj=8.`[wcflVnn|yfPa<:2=7*dWzcfSnaclhqjkkYd`li`1LBC,b]`khkhfVigg0>#c^ufeZqnl}b6=!mPh`q\akd:8%iTdl}Peoc>5)eXlhT{dj{h<3/gjkwggoexR`nmd?qkh>l$jU~hQmyug\s`d:8%iTy~kPbxvf[rcf59&hS}{_qpjkwosqVh6OH"l_sqw[utng{cuRo2CD.`[pubWmommxb{_ecwe86+u8i0~bc7k^`ooZkbeVmnbRx;_2]{wqY6<2xxxl:4rrva3>uea}oy~<?4tlr,[fa(zfg3g#`ho79tad.7!11|il2?:1<5?rce 9#37zkm<183:xFGx8=:7MNw2529B?2=9rY:<i4=22817?74:mhm?7=?38ym5f1=92d:o549;%3`1?7d92wX==l5231966<6;;nij>4<02;8W4>f2;836=4>33fab6<48:30_<>m:30;>5<6;;nij>4<02c8`75>290:6<u\11f9675=::0:??jmf28046?<~];ji7>51;395=}T99n1>?=5228277ben:08<>74$0`a>4>e3_;h:7<tu0:`>4=r91n1<6s+1`;923=e::31<7?8:2823~N6j01Qj>4={3g9ea<z,8h86?=6;%3`0?7a:2c9>94?::k2ga<72-;jn7?k9:l2ed<732c:on4?:%3bf?7c12d:ml4>;:k2gg<72-;jn7?k9:l2ed<532c:h84?:%3bf?7c12d:ml4<;:k2`1<72-;jn7?k9:l2ed<332c:h>4?:%3bf?7c12d:ml4:;:k2`7<72-;jn7?k9:l2ed<132c:h<4?:%3bf?7c12d:ml48;:k2`5<72-;jn7?k9:l2ed<?32c:ok4?:%3bf?7c12d:ml46;:k2g`<72-;jn7?k9:l2ed<f32c:ol4?:%3bf?7c12d:ml4m;:k2g<<72-;jn7?k9:l2ed<d32e9<k4?:%3bf?46?2d:ml4?;:m14`<72-;jn7<>7:l2ed<632e9<i4?:%3bf?46?2d:ml4=;:m14f<72-;jn7<>7:l2ed<432e9<o4?:%3bf?46?2d:ml4;;:m14d<72-;jn7<>7:l2ed<232e9<44?:%3bf?46?2d:ml49;:m14=<72-;jn7<>7:l2ed<032c:j>4?::`2fd<7280;6=uG1c;8 4d428hj7b?n8;29?xd6<>0;6<4?:1yK5g?<,8h86<:8;n372?6=3thm>7>55486>4>|@8h27Wh<:00x75<4<39>6?k52g8b`?gb2hh1mn4<0;cg>dc=;=0897<j:3d9eg<fk3w/=o=522a8 46?2;9j7)??c;00f>"6i<0:m:5f23594?=h:;n1<7*>ac8173=i9hk1<65`23a94?"6ik09?;5a1`c95>=h:;h1<7*>ac8173=i9hk1>65`22794?"6ik09?;5a1`c97>=h::>1<7*>ac8173=i9hk1865`22194?"6ik09?;5a1`c91>=h::81<7*>ac8173=i9hk1:65`22394?"6ik09?;5a1`c93>=h:::1<7*>ac8173=i9hk1465`23d94?"6ik09?;5a1`c9=>=h:;o1<7*>ac8173=i9hk1m65`23c94?"6ik09?;5a1`c9f>=h:;31<7*>ac8173=i9hk1o65f23694?=n:;?1<75f22594?=n::21<75f25394?"6ik098?5a1`c94>=n:=91<7*>ac8101=i9hk1<65f1bf94?"6ik0:h45a1`c94>=n9ji1<7*>ac82`<=i9hk1=65f1b`94?"6ik0:h45a1`c96>=n9m?1<7*>ac82`<=i9hk1?65f1e694?"6ik0:h45a1`c90>=n9m91<7*>ac82`<=i9hk1965f1e094?"6ik0:h45a1`c92>=n9m;1<7*>ac82`<=i9hk1;65f1e294?"6ik0:h45a1`c9<>=n9jl1<7*>ac82`<=i9hk1565f1bg94?"6ik0:h45a1`c9e>=n9jk1<7*>ac82`<=i9hk1n65f1b;94?"6ik0:h45a1`c9g>=n9l21<7*>ac82b4=i9hk1<65f1d594?"6ik0:j<5a1`c95>=n9l<1<7*>ac82b4=i9hk1>65f1g294?"6ik0:j<5a1`c97>=n9ll1<7*>ac82b4=i9hk1865f1dg94?"6ik0:j<5a1`c91>=n9ln1<7*>ac82b4=i9hk1:65f1da94?"6ik0:j<5a1`c93>=n9lh1<7*>ac82b4=i9hk1465f1dc94?"6ik0:j<5a1`c9=>=n9l31<7*>ac82b4=i9hk1m65f1d794?"6ik0:j<5a1`c9f>=n9l>1<7*>ac82b4=i9hk1o65f22f94?=n::o1<75`22d94?=h:9l1<7*>ac8152=i9hk1<65`21g94?"6ik09=:5a1`c95>=h:9n1<7*>ac8152=i9hk1>65`21a94?"6ik09=:5a1`c97>=h:9h1<7*>ac8152=i9hk1865`21c94?"6ik09=:5a1`c91>=h:931<7*>ac8152=i9hk1:65`21:94?"6ik09=:5a1`c93>=h:;:1<7*>ac8167=i9hk1<65`20d94?"6ik09>?5a1`c95>=h:8o1<7*>ac8167=i9hk1>65`20f94?"6ik09>?5a1`c97>=h:8i1<7*>ac8167=i9hk1865`20`94?"6ik09>?5a1`c91>=h:8k1<7*>ac8167=i9hk1:65`20;94?"6ik09>?5a1`c93>=n9o91<75f1g694?=n9on1<7*>ac82b`=i9hk1<65f1ga94?"6ik0:jh5a1`c95>=n9oh1<7*>ac82b`=i9hk1>65f1gc94?"6ik0:jh5a1`c97>=n9o31<7*>ac82b`=i9hk1865f1g:94?"6ik0:jh5a1`c91>=n9o=1<7*>ac82b`=i9hk1:65f1g494?"6ik0:jh5a1`c93>=n:9<1<7*>ac8142=i9hk1<65f21794?"6ik09<:5a1`c95>=n:9>1<7*>ac8142=i9hk1>65f21194?"6ik09<:5a1`c97>=n:981<7*>ac8142=i9hk1865f21394?"6ik09<:5a1`c91>=n:9:1<7*>ac8142=i9hk1:65f1gd94?"6ik09<:5a1`c93>=n:;<1<75`1g794?=e9j91<7?50;2x 4d428><7E?l2:J2f<=h9=<1<75rb0`4>5<5i3:1<v*>b282ef=O9j80D<l6;[d0>3}5k38o69954987=?2f2t.:o=4>bd9'5d`=92.:8547e:&20<<2:2.:8l495:&20g<6l2.:8n4<;%37`?753-;?i76?;%37b?373-;><7?8;%365??03-;>>7=m;%367?75j2.:994:f:&210<4>2.:9;4>2e9'501=j11/=865899'50?=nj1/=8o5689'50d=99>0(<;l:031?!72l3;27)?:e;5e?!72n3;;?6*>618a7>"6>80:m6*>6380`>"6>:02o6*>65820>"6><0:j6*>678f<>"6>>03>6*>69844>"6>00:96*>6`8b<>"6>k08i6*>6b87g>"6>m0:??5+17g96==#9?l1==<4$053>7?<,8=:64>4$051>f=#9>915?5+166921=#9>?1=>:4$055>4603-;<;7?<a:&23=<6;01/=:75f69'52g=i=1/=:l5f`9'52e=mk1/=:j59:&23`<0j2.:;k4>049'5=6==l1/=5?58e9'5=4=?2.:4>4<1:&2<1<?92.:4847;%3;2?1?3-;3;7?9;%3b`?c03-;347?4$0::>4=#9kl1=ok4$0`3>4=n9931<75f11c94?=n9::1<75f12394?=n9k;1<75f1c094?=n9ki1<75f1cf94?=nkm0;6)?nb;a`?k7fi3:07dmm:18'5dd=kj1e=lo51:9jgd<72-;jn7ml;o3be?4<3`n=6=4+1``9gf=i9hk1?65fd483>!7fj3ih7c?na;68?lb3290/=ll5cb9m5dg==21bh>4?:%3bf?ed3g;jm784;hf1>5<#9hh1on5a1`c93>=nl80;6)?nb;a`?k7fi3207dj?:18'5dd=kj1e=lo59:9jgc<72-;jn7ml;o3be?g<3`in6=4+1``9gf=i9hk1n65fc883>!7fj3ih7c?na;a8?lbe290/=ll5d`9m5dg=821bh44?:%3bf?bf3g;jm7?4;hf;>5<#9hh1hl5a1`c96>=nm=0;6)?nb;fb?k7fi3907dk<:18'5dd=lh1e=lo54:9ja7<72-;jn7jn;o3be?3<3`o:6=4+1``9`d=i9hk1:65fe183>!7fj3nj7c?na;58?lba290/=ll5d`9m5dg=021bhh4?:%3bf?bf3g;jm774;hfg>5<#9hh1hl5a1`c9e>=nlj0;6)?nb;fb?k7fi3h07dj8:18'5dd=lh1e=lo5c:9j54g=83.:mo4>189m5dg=821b=<650;&2eg<6901e=lo51:9j54b=83.:mo4>1b9m5dg=821b=<l50;&2eg<69j1e=lo51:9l576=83.:mo4>1g9m5dg=821d=<k50;&2eg<69o1e=lo51:9l575=83.:mo4>239m5dg=821d=??50;&2eg<6:;1e=lo51:9~f4d12909m7>50z&2f6<6ij1C=n<4H0`:?_`42?q9o7<k:5590=<313>j6p*>c182f`=#9hl1=6*>498:`>"6<00m=6*>4`863>"6<k0h<6*>4b8f1>"6<m0h96*>4d8`7>"6<o0ii6*>51815>"6=80=<6*>53865>"6=:0>56*>558a0>"6=<0i7)?:6;62?!72?3;8h6*>598;1>"6=00n7)?:a;33b>"6=k0m86*>5b853>"6=m0?n6*>5d8e`>"6=o0:o6*>618245=#9?;1=55+170954=#9?91895+17697<=#9??18=5+174932=#9?=1>;5+17:9b0=#9?31>85+17c955c<,8<i68=4$04`>02<,8<o6k64$04f>=2<,8<m6>64$053>gg<,8=:6;m4$051>g1<,8=86n:4$057>71<,8=>6k74$055>2c<,8=<6?<4$05;>4273-;<57j4$05b>4713-;<n79>;%34g?ga3-;<h776;%34a?7512.:;k4l2:&2<5<>92.:4<4>159'5=4==2.:4>4:5:&2<1<2l2.:484n;%3;2?2a3-;3;7=<;%3b`?c03-;347?4$0::>4=#9kl1=ok4$0`3>4=n9931<75f11c94?=n9::1<75f12394?=n9k;1<75f1c094?=n9ki1<75f1cf94?=nkm0;6)?nb;a`?k7fi3:07dmm:18'5dd=kj1e=lo51:9jgd<72-;jn7ml;o3be?4<3`n=6=4+1``9gf=i9hk1?65fd483>!7fj3ih7c?na;68?lb3290/=ll5cb9m5dg==21bh>4?:%3bf?ed3g;jm784;hf1>5<#9hh1on5a1`c93>=nl80;6)?nb;a`?k7fi3207dj?:18'5dd=kj1e=lo59:9jgc<72-;jn7ml;o3be?g<3`in6=4+1``9gf=i9hk1n65fc883>!7fj3ih7c?na;a8?lbe290/=ll5d`9m5dg=821bh44?:%3bf?bf3g;jm7?4;hf;>5<#9hh1hl5a1`c96>=nm=0;6)?nb;fb?k7fi3907dk<:18'5dd=lh1e=lo54:9ja7<72-;jn7jn;o3be?3<3`o:6=4+1``9`d=i9hk1:65fe183>!7fj3nj7c?na;58?lba290/=ll5d`9m5dg=021bhh4?:%3bf?bf3g;jm774;hfg>5<#9hh1hl5a1`c9e>=nlj0;6)?nb;fb?k7fi3h07dj8:18'5dd=lh1e=lo5c:9j54g=83.:mo4>189m5dg=821b=<650;&2eg<6901e=lo51:9j54b=83.:mo4>1b9m5dg=821b=<l50;&2eg<69j1e=lo51:9l576=83.:mo4>1g9m5dg=821d=<k50;&2eg<69o1e=lo51:9l575=83.:mo4>239m5dg=821d=??50;&2eg<6:;1e=lo51:9~f4d22909m7>50z&2f6<6ij1C=n<4H0`:?_`42?q9o7<k:5590=<313>j6p*>c182f`=#9hl1=6*>49826==#9=31j=5+15c956`<,8>i6l>4$06`>1b<,8>o6<=4$06f><`<,8>m6oj4$073>2g<,8?:6<=:;%366?5f3-;>?7m7;%360?g63-;>979:;%362?d23-;>;7::;%36<?153-;>57?m;%36e?g03-;>n7?<8:&21f<5<2.:9i49d:&21`<f>2.:9k4>2b9'536=98:0(<8>:878 4052k<0(<8<:d;8 4032oh0(<8::066?!71>3;?=6*>668;3>"6>102?6*>688be>"6>h0=i6*>6c84=>"6>j03m6*>6e8;g>"6>l09m6*>6g8243=#9>:15h5+1639=1=#9>81m45+16193f=#9>>18?5+167955=#9><14;5+1659ac=#9>21=>l4$05:>2b<,8=j6<<8;%34f?73<2.:;n466:&23a<2i2.:;h4>379'52`=>11/=5>5bc9'5=7==11/=5<56:&2<6<2>2.:494:c:&2<0<d>2.:4;479:&2<2<2j2.:mi4j7:&2<=<63-;357?4$0`e>4db3-;i<7?4i02:>5<<a8:j6=44i013>5<<a89:6=44i0`2>5<<a8h96=44i0``>5<<a8ho6=44ibf94?"6ik0ho6`>a`83?>odj3:1(<om:ba8j4gf2810eno50;&2eg<dk2d:ml4=;:kg2?6=,8ki6nm4n0cb>6=<am?1<7*>ac8`g>h6ih0?76gk4;29 4ge2ji0b<on:498ma5=83.:mo4lc:l2ed<132co>7>5$0ca>fe<f8kj6:54ie394?"6ik0ho6`>a`8;?>oc83:1(<om:ba8j4gf2010enh50;&2eg<dk2d:ml4n;:k`a?6=,8ki6nm4n0cb>g=<aj31<7*>ac8`g>h6ih0h76gkb;29 4ge2mk0b<on:198ma?=83.:mo4ka:l2ed<632co47>5$0ca>ag<f8kj6?54id694?"6ik0om6`>a`80?>ob;3:1(<om:ec8j4gf2=10eh<50;&2eg<ci2d:ml4:;:kf5?6=,8ki6io4n0cb>3=<al:1<7*>ac8ge>h6ih0<76gkf;29 4ge2mk0b<on:998mac=83.:mo4ka:l2ed<>32coh7>5$0ca>ag<f8kj6l54iea94?"6ik0om6`>a`8a?>oc?3:1(<om:ec8j4gf2j10e<?n:18'5dd=9830b<on:198m47?290/=ll510;8j4gf2810e<?k:18'5dd=98i0b<on:198m47e290/=ll510a8j4gf2810c<<?:18'5dd=98l0b<on:198k47b290/=ll510d8j4gf2810c<<<:18'5dd=9;80b<on:198k446290/=ll51308j4gf2810qo?m4;296d<729q/=o=51`a8L4e53A;i56Ti3;4x6f<5l3><69654887e?{#9j:1=ok4$0ce>4=#9=21=9=4$06:>`b<,8>j65l4$06a>61<,8>h6ho4$06g>f1<,8>n6h84$06e>g7<,8?;6kh4$072>37<,8?96n?4$070>25<,8??6<?>;%361?`b3-;>:76i;%363?75m2.:954>369'50?=9:90(<;n:708 43e2o<0(<;l:036?!72l3==7)?:e;;b?!72n33i7)?90;3f?!71938;7)?92;11?!71;3h97)?94;310>"6><0:>85+1749f5=#9?=1:l5+17:9a`=#9?31==?4$04b>3`<,8<i6984$04`>1c<,8<o6oh4$04f>44a3-;=j777;%344?g43-;<=7?>3:&237<bk2.:;>4m9:&231<f:2.:;8473:&233<6;l1/=:951508 41?288j7)?89;312>"6?h0io6*>7c827f=#9>i1=<94$05g>22<,8=n6;=4$05e>3d<,82;6l;4$0:2>6e<,829695+19197c=#91>18>5+1979b>"60?097)?77;0a?!7fl3o<7)?78;38 4>>281/=oh51cg8 4d7281b==750;9j55g=831b=>>50;9j567=831b=o?50;9j5g4=831b=om50;9j5gb=831boi4?:%3bf?ed3g;jm7>4;haa>5<#9hh1on5a1`c95>=nkh0;6)?nb;a`?k7fi3807dj9:18'5dd=kj1e=lo53:9j`0<72-;jn7ml;o3be?2<3`n?6=4+1``9gf=i9hk1965fd283>!7fj3ih7c?na;48?lb5290/=ll5cb9m5dg=?21bh<4?:%3bf?ed3g;jm764;hf3>5<#9hh1on5a1`c9=>=nko0;6)?nb;a`?k7fi3k07dmj:18'5dd=kj1e=lo5b:9jg<<72-;jn7ml;o3be?e<3`ni6=4+1``9`d=i9hk1<65fd883>!7fj3nj7c?na;38?lb?290/=ll5d`9m5dg=:21bi94?:%3bf?bf3g;jm7=4;hg0>5<#9hh1hl5a1`c90>=nm;0;6)?nb;fb?k7fi3?07dk>:18'5dd=lh1e=lo56:9ja5<72-;jn7jn;o3be?1<3`nm6=4+1``9`d=i9hk1465fdd83>!7fj3nj7c?na;;8?lbc290/=ll5d`9m5dg=i21bhn4?:%3bf?bf3g;jm7l4;hf4>5<#9hh1hl5a1`c9g>=n98k1<7*>ac825<=i9hk1<65f10:94?"6ik0:=45a1`c95>=n98n1<7*>ac825f=i9hk1<65f10`94?"6ik0:=n5a1`c95>=h9;:1<7*>ac825c=i9hk1<65`10g94?"6ik0:=k5a1`c95>=h9;91<7*>ac8267=i9hk1<65`13394?"6ik0:>?5a1`c95>=z{;8:6=484z\2b0=Y::l0R?<k;_01g>X5:k1U>>;4^317?[44;2T9??5Q2238Z7573W89j6P=2d9]67g<V;827S<=0:\15c=Y:8o0R??k;_02g>X59k1U><o4^33:?87d;3;?:63>b6824d=:9k=1=>?4=0`4>4d634;i;7?m2:?2f2<6jj16=o951cf894d02mh01<l8:e;894d02m201<l8:d6894d02l901<l8:d0894d02l;01<l8:d2894d02ml01<l8:eg894d02mn01<l8:ea894d02m=01<l8:03b?87e?3;:463>b6825a=:9k=1=<l4=0`5>46f34;i:7?<1:?2f3<6j816=o851c0894d128hh70?m6;3a`>;6j?0on63>b78g=>;6j?0o463>b78f0>;6j?0n?63>b78f6>;6j?0n=63>b78f4>;6j?0oj63>b78ga>;6j?0oh63>b78gg>;6j?0o;63>b7825d=:9k<1=<64=0`5>47c34;i:7?>b:?2f0<68h16=o;5123894d228h:70?m5;3a6>;6j<0:nn521c795gb<58h>6il4=0`6>a?<58h>6i64=0`6>`2<58h>6h=4=0`6>`4<58h>6h?4=0`6>`6<58h>6ih4=0`6>ac<58h>6ij4=0`6>ae<58h>6i94=0`6>47f34;i97?>8:?2f0<69m16=o;510`894d328:j70?m4;305>;6j=0:n<521c695g4<58h?6<ll;<3a0?7el27:n94kb:?2f1<c127:n94k8:?2f1<b<27:n94j3:?2f1<b:27:n94j1:?2f1<b827:n94kf:?2f1<cm27:n94kd:?2f1<ck27:n94k7:?2f1<69h16=o:510:894d328;o70?m4;32f>{t:;>1<7;t^307?87e?3;8<63>b78275=:9k?1=>>4=0`7>4573ty:j>4?:4y]5c5<58h<6<>6;<3a2?77127:n84>089>5g2=9930q~<>8;296~X58o16=o951328yv46>3:1>vP=0d9>5g1=98o0q~<>5;296~X58m16=o851328yv46<3:1>vP=0b9>5g0=98o0q~<>3;296~X58k16=o;51328yv46:3:1>vP=0`9>5g3=98o0q~<>1;296~X58016=o:51328yv4683:1>vP=099>5g2=98o0q~?ka;291~X6km16=o95ce9>5g0=km16=o;5ce9>5g2=km1v<j7:186[7dk27:n:4lb:?2f3<dj27:n84lb:?2f1<dj2wx=i950;7xZ4ee34;i;7mn;<3a2?ef34;i97mn;<3a0?ef3ty:i>4?:4y]5a3<58h<6i84=0`5>a0<58h>6i84=0`7>a0<uz;n>7>55z\2`1=:9k=1h8521c49`0=:9k?1h8521c69`0=z{8o:6=4:{_3g7>;6j>0o863>b78g0>;6j<0o863>b58g0>{t9l:1<7;t^0f1?87e?3n870?m6;f0?87e=3n870?m4;f0?xu6lo0;68uQ1e3894d02m801<l9:e0894d22m801<l;:e08yv7cm3:19vP>d19>5g1=l816=o85d09>5g3=l816=o:5d09~w4bc290>wS?lf:?2f2<c827:n;4k0:?2f0<c827:n94k0:p5ae=83?pR<mj;<3a3?ea34;i:7mi;<3a1?ea34;i87mi;|q2`g<72<qU=no4=0`4>fc<58h=6nk4=0`6>fc<58h?6nk4}r3g2?6==rT:o4521c59g<=:9k<1o4521c79g<=:9k>1o45r}r3e7?6=:rT:j>52f382b6=#9k21=464}r010?6=:rT9>952f38161=#9k21=l?4}r3ge?6=:rT:oi52f382ga=#9k21=l<4}r3g<?6=:rT:on52f382gf=#9k21=l=4}r3g3?6=:rT:oo52f382gg=#9k21=l:4}r3f7?6=:rT:h852f382`0=#9k21=5k4}r3f6?6=:rT:h952f382`1=#9k21=5h4}r3f5?6=:rT:h>52f382`6=#9k21=4>4}r3f4?6=:rT:h?52f382`7=#9k21=4?4}r3gb?6=:rT:h<52f382`4=#9k21=4<4}r3ga?6=:rT:h=52f382`5=#9k21=4=4}r3g`?6=:rT:ok52f382gc=#9k21=4:4}r3gg?6=:rT:oh52f382g`=#9k21=4;4}r3gf?6=:rT:ol52f382gd=#9k21=484}r3g2?6=:rT:o452f382g<=#9k21=494}r02<?6=:rT9<k52f3814c=#9k21=474}r022?6=:rT9<h52f3814`=#9k21=4o4}r021?6=:rT9<i52f3814a=#9k21=4l4}r020?6=:rT9<n52f3814f=#9k21=4m4}r027?6=:rT9<o52f3814g=#9k21=4j4}r026?6=:rT9<l52f3814d=#9k21=4k4}r025?6=:rT9<452f3814<=#9k21=4h4}r024?6=:rT9<552f3814==#9k21=l>4}|l207<72;qC=o74}o377?6=:rB:n45rn067>5<5sA;i56sa15794?4|@8h27p`>4783>7}O9k30qc?;7;296~N6j01vb<:7:181M7e12we=9750;0xL4d>3td:8l4?:3yK5g?<ug;?n7>52zJ2f<=zf8>h6=4={I3a=>{i9=n1<7<tH0`:?xh6<l0;6?uG1c;8yk73n3:1>vF>b89~j4372909wE?m9:m507=838pD<l6;|l217<72;qC=o74}o367?6=:rB:n45rn077>5<5sA;i56sa14794?4|@8h27p`>5783>7}O9k30qc?:7;296~N6j01vb<;7:181M7e12we=?o50;3xL4d>3twvqMNL{052>cb1k12j?pNOBz2~DEV|uIJ
\ No newline at end of file
diff --git a/cores/JupiterAce/rom8k.sym b/cores/JupiterAce/rom8k.sym
deleted file mode 100644
index 3485010..0000000
--- a/cores/JupiterAce/rom8k.sym
+++ /dev/null
@@ -1,21 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="rom8k">
-    <symboltype>BLOCK</symboltype>
-    <timestamp>2011-3-23T1:22:54</timestamp>
-    <pin polarity="Input" x="0" y="80" name="addra[12:0]" />
-    <pin polarity="Input" x="0" y="144" name="ena" />
-    <pin polarity="Input" x="0" y="272" name="clka" />
-    <pin polarity="Output" x="576" y="80" name="douta[7:0]" />
-    <graph>
-        <text style="fontsize:40;fontname:Arial" x="32" y="32">rom8k</text>
-        <rect width="512" x="32" y="32" height="640" />
-        <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[12:0]" />
-        <line x2="32" y1="144" y2="144" x1="0" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
-        <line x2="32" y1="272" y2="272" x1="0" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
-        <line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
-        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
-    </graph>
-</symbol>
diff --git a/cores/JupiterAce/rom8k.v b/cores/JupiterAce/rom8k.v
deleted file mode 100644
index 058068b..0000000
--- a/cores/JupiterAce/rom8k.v
+++ /dev/null
@@ -1,158 +0,0 @@
-/*******************************************************************************
-*     (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved.              *
-*                                                                              *
-*     This file contains confidential and proprietary information              *
-*     of Xilinx, Inc. and is protected under U.S. and                          *
-*     international copyright and other intellectual property                  *
-*     laws.                                                                    *
-*                                                                              *
-*     DISCLAIMER                                                               *
-*     This disclaimer is not a license and does not grant any                  *
-*     rights to the materials distributed herewith. Except as                  *
-*     otherwise provided in a valid license issued to you by                   *
-*     Xilinx, and to the maximum extent permitted by applicable                *
-*     law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND                  *
-*     WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES              *
-*     AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING                *
-*     BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-                   *
-*     INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and                 *
-*     (2) Xilinx shall not be liable (whether in contract or tort,             *
-*     including negligence, or under any other theory of                       *
-*     liability) for any loss or damage of any kind or nature                  *
-*     related to, arising under or in connection with these                    *
-*     materials, including for any direct, or any indirect,                    *
-*     special, incidental, or consequential loss or damage                     *
-*     (including loss of data, profits, goodwill, or any type of               *
-*     loss or damage suffered as a result of any action brought                *
-*     by a third party) even if such damage or loss was                        *
-*     reasonably foreseeable or Xilinx had been advised of the                 *
-*     possibility of the same.                                                 *
-*                                                                              *
-*     CRITICAL APPLICATIONS                                                    *
-*     Xilinx products are not designed or intended to be fail-                 *
-*     safe, or for use in any application requiring fail-safe                  *
-*     performance, such as life-support or safety devices or                   *
-*     systems, Class III medical devices, nuclear facilities,                  *
-*     applications related to the deployment of airbags, or any                *
-*     other applications that could lead to death, personal                    *
-*     injury, or severe property or environmental damage                       *
-*     (individually and collectively, "Critical                                *
-*     Applications"). Customer assumes the sole risk and                       *
-*     liability of any use of Xilinx products in Critical                      *
-*     Applications, subject only to applicable laws and                        *
-*     regulations governing limitations on product liability.                  *
-*                                                                              *
-*     THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS                 *
-*     PART OF THIS FILE AT ALL TIMES.                                          *
-*******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file rom8k.v when simulating
-// the core, rom8k. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module rom8k(
-	clka,
-	ena,
-	addra,
-	douta);
-
-
-input clka;
-input ena;
-input [12 : 0] addra;
-output [7 : 0] douta;
-
-// synthesis translate_off
-
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(13),
-		.C_ADDRB_WIDTH(13),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(0),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan6"),
-		.C_HAS_ENA(1),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("rom8k.mif"),
-		.C_LOAD_INIT_FILE(1),
-		.C_MEM_TYPE(3),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(8192),
-		.C_READ_DEPTH_B(8192),
-		.C_READ_WIDTH_A(8),
-		.C_READ_WIDTH_B(8),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(8192),
-		.C_WRITE_DEPTH_B(8192),
-		.C_WRITE_MODE_A("WRITE_FIRST"),
-		.C_WRITE_MODE_B("WRITE_FIRST"),
-		.C_WRITE_WIDTH_A(8),
-		.C_WRITE_WIDTH_B(8),
-		.C_XDEVICEFAMILY("spartan6"))
-	inst (
-		.CLKA(clka),
-		.ENA(ena),
-		.ADDRA(addra),
-		.DOUTA(douta),
-		.RSTA(),
-		.REGCEA(),
-		.WEA(),
-		.DINA(),
-		.CLKB(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.ADDRB(),
-		.DINB(),
-		.DOUTB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
-
-// synthesis translate_on
-
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of rom8k is "black_box"
-
-endmodule
-
diff --git a/cores/JupiterAce/rom8k.veo b/cores/JupiterAce/rom8k.veo
deleted file mode 100644
index a807a73..0000000
--- a/cores/JupiterAce/rom8k.veo
+++ /dev/null
@@ -1,65 +0,0 @@
-/*******************************************************************************
-*     (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved.              *
-*                                                                              *
-*     This file contains confidential and proprietary information              *
-*     of Xilinx, Inc. and is protected under U.S. and                          *
-*     international copyright and other intellectual property                  *
-*     laws.                                                                    *
-*                                                                              *
-*     DISCLAIMER                                                               *
-*     This disclaimer is not a license and does not grant any                  *
-*     rights to the materials distributed herewith. Except as                  *
-*     otherwise provided in a valid license issued to you by                   *
-*     Xilinx, and to the maximum extent permitted by applicable                *
-*     law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND                  *
-*     WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES              *
-*     AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING                *
-*     BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-                   *
-*     INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and                 *
-*     (2) Xilinx shall not be liable (whether in contract or tort,             *
-*     including negligence, or under any other theory of                       *
-*     liability) for any loss or damage of any kind or nature                  *
-*     related to, arising under or in connection with these                    *
-*     materials, including for any direct, or any indirect,                    *
-*     special, incidental, or consequential loss or damage                     *
-*     (including loss of data, profits, goodwill, or any type of               *
-*     loss or damage suffered as a result of any action brought                *
-*     by a third party) even if such damage or loss was                        *
-*     reasonably foreseeable or Xilinx had been advised of the                 *
-*     possibility of the same.                                                 *
-*                                                                              *
-*     CRITICAL APPLICATIONS                                                    *
-*     Xilinx products are not designed or intended to be fail-                 *
-*     safe, or for use in any application requiring fail-safe                  *
-*     performance, such as life-support or safety devices or                   *
-*     systems, Class III medical devices, nuclear facilities,                  *
-*     applications related to the deployment of airbags, or any                *
-*     other applications that could lead to death, personal                    *
-*     injury, or severe property or environmental damage                       *
-*     (individually and collectively, "Critical                                *
-*     Applications"). Customer assumes the sole risk and                       *
-*     liability of any use of Xilinx products in Critical                      *
-*     Applications, subject only to applicable laws and                        *
-*     regulations governing limitations on product liability.                  *
-*                                                                              *
-*     THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS                 *
-*     PART OF THIS FILE AT ALL TIMES.                                          *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-rom8k YourInstanceName (
-	.clka(clka),
-	.ena(ena),
-	.addra(addra), // Bus [12 : 0] 
-	.douta(douta)); // Bus [7 : 0] 
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file rom8k.v when simulating
-// the core, rom8k. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
diff --git a/cores/JupiterAce/rom8k.xco b/cores/JupiterAce/rom8k.xco
deleted file mode 100644
index 710aa0d..0000000
--- a/cores/JupiterAce/rom8k.xco
+++ /dev/null
@@ -1,93 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.4
-# Date: Wed Mar 23 01:23:52 2011
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s500e
-SET devicefamily = spartan3e
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg320
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET additional_inputs_for_power_estimation=false
-CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
-CSET byte_size=9
-CSET coe_file=.\rom_jace.coe
-CSET collision_warnings=ALL
-CSET component_name=rom8k
-CSET disable_collision_warnings=false
-CSET disable_out_of_range_warnings=false
-CSET ecc=false
-CSET ecctype=No_ECC
-CSET enable_a=Use_ENA_Pin
-CSET enable_b=Always_Enabled
-CSET error_injection_type=Single_Bit_Error_Injection
-CSET fill_remaining_memory_locations=false
-CSET load_init_file=true
-CSET memory_type=Single_Port_ROM
-CSET operating_mode_a=WRITE_FIRST
-CSET operating_mode_b=WRITE_FIRST
-CSET output_reset_value_a=0
-CSET output_reset_value_b=0
-CSET pipeline_stages=0
-CSET port_a_clock=100
-CSET port_a_enable_rate=100
-CSET port_a_write_rate=0
-CSET port_b_clock=0
-CSET port_b_enable_rate=0
-CSET port_b_write_rate=0
-CSET primitive=8kx2
-CSET read_width_a=8
-CSET read_width_b=8
-CSET register_porta_input_of_softecc=false
-CSET register_porta_output_of_memory_core=false
-CSET register_porta_output_of_memory_primitives=false
-CSET register_portb_output_of_memory_core=false
-CSET register_portb_output_of_memory_primitives=false
-CSET register_portb_output_of_softecc=false
-CSET remaining_memory_locations=0
-CSET reset_memory_latch_a=false
-CSET reset_memory_latch_b=false
-CSET reset_priority_a=CE
-CSET reset_priority_b=CE
-CSET reset_type=SYNC
-CSET softecc=false
-CSET use_byte_write_enable=false
-CSET use_error_injection_pins=false
-CSET use_regcea_pin=false
-CSET use_regceb_pin=false
-CSET use_rsta_pin=false
-CSET use_rstb_pin=false
-CSET write_depth_a=8192
-CSET write_width_a=8
-CSET write_width_b=8
-# END Parameters
-GENERATE
-# CRC: f60395b6
diff --git a/cores/JupiterAce/rom8k.xise b/cores/JupiterAce/rom8k.xise
deleted file mode 100644
index c07c4b1..0000000
--- a/cores/JupiterAce/rom8k.xise
+++ /dev/null
@@ -1,368 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="rom8k.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="rom8k.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Module|rom8k" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="rom8k.ngc" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/rom8k" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="rom8k" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="rom8k_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="rom8k_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="rom8k_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="rom8k_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="rom8k" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-23T02:23:57" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FB5288D369F04B859B807E0D8D321ED9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/cores/JupiterAce/rom8k_flist.txt b/cores/JupiterAce/rom8k_flist.txt
deleted file mode 100644
index 44fb91a..0000000
--- a/cores/JupiterAce/rom8k_flist.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-# Output products list for <rom8k>
-_xmsgs\pn_parser.xmsgs
-blk_mem_gen_ds512.pdf
-blk_mem_gen_readme.txt
-rom8k.asy
-rom8k.gise
-rom8k.mif
-rom8k.ngc
-rom8k.sym
-rom8k.v
-rom8k.veo
-rom8k.xco
-rom8k.xise
-rom8k_flist.txt
-rom8k_xmdf.tcl
diff --git a/cores/JupiterAce/rom8k_xmdf.tcl b/cores/JupiterAce/rom8k_xmdf.tcl
deleted file mode 100644
index 180f9c9..0000000
--- a/cores/JupiterAce/rom8k_xmdf.tcl
+++ /dev/null
@@ -1,84 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide rom8k_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::rom8k_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::rom8k_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name rom8k
-}
-# ::rom8k_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::rom8k_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.mif
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.sym
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom8k
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/cores/MasterSystem/src/sms.vhd b/cores/MasterSystem/src/sms.vhd
index 0785317..9c4f44c 100644
--- a/cores/MasterSystem/src/sms.vhd
+++ b/cores/MasterSystem/src/sms.vhd
@@ -6,8 +6,8 @@ entity sms is
 	port (
 		clk:			in			STD_LOGIC;
 		
-		ram_we_n:	out		STD_LOGIC;
-		ram_a:		out		STD_LOGIC_VECTOR(18 downto 0);
+		sram_we_n:	out		STD_LOGIC;
+		sram_a:		out		STD_LOGIC_VECTOR(18 downto 0);
 		ram_d:		inout		STD_LOGIC_VECTOR(7 downto 0); --Q
 
 --		j1_MDsel:	out		STD_LOGIC; --Q
@@ -171,13 +171,18 @@ architecture Behavioral of sms is
 	
 	signal rgb_clk:		std_logic;
 	
---	signal scanDB:			std_logic;
+	signal scanSWk:		std_logic;
 	signal scanSW:			std_logic;
 	
 	signal j2_tr:			std_logic;
 	
 	signal c0, c1, c2 : 	std_logic_vector(9 downto 0);	--hdmi
 	
+	signal poweron_reset:	unsigned(7 downto 0) := "00000000";
+	signal scandoubler_ctrl: std_logic_vector(1 downto 0);
+	signal ram_we_n: std_logic;
+	signal ram_a:	std_logic_vector(18 downto 0);
+	
 begin
 
 	clock_inst: clock
@@ -257,7 +262,7 @@ begin
 		ps2_clk		=> ps2_clk,
 		ps2_data		=> ps2_data,
 		
-		scanSW		=> scanSW,
+		scanSW		=> scanSWk,
 
 		spi_do		=> spi_do,
 		spi_sclk		=> spi_sclk,
@@ -266,6 +271,7 @@ begin
 		);
 	
 	led <= not spi_cs_n; --Q
+--	led <= scandoubler_ctrl(0); --debug scandblctrl reg.
 
 	audio_l <= audio;
 	audio_r <= audio;
@@ -273,6 +279,25 @@ begin
 	NTSC <= '0';
 	PAL <= '1';	
 	
+	---- scandlbctrl register detection for video mode initialization at start ----
+	
+	process (clk_cpu)
+	begin
+		if rising_edge(clk_cpu) then
+        if (poweron_reset < 126) then
+            scandoubler_ctrl <= ram_d(1 downto 0);
+		  end if;
+		  if poweron_reset < 254 then
+				poweron_reset <= poweron_reset + 1;
+		  end if;
+		end if;
+	end process;
+	
+
+	sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
+	sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
+	
+	-------------------------------------------------------------------------------
 	
 	vsync <= vga_vsync when scanSW='1'	else '1';
 	hsync <= vga_hsync when scanSW='1' 	else rgb_hsync;
@@ -286,8 +311,10 @@ begin
 	x <= vga_x when scanSW='1'	else rgb_x;
 	y <= vga_y when scanSW='1'	else rgb_y;	
 	
---	sel_pclock <= '1' when scanDB='1' else '0';
 	sel_pclock <= '1' when scanSW='1' else '0';
+	
+--	scanSW <= '1' when scanSWk = '1' else '0';
+	scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
 
 
 --HDMI
diff --git a/cores/MasterSystem/src/sms_zxuno_Ap.ucf b/cores/MasterSystem/src/sms_zxuno_Ap.ucf
index c748d03..ae35176 100644
--- a/cores/MasterSystem/src/sms_zxuno_Ap.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_Ap.ucf
@@ -29,25 +29,25 @@ NET "ps2_data"        LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 # SRAM  
-NET ram_a(0)          LOC="P115" | IOSTANDARD = LVCMOS33;
-NET ram_a(1)          LOC="P116" | IOSTANDARD = LVCMOS33;
-NET ram_a(2)          LOC="P117" | IOSTANDARD = LVCMOS33;
-NET ram_a(3)          LOC="P119" | IOSTANDARD = LVCMOS33;
-NET ram_a(4)          LOC="P120" | IOSTANDARD = LVCMOS33;
-NET ram_a(5)          LOC="P123" | IOSTANDARD = LVCMOS33;
-NET ram_a(6)          LOC="P126" | IOSTANDARD = LVCMOS33;
-NET ram_a(7)          LOC="P131" | IOSTANDARD = LVCMOS33;
-NET ram_a(8)          LOC="P127" | IOSTANDARD = LVCMOS33;
-NET ram_a(9)          LOC="P124" | IOSTANDARD = LVCMOS33;
-NET ram_a(10)         LOC="P118" | IOSTANDARD = LVCMOS33;
-NET ram_a(11)         LOC="P121" | IOSTANDARD = LVCMOS33;
-NET ram_a(12)         LOC="P133" | IOSTANDARD = LVCMOS33;
-NET ram_a(13)         LOC="P132" | IOSTANDARD = LVCMOS33;
-NET ram_a(14)         LOC="P137" | IOSTANDARD = LVCMOS33;
-NET ram_a(15)         LOC="P140" | IOSTANDARD = LVCMOS33;
-NET ram_a(16)         LOC="P139" | IOSTANDARD = LVCMOS33;
-NET ram_a(17)         LOC="P141" | IOSTANDARD = LVCMOS33;
-NET ram_a(18)         LOC="P138" | IOSTANDARD = LVCMOS33;
+NET sram_a(0)         LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(1)         LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(2)         LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(3)         LOC="P119" | IOSTANDARD = LVCMOS33;
+NET sram_a(4)         LOC="P120" | IOSTANDARD = LVCMOS33;
+NET sram_a(5)         LOC="P123" | IOSTANDARD = LVCMOS33;
+NET sram_a(6)         LOC="P126" | IOSTANDARD = LVCMOS33;
+NET sram_a(7)         LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(8)         LOC="P127" | IOSTANDARD = LVCMOS33;
+NET sram_a(9)         LOC="P124" | IOSTANDARD = LVCMOS33;
+NET sram_a(10)        LOC="P118" | IOSTANDARD = LVCMOS33;
+NET sram_a(11)        LOC="P121" | IOSTANDARD = LVCMOS33;
+NET sram_a(12)        LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(13)        LOC="P132" | IOSTANDARD = LVCMOS33;
+NET sram_a(14)        LOC="P137" | IOSTANDARD = LVCMOS33;
+NET sram_a(15)        LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(16)        LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(17)        LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(18)        LOC="P138" | IOSTANDARD = LVCMOS33;
 
 
 
@@ -60,7 +60,7 @@ NET ram_d(5)          LOC="P102" | IOSTANDARD = LVCMOS33;
 NET ram_d(6)          LOC="P101" | IOSTANDARD = LVCMOS33;
 NET ram_d(7)          LOC="P100" | IOSTANDARD = LVCMOS33;
 
-NET ram_WE_n          LOC="P134" | IOSTANDARD = LVCMOS33;
+NET sram_WE_n         LOC="P134" | IOSTANDARD = LVCMOS33;
 
 
 
diff --git a/cores/MasterSystem/src/sms_zxuno_v2.ucf b/cores/MasterSystem/src/sms_zxuno_v2.ucf
index 9aa7ab6..e153c27 100644
--- a/cores/MasterSystem/src/sms_zxuno_v2.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v2.ucf
@@ -1,84 +1,97 @@
 #UCF para el ZX-UNO v2
+NET "CLK"             LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
+NET "led"             LOC="P10"  | IOSTANDARD = LVCMOS33;
 
-NET "CLK"	 			PERIOD=20 ns;
-NET "CLK"      		LOC="P55"  | IOSTANDARD=LVCMOS33;
+# Video output
+NET "red(2)"          LOC="P93"  | IOSTANDARD = LVCMOS33;                              
+NET "red(1)"          LOC="P92"  | IOSTANDARD = LVCMOS33;                                
+NET "red(0)"          LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "green(2)"        LOC="P84"  | IOSTANDARD = LVCMOS33;                               
+NET "green(1)"        LOC="P83"  | IOSTANDARD = LVCMOS33;                                
+NET "green(0)"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "blue(2)"         LOC="P81"  | IOSTANDARD = LVCMOS33;                                
+NET "blue(1)"         LOC="P80"  | IOSTANDARD = LVCMOS33;                                
+NET "blue(0)"         LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET NTSC              LOC="P66"  | IOSTANDARD = LVCMOS33;
+NET PAL               LOC="P67"  | IOSTANDARD = LVCMOS33;
 
-NET "led"			LOC="P10"  | IOSTANDARD=LVCMOS33;
+# Sound input/output
+NET "audio_l"         LOC="P8"   | IOSTANDARD = LVCMOS33;                               
+NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;                               
 
-NET "j1_tr"			LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_tl"			LOC="P6"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_right"		LOC="P5"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_left"		LOC="P2"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_down"		LOC="P1"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_up"			LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
 
-NET "vsync"			LOC="P85"  | IOSTANDARD=LVCMOS33;                                
-NET "hsync"			LOC="P87"  | IOSTANDARD=LVCMOS33;                                
-
-NET "green(0)"		LOC="P82"  | IOSTANDARD=LVCMOS33;                                
-NET "red(0)"		LOC="P88"  | IOSTANDARD=LVCMOS33;                               
-NET "blue(0)"		LOC="P79"  | IOSTANDARD=LVCMOS33;                               
-
-NET "green(1)"		LOC="P83"  | IOSTANDARD=LVCMOS33;                                
-NET "red(1)"		LOC="P92"  | IOSTANDARD=LVCMOS33;                                
-NET "blue(1)"		LOC="P80"  | IOSTANDARD=LVCMOS33;                                
-
-NET "green(2)"		LOC="P84"  | IOSTANDARD=LVCMOS33;                               
-NET "red(2)"		LOC="P93"  | IOSTANDARD=LVCMOS33;                              
-NET "blue(2)"		LOC="P81"  | IOSTANDARD=LVCMOS33;                                
-                               
-NET "spi_do"		LOC="P78"  | IOSTANDARD=LVCMOS33;
-NET "spi_sclk"		LOC="P75"  | IOSTANDARD=LVCMOS33;
-NET "spi_di"		LOC="P74"  | IOSTANDARD=LVCMOS33;
-NET "spi_cs_n"		LOC="P59"  | IOSTANDARD=LVCMOS33;
-
-NET "audio_l"		LOC="P8"   | IOSTANDARD=LVCMOS33;                               
-NET "audio_r"		LOC="P9"   | IOSTANDARD=LVCMOS33;                               
-
-NET ram_a(0)  LOC="P115"   | IOSTANDARD=LVCMOS33;
-NET ram_a(1)  LOC="P116"   | IOSTANDARD=LVCMOS33;
-NET ram_a(2)  LOC="P117"   | IOSTANDARD=LVCMOS33;
-NET ram_a(3)  LOC="P119"   | IOSTANDARD=LVCMOS33;
-NET ram_a(4)  LOC="P120"   | IOSTANDARD=LVCMOS33;
-NET ram_a(5)  LOC="P123"   | IOSTANDARD=LVCMOS33;
-NET ram_a(6)  LOC="P126"   | IOSTANDARD=LVCMOS33;
-NET ram_a(7)  LOC="P131"   | IOSTANDARD=LVCMOS33;
-NET ram_a(8)  LOC="P127"   | IOSTANDARD=LVCMOS33;
-NET ram_a(9)  LOC="P124"   | IOSTANDARD=LVCMOS33;
-NET ram_a(10) LOC="P118"   | IOSTANDARD=LVCMOS33;
-NET ram_a(11) LOC="P121"   | IOSTANDARD=LVCMOS33;
-NET ram_a(12) LOC="P133"   | IOSTANDARD=LVCMOS33;
-NET ram_a(13) LOC="P132"   | IOSTANDARD=LVCMOS33;
-NET ram_a(14) LOC="P137"   | IOSTANDARD=LVCMOS33;
-NET ram_a(15) LOC="P140"   | IOSTANDARD=LVCMOS33;
-NET ram_a(16) LOC="P139"   | IOSTANDARD=LVCMOS33;
-NET ram_a(17) LOC="P141"   | IOSTANDARD=LVCMOS33;
-NET ram_a(18) LOC="P138"   | IOSTANDARD=LVCMOS33;
+# Keyboard and mouse
+NET "ps2_clk"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ps2_data"        LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 
-NET ram_d(0)  LOC="P114"   | IOSTANDARD=LVCMOS33;
-NET ram_d(1)  LOC="P112"   | IOSTANDARD=LVCMOS33;
-NET ram_d(2)  LOC="P111"   | IOSTANDARD=LVCMOS33;
-NET ram_d(3)  LOC="P99"    | IOSTANDARD=LVCMOS33;
-NET ram_d(4)  LOC="P100"   | IOSTANDARD=LVCMOS33;
-NET ram_d(5)  LOC="P101"   | IOSTANDARD=LVCMOS33;
-NET ram_d(6)  LOC="P102"   | IOSTANDARD=LVCMOS33;
-NET ram_d(7)  LOC="P104"   | IOSTANDARD=LVCMOS33;
+# SRAM
+NET sram_a(0)         LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(1)         LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(2)         LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(3)         LOC="P119" | IOSTANDARD = LVCMOS33;
+NET sram_a(4)         LOC="P120" | IOSTANDARD = LVCMOS33;
+NET sram_a(5)         LOC="P123" | IOSTANDARD = LVCMOS33;
+NET sram_a(6)         LOC="P126" | IOSTANDARD = LVCMOS33;
+NET sram_a(7)         LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(8)         LOC="P127" | IOSTANDARD = LVCMOS33;
+NET sram_a(9)         LOC="P124" | IOSTANDARD = LVCMOS33;
+NET sram_a(10)        LOC="P118" | IOSTANDARD = LVCMOS33;
+NET sram_a(11)        LOC="P121" | IOSTANDARD = LVCMOS33;
+NET sram_a(12)        LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(13)        LOC="P132" | IOSTANDARD = LVCMOS33;
+NET sram_a(14)        LOC="P137" | IOSTANDARD = LVCMOS33;
+NET sram_a(15)        LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(16)        LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(17)        LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(18)        LOC="P138" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>"                   IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>"                   IOSTANDARD = LVCMOS33;
 
-NET ram_WE_n  	 LOC="P134"  | IOSTANDARD=LVCMOS33;
+NET ram_d(0)          LOC="P114" | IOSTANDARD = LVCMOS33;
+NET ram_d(1)          LOC="P112" | IOSTANDARD = LVCMOS33;
+NET ram_d(2)          LOC="P111" | IOSTANDARD = LVCMOS33;
+NET ram_d(3)          LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET ram_d(4)          LOC="P100" | IOSTANDARD = LVCMOS33;
+NET ram_d(5)          LOC="P101" | IOSTANDARD = LVCMOS33;
+NET ram_d(6)          LOC="P102" | IOSTANDARD = LVCMOS33;
+NET ram_d(7)          LOC="P104" | IOSTANDARD = LVCMOS33;
 
-NET NTSC         LOC="P67"   | IOSTANDARD=LVCMOS33;
-NET PAL          LOC="P66"   | IOSTANDARD=LVCMOS33;
+NET sram_WE_n         LOC="P134" | IOSTANDARD = LVCMOS33;
 
-NET "ps2_data"   LOC="P97"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "ps2_clk"    LOC="P98"   | IOSTANDARD=LVCMOS33 | PULLUP;
 
-NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
\ No newline at end of file
+
+
+
+
+
+
+
+# SD/MMC
+NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33;
+NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33;
+NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33;
+NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "j1_up"           LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_down"         LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_left"         LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_right"        LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tl"           LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tr"           LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+# Otros
+NET "hdmi_out_p<0>"   LOC="P44"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<0>"   LOC="P43"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<1>"   LOC="P46"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<1>"   LOC="P45"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<2>"   LOC="P48"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<2>"   LOC="P47"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<3>"   LOC="P41"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<3>"   LOC="P40"  | IOSTANDARD = "TMDS_33";
diff --git a/cores/MasterSystem/src/sms_zxuno_v3.ucf b/cores/MasterSystem/src/sms_zxuno_v3.ucf
index 5fc4889..b41d2c7 100644
--- a/cores/MasterSystem/src/sms_zxuno_v3.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v3.ucf
@@ -1,84 +1,97 @@
 #UCF para el ZX-UNO v3
+NET "CLK"             LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
+NET "led"             LOC="P10"  | IOSTANDARD = LVCMOS33;
 
-NET "CLK"	 			PERIOD=20 ns;
-NET "CLK"      		LOC="P55"  | IOSTANDARD=LVCMOS33;
+# Video output
+NET "red(2)"          LOC="P93"  | IOSTANDARD = LVCMOS33;                              
+NET "red(1)"          LOC="P92"  | IOSTANDARD = LVCMOS33;                                
+NET "red(0)"          LOC="P88"  | IOSTANDARD = LVCMOS33;
+NET "green(2)"        LOC="P84"  | IOSTANDARD = LVCMOS33;                               
+NET "green(1)"        LOC="P83"  | IOSTANDARD = LVCMOS33;                                
+NET "green(0)"        LOC="P82"  | IOSTANDARD = LVCMOS33;
+NET "blue(2)"         LOC="P81"  | IOSTANDARD = LVCMOS33;                                
+NET "blue(1)"         LOC="P80"  | IOSTANDARD = LVCMOS33;                                
+NET "blue(0)"         LOC="P79"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET NTSC              LOC="P66"  | IOSTANDARD = LVCMOS33;
+NET PAL               LOC="P67"  | IOSTANDARD = LVCMOS33;
 
-NET "led"			LOC="P10"  | IOSTANDARD=LVCMOS33;
+# Sound input/output
+NET "audio_l"         LOC="P8"   | IOSTANDARD = LVCMOS33;                               
+NET "audio_r"         LOC="P9"   | IOSTANDARD = LVCMOS33;                               
 
-NET "j1_tr"			LOC="P39"  | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_tl"			LOC="P2"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_right"		LOC="P7"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_left"		LOC="P6"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_down"		LOC="P5"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "j1_up"			LOC="P1"   | IOSTANDARD=LVCMOS33 | PULLUP;
 
-NET "vsync"			LOC="P85"  | IOSTANDARD=LVCMOS33;
-NET "hsync"			LOC="P87"  | IOSTANDARD=LVCMOS33;
-
-NET "green(0)"		LOC="P82"  | IOSTANDARD=LVCMOS33;
-NET "red(0)"		LOC="P88"  | IOSTANDARD=LVCMOS33;
-NET "blue(0)"		LOC="P79"  | IOSTANDARD=LVCMOS33;
-
-NET "green(1)"		LOC="P83"  | IOSTANDARD=LVCMOS33;                                
-NET "red(1)"		LOC="P92"  | IOSTANDARD=LVCMOS33;                                
-NET "blue(1)"		LOC="P80"  | IOSTANDARD=LVCMOS33;                                
-
-NET "green(2)"		LOC="P84"  | IOSTANDARD=LVCMOS33;                               
-NET "red(2)"		LOC="P93"  | IOSTANDARD=LVCMOS33;                              
-NET "blue(2)"		LOC="P81"  | IOSTANDARD=LVCMOS33;                                
-                               
-NET "spi_do"		LOC="P78"  | IOSTANDARD=LVCMOS33;
-NET "spi_sclk"		LOC="P75"  | IOSTANDARD=LVCMOS33;
-NET "spi_di"		LOC="P74"  | IOSTANDARD=LVCMOS33;
-NET "spi_cs_n"		LOC="P59"  | IOSTANDARD=LVCMOS33;
-
-NET "audio_l"		LOC="P8"   | IOSTANDARD=LVCMOS33;                               
-NET "audio_r"		LOC="P9"   | IOSTANDARD=LVCMOS33;                               
-
-NET ram_a(0)  LOC="P143"   | IOSTANDARD=LVCMOS33;
-NET ram_a(1)  LOC="P142"   | IOSTANDARD=LVCMOS33;
-NET ram_a(2)  LOC="P141"   | IOSTANDARD=LVCMOS33;
-NET ram_a(3)  LOC="P140"   | IOSTANDARD=LVCMOS33;
-NET ram_a(4)  LOC="P139"   | IOSTANDARD=LVCMOS33;
-NET ram_a(5)  LOC="P104"   | IOSTANDARD=LVCMOS33;
-NET ram_a(6)  LOC="P102"   | IOSTANDARD=LVCMOS33;
-NET ram_a(7)  LOC="P101"   | IOSTANDARD=LVCMOS33;
-NET ram_a(8)  LOC="P100"   | IOSTANDARD=LVCMOS33;
-NET ram_a(9)  LOC="P99"    | IOSTANDARD=LVCMOS33;
-NET ram_a(10) LOC="P112"   | IOSTANDARD=LVCMOS33;
-NET ram_a(11) LOC="P114"   | IOSTANDARD=LVCMOS33;
-NET ram_a(12) LOC="P115"   | IOSTANDARD=LVCMOS33;
-NET ram_a(13) LOC="P116"   | IOSTANDARD=LVCMOS33;
-NET ram_a(14) LOC="P117"   | IOSTANDARD=LVCMOS33;
-NET ram_a(15) LOC="P131"   | IOSTANDARD=LVCMOS33;
-NET ram_a(16) LOC="P133"   | IOSTANDARD=LVCMOS33;
-NET ram_a(17) LOC="P134"   | IOSTANDARD=LVCMOS33;
-NET ram_a(18) LOC="P137"   | IOSTANDARD=LVCMOS33;
+# Keyboard and mouse
+NET "ps2_clk"         LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ps2_data"        LOC="P97"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 
-NET ram_d(0)  LOC="P132"   | IOSTANDARD=LVCMOS33;
-NET ram_d(1)  LOC="P126"   | IOSTANDARD=LVCMOS33;
-NET ram_d(2)  LOC="P123"   | IOSTANDARD=LVCMOS33;
-NET ram_d(3)  LOC="P120"   | IOSTANDARD=LVCMOS33;
-NET ram_d(4)  LOC="P119"   | IOSTANDARD=LVCMOS33;
-NET ram_d(5)  LOC="P121"   | IOSTANDARD=LVCMOS33;
-NET ram_d(6)  LOC="P124"   | IOSTANDARD=LVCMOS33;
-NET ram_d(7)  LOC="P127"   | IOSTANDARD=LVCMOS33;
+# SRAM
+NET sram_a(0)         LOC="P143" | IOSTANDARD = LVCMOS33;
+NET sram_a(1)         LOC="P142" | IOSTANDARD = LVCMOS33;
+NET sram_a(2)         LOC="P141" | IOSTANDARD = LVCMOS33;
+NET sram_a(3)         LOC="P140" | IOSTANDARD = LVCMOS33;
+NET sram_a(4)         LOC="P139" | IOSTANDARD = LVCMOS33;
+NET sram_a(5)         LOC="P104" | IOSTANDARD = LVCMOS33;
+NET sram_a(6)         LOC="P102" | IOSTANDARD = LVCMOS33;
+NET sram_a(7)         LOC="P101" | IOSTANDARD = LVCMOS33;
+NET sram_a(8)         LOC="P100" | IOSTANDARD = LVCMOS33;
+NET sram_a(9)         LOC="P99"  | IOSTANDARD = LVCMOS33;
+NET sram_a(10)        LOC="P112" | IOSTANDARD = LVCMOS33;
+NET sram_a(11)        LOC="P114" | IOSTANDARD = LVCMOS33;
+NET sram_a(12)        LOC="P115" | IOSTANDARD = LVCMOS33;
+NET sram_a(13)        LOC="P116" | IOSTANDARD = LVCMOS33;
+NET sram_a(14)        LOC="P117" | IOSTANDARD = LVCMOS33;
+NET sram_a(15)        LOC="P131" | IOSTANDARD = LVCMOS33;
+NET sram_a(16)        LOC="P133" | IOSTANDARD = LVCMOS33;
+NET sram_a(17)        LOC="P134" | IOSTANDARD = LVCMOS33;
+NET sram_a(18)        LOC="P137" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>"      LOC="P111" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>"      LOC="P138" | IOSTANDARD = LVCMOS33;
 
-NET ram_WE_n  	 LOC="P118"  | IOSTANDARD=LVCMOS33;
+NET ram_d(0)          LOC="P132" | IOSTANDARD = LVCMOS33;
+NET ram_d(1)          LOC="P126" | IOSTANDARD = LVCMOS33;
+NET ram_d(2)          LOC="P123" | IOSTANDARD = LVCMOS33;
+NET ram_d(3)          LOC="P120" | IOSTANDARD = LVCMOS33;
+NET ram_d(4)          LOC="P119" | IOSTANDARD = LVCMOS33;
+NET ram_d(5)          LOC="P121" | IOSTANDARD = LVCMOS33;
+NET ram_d(6)          LOC="P124" | IOSTANDARD = LVCMOS33;
+NET ram_d(7)          LOC="P127" | IOSTANDARD = LVCMOS33;
 
-NET NTSC        LOC="P67"   | IOSTANDARD=LVCMOS33;
-NET PAL       	 LOC="P66"   | IOSTANDARD=LVCMOS33;
+NET sram_WE_n         LOC="P118" | IOSTANDARD = LVCMOS33;
 
-NET "ps2_data"   LOC="P97"   | IOSTANDARD=LVCMOS33 | PULLUP;
-NET "ps2_clk"    LOC="P98"   | IOSTANDARD=LVCMOS33 | PULLUP;
 
-NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
-NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
\ No newline at end of file
+
+
+
+
+
+
+
+# SD/MMC
+NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33;
+NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33;
+NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33;
+NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "j1_up"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_down"         LOC="P5"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_left"         LOC="P6"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_right"        LOC="P7"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tl"           LOC="P2"   | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "j1_tr"           LOC="P39"  | IOSTANDARD = LVCMOS33 | PULLUP;
+
+
+
+# Otros
+NET "hdmi_out_p<0>"   LOC="P44"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<0>"   LOC="P43"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<1>"   LOC="P46"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<1>"   LOC="P45"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<2>"   LOC="P48"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<2>"   LOC="P47"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_p<3>"   LOC="P41"  | IOSTANDARD = "TMDS_33";
+NET "hdmi_out_n<3>"   LOC="P40"  | IOSTANDARD = "TMDS_33";
diff --git a/cores/MasterSystem/src/sms_zxuno_v4.ucf b/cores/MasterSystem/src/sms_zxuno_v4.ucf
index 4c8f5cb..47f0fba 100644
--- a/cores/MasterSystem/src/sms_zxuno_v4.ucf
+++ b/cores/MasterSystem/src/sms_zxuno_v4.ucf
@@ -29,27 +29,27 @@ NET "ps2_data"        LOC="P98"  | IOSTANDARD = LVCMOS33 | PULLUP;
 
 
 # SRAM
-NET "ram_a<0>"        LOC="P141" | IOSTANDARD = LVCMOS33;
-NET "ram_a<1>"        LOC="P139" | IOSTANDARD = LVCMOS33;
-NET "ram_a<2>"        LOC="P137" | IOSTANDARD = LVCMOS33;
-NET "ram_a<3>"        LOC="P134" | IOSTANDARD = LVCMOS33;
-NET "ram_a<4>"        LOC="P133" | IOSTANDARD = LVCMOS33;
-NET "ram_a<5>"        LOC="P120" | IOSTANDARD = LVCMOS33;
-NET "ram_a<6>"        LOC="P118" | IOSTANDARD = LVCMOS33;
-NET "ram_a<7>"        LOC="P116" | IOSTANDARD = LVCMOS33;
-NET "ram_a<8>"        LOC="P114" | IOSTANDARD = LVCMOS33;
-NET "ram_a<9>"        LOC="P112" | IOSTANDARD = LVCMOS33;
-NET "ram_a<10>"       LOC="P104" | IOSTANDARD = LVCMOS33;
-NET "ram_a<11>"       LOC="P102" | IOSTANDARD = LVCMOS33;
-NET "ram_a<12>"       LOC="P101" | IOSTANDARD = LVCMOS33;
-NET "ram_a<13>"       LOC="P100" | IOSTANDARD = LVCMOS33;
-NET "ram_a<14>"       LOC="P111" | IOSTANDARD = LVCMOS33;
-NET "ram_a<15>"       LOC="P131" | IOSTANDARD = LVCMOS33;
-NET "ram_a<16>"       LOC="P138" | IOSTANDARD = LVCMOS33;
-NET "ram_a<17>"       LOC="P140" | IOSTANDARD = LVCMOS33;
-NET "ram_a<18>"       LOC="P142" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<19>"       LOC="P105" | IOSTANDARD = LVCMOS33;
-#NET "ram_a<20>"       LOC="P143" | IOSTANDARD = LVCMOS33;
+NET "sram_a<0>"       LOC="P141" | IOSTANDARD = LVCMOS33;
+NET "sram_a<1>"       LOC="P139" | IOSTANDARD = LVCMOS33;
+NET "sram_a<2>"       LOC="P137" | IOSTANDARD = LVCMOS33;
+NET "sram_a<3>"       LOC="P134" | IOSTANDARD = LVCMOS33;
+NET "sram_a<4>"       LOC="P133" | IOSTANDARD = LVCMOS33;
+NET "sram_a<5>"       LOC="P120" | IOSTANDARD = LVCMOS33;
+NET "sram_a<6>"       LOC="P118" | IOSTANDARD = LVCMOS33;
+NET "sram_a<7>"       LOC="P116" | IOSTANDARD = LVCMOS33;
+NET "sram_a<8>"       LOC="P114" | IOSTANDARD = LVCMOS33;
+NET "sram_a<9>"       LOC="P112" | IOSTANDARD = LVCMOS33;
+NET "sram_a<10>"      LOC="P104" | IOSTANDARD = LVCMOS33;
+NET "sram_a<11>"      LOC="P102" | IOSTANDARD = LVCMOS33;
+NET "sram_a<12>"      LOC="P101" | IOSTANDARD = LVCMOS33;
+NET "sram_a<13>"      LOC="P100" | IOSTANDARD = LVCMOS33;
+NET "sram_a<14>"      LOC="P111" | IOSTANDARD = LVCMOS33;
+NET "sram_a<15>"      LOC="P131" | IOSTANDARD = LVCMOS33;
+NET "sram_a<16>"      LOC="P138" | IOSTANDARD = LVCMOS33;
+NET "sram_a<17>"      LOC="P140" | IOSTANDARD = LVCMOS33;
+NET "sram_a<18>"      LOC="P142" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<19>"      LOC="P105" | IOSTANDARD = LVCMOS33;
+#NET "sram_a<20>"      LOC="P143" | IOSTANDARD = LVCMOS33;
 
 NET "ram_d<0>"        LOC="P132" | IOSTANDARD = LVCMOS33;
 NET "ram_d<1>"        LOC="P127" | IOSTANDARD = LVCMOS33;
@@ -60,7 +60,7 @@ NET "ram_d<5>"        LOC="P117" | IOSTANDARD = LVCMOS33;
 NET "ram_d<6>"        LOC="P119" | IOSTANDARD = LVCMOS33;
 NET "ram_d<7>"        LOC="P126" | IOSTANDARD = LVCMOS33;
 
-NET "ram_WE_n"        LOC="P121" | IOSTANDARD = LVCMOS33;
+NET "sram_WE_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
 
 
 
@@ -71,10 +71,10 @@ NET "ram_WE_n"        LOC="P121" | IOSTANDARD = LVCMOS33;
 
 
 # SD/MMC
-NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33;
+NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33;
 NET "spi_sclk"        LOC="P75"  | IOSTANDARD = LVCMOS33;
 NET "spi_di"          LOC="P74"  | IOSTANDARD = LVCMOS33;
-NET "spi_cs_n"        LOC="P59"  | IOSTANDARD = LVCMOS33;
+NET "spi_do"          LOC="P78"  | IOSTANDARD = LVCMOS33;
 
 # JOYSTICK
 NET "j1_up"           LOC="P1"   | IOSTANDARD = LVCMOS33 | PULLUP;
diff --git a/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf b/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
index 8b62906..11d2892 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P2"   | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P84"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P83"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"          LOC="P92"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P93"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P92"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P51"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P50"  | IOSTANDARD = LVCMOS33;
 
@@ -87,5 +87,3 @@ NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
 
 
 # Otros
-NET "clk12"           PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v2.ucf b/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
index 711e9ac..17975e0 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v2.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P10"  | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P67"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P66"  | IOSTANDARD = LVCMOS33;
 
@@ -87,5 +87,3 @@ NET "sram_we_n"       LOC="P134" | IOSTANDARD = LVCMOS33;
 
 
 # Otros
-NET "clk12"           PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v3.ucf b/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
index 679a83e..451cf3a 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v3.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P10"  | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P81"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P80"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P79"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P67"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P66"  | IOSTANDARD = LVCMOS33;
 
@@ -87,5 +87,3 @@ NET "sram_we_n"       LOC="P118" | IOSTANDARD = LVCMOS33;
 
 
 # Otros
-NET "clk12"           PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/SamCoupe_zxuno_v4.ucf b/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
index 4daa913..9e2c339 100644
--- a/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
+++ b/cores/SamCoupe/SamCoupe_zxuno_v4.ucf
@@ -1,5 +1,5 @@
 # Clocks & debug
-NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
+NET "clk50mhz"        LOC="P55"  | IOSTANDARD = LVCMOS33;
 #NET "testled"         LOC="P11"  | IOSTANDARD = LVCMOS33;
 
 # Video output
@@ -12,8 +12,8 @@ NET "g<0>"            LOC="P82"  | IOSTANDARD = LVCMOS33;
 NET "b<2>"            LOC="P93"  | IOSTANDARD = LVCMOS33;
 NET "b<1>"            LOC="P92"  | IOSTANDARD = LVCMOS33;
 NET "b<0>"            LOC="P88"  | IOSTANDARD = LVCMOS33;
-NET "csync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
-#NET "vsync"          LOC="P85"  | IOSTANDARD = LVCMOS33;
+NET "hsync"           LOC="P87"  | IOSTANDARD = LVCMOS33;
+NET "vsync"           LOC="P85"  | IOSTANDARD = LVCMOS33;
 NET "stdn"            LOC="P66"  | IOSTANDARD = LVCMOS33;
 NET "stdnb"           LOC="P67"  | IOSTANDARD = LVCMOS33;
 
@@ -87,5 +87,3 @@ NET "sram_we_n"       LOC="P121" | IOSTANDARD = LVCMOS33;
 
 
 # Otros
-NET "clk12"           PERIOD=83 ns;
-
diff --git a/cores/SamCoupe/asic.v b/cores/SamCoupe/asic.v
index af6a145..ac37cdc 100644
--- a/cores/SamCoupe/asic.v
+++ b/cores/SamCoupe/asic.v
@@ -56,7 +56,8 @@ module asic (
     output wire [1:0] g,
     output wire [1:0] b,
     output wire bright,
-    output reg csync,
+    output reg hsync_pal,
+    output reg vsync_pal,
     output wire int_n
     );
 
@@ -177,14 +178,17 @@ module asic (
     reg rint_n;
     
     always @* begin
-        csync = 1'b1;
+        hsync_pal = 1'b1;
+        vsync_pal = 1'b1;
         vint_n = 1'b1;
         rint_n = 1'b1;
-        if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC))
-          csync = 1'b0;
-        if (vc >= BEGINVSYNCV && vc < ENDVSYNCV)
-          csync = ~csync;
-        if (vc == BEGINVSYNCV && hc < 256)
+        if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC)) begin
+          hsync_pal = 1'b0;
+		end
+        if (vc >= BEGINVSYNCV && vc < ENDVSYNCV) begin
+          vsync_pal = 1'b0;
+		end
+        if (vc == BEGINVSYNCV && hc < 10'd256)
           vint_n = 1'b0;
         if (lineint >= 8'd0 && lineint <= 8'd191)
             if ({1'b0, lineint} == vc && hc < 10'd256)
@@ -197,7 +201,7 @@ module asic (
     reg fetching_pixels;
     
     always @* begin
-        if (vc>=0 && vc<VACTIVEREGION && hc>=256 && hc<HTOTAL)
+        if (vc>=0 && vc<VACTIVEREGION && hc>=10'd256 && hc<HTOTAL)
             fetching_pixels = ~screen_off;
         else
             fetching_pixels = 1'b0;
@@ -226,28 +230,25 @@ module asic (
         mem_contention = 1'b0;
         io_contention = 1'b0;
 
-//        if (screen_off == 1'b0 && hc[3:0]<4'd10)
-//            io_contention = 1'b1;
-//        if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
-//                                        hc[3:0]==4'd1 ||
-//                                        hc[3:0]==4'd8 ||
-//                                        hc[3:0]==4'd9) )
-//            io_contention = 1'b1;
+        if (screen_off == 1'b0 && hc[3:0]<4'd10)
+            io_contention = 1'b1;
+        if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
+                                        hc[3:0]==4'd1 ||
+                                        hc[3:0]==4'd8 ||
+                                        hc[3:0]==4'd9) )
+            io_contention = 1'b1;
             
         if (fetching_pixels == 1'b1 && hc[3:0]<4'd10) begin
            mem_contention = 1'b1;
-           //io_contention = 1'b1;
         end
         if (fetching_pixels == 1'b0 && (hc[3:0]==4'd0 ||
                                              hc[3:0]==4'd1 ||
                                              hc[3:0]==4'd8 ||
                                              hc[3:0]==4'd9) ) begin
             mem_contention = 1'b1;
-            //io_contention = 1'b1;
         end
         if (screen_mode == 2'b00 && hc[3:0]<4'd10 && (hc<10'd128 || hc>=10'd256)) begin
             mem_contention = 1'b1;  // extra contention for MODE 1
-            //io_contention = 1'b1;
         end
     end
     assign asic_is_using_ram = mem_contention & fetching_pixels;
@@ -465,7 +466,7 @@ module asic (
             border <= 8'h00;
         end
         else begin
-            if (iorq_n == 1'b0 && wr_n == 1'b0) begin
+            if (iorq_n == 1'b0 && wr_n == 1'b0 && wait_n == 1'b1) begin
                 if (cpuaddr[7:0] == IOADDR_BORDER)
                     border <= data_from_cpu;
                 else if (cpuaddr[7:0] == IOADDR_VMPR)
diff --git a/cores/SamCoupe/audio_management.v b/cores/SamCoupe/audio_management.v
index c40ec95..593c195 100644
--- a/cores/SamCoupe/audio_management.v
+++ b/cores/SamCoupe/audio_management.v
@@ -37,7 +37,7 @@ module dac (DACout, DACin, Clk, Reset);
 	always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
 	always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
 	always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
-	always @(posedge Clk or posedge Reset)
+	always @(posedge Clk)
 	begin
 		if(Reset)
 		begin
diff --git a/cores/SamCoupe/multiboot.v b/cores/SamCoupe/multiboot.v
new file mode 100644
index 0000000..f8346f4
--- /dev/null
+++ b/cores/SamCoupe/multiboot.v
@@ -0,0 +1,307 @@
+module multiboot (
+    input wire clk_icap,   // WARNING: this clock must not be greater than 20MHz (50ns period)
+    input wire mrst_n
+    );
+    
+    reg [4:0] q = 5'b00000;
+    reg reboot_ff = 1'b0;
+    always @(posedge clk_icap) begin
+      q[0] <= ~mrst_n;
+      q[1] <= q[0];
+      q[2] <= q[1];
+      q[3] <= q[2];
+      q[4] <= q[3];
+      reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
+    end
+
+    multiboot_spartan6 hacer_multiboot (
+        .CLK(clk_icap),
+        .MBT_RESET(1'b0),
+        .MBT_REBOOT(reboot_ff),
+        .spi_addr(24'h000000)
+    );
+endmodule            
+    
+module multiboot_spartan6 (
+    input wire CLK,
+    input wire MBT_RESET,
+    input wire MBT_REBOOT,
+    input wire [23:0] spi_addr
+  );
+
+reg  [15:0] icap_din;
+reg         icap_ce;
+reg         icap_wr;
+
+reg  [15:0] ff_icap_din_reversed;
+reg         ff_icap_ce;
+reg         ff_icap_wr;
+
+
+  ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
+  
+    .CE        (ff_icap_ce),   // Clock enable input
+    .CLK       (CLK),         // Clock input
+    .I         (ff_icap_din_reversed),  // 16-bit data input
+    .WRITE     (ff_icap_wr)    // Write input
+  );
+
+
+//  -------------------------------------------------
+//  --  State Machine for ICAP_SPARTAN6 MultiBoot  --
+//  -------------------------------------------------
+
+
+parameter         IDLE     = 0, 
+                  SYNC_H   = 1, 
+                  SYNC_L   = 2, 
+                  
+                  CWD_H    = 3,  
+                  CWD_L    = 4,  
+                                 
+                  GEN1_H   = 5,  
+                  GEN1_L   = 6,  
+                                 
+                  GEN2_H   = 7,  
+                  GEN2_L   = 8,  
+                                 
+                  GEN3_H   = 9,  
+                  GEN3_L   = 10, 
+                                 
+                  GEN4_H   = 11, 
+                  GEN4_L   = 12, 
+                                 
+                  GEN5_H   = 13, 
+                  GEN5_L   = 14, 
+                                 
+                  NUL_H    = 15, 
+                  NUL_L    = 16, 
+                                 
+                  MOD_H    = 17, 
+                  MOD_L    = 18, 
+                                 
+                  HCO_H    = 19, 
+                  HCO_L    = 20, 
+                                 
+                  RBT_H    = 21, 
+                  RBT_L    = 22, 
+                  
+                  NOOP_0   = 23, 
+                  NOOP_1   = 24,
+                  NOOP_2   = 25,
+                  NOOP_3   = 26;
+                  
+                   
+reg [4:0]     state;
+reg [4:0]     next_state;
+
+
+always @*
+   begin: COMB
+
+      case (state)
+      
+         IDLE:
+            begin
+               if (MBT_REBOOT)
+                  begin
+                     next_state  = SYNC_H;
+                     icap_ce     = 0;
+                     icap_wr     = 0;
+                     icap_din    = 16'hAA99;  // Sync word 1 
+                  end
+               else
+                  begin
+                     next_state  = IDLE;
+                     icap_ce     = 1;
+                     icap_wr     = 1;
+                     icap_din    = 16'hFFFF;  // Null 
+                  end
+            end
+            
+         SYNC_H:
+            begin
+               next_state  = SYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h5566;    // Sync word 2
+            end
+
+         SYNC_L:
+            begin
+               next_state  = NUL_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h30A1;    //  Write to Command Register....
+            end
+
+        NUL_H:
+            begin
+              // next_state  = NUL_L;
+	       next_state  = GEN1_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h0000;   //  Null Command issued....  value = 0x0000
+            end
+
+//Q
+
+         GEN1_H:
+            begin
+               next_state  = GEN1_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3261;    //  Escritura a reg GENERAL_1 (bit boot en caliente)
+            end
+
+        GEN1_L:
+            begin
+               next_state  = GEN2_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = spi_addr[15:0]; //16'hC000;   //  dreccion SPI BAJA
+            end
+
+         GEN2_H:
+            begin
+               next_state  = GEN2_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3281;   //  Escritura a reg GENERAL_2
+            end
+
+        GEN2_L:
+            begin
+               next_state  = MOD_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = {8'h6B, spi_addr[23:16]}; // 16'h030A;   //  03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
+            end
+	
+///////	Registro MODE (para carga a 4x tras reboot)
+
+        MOD_H:
+            begin
+               next_state  = MOD_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3301;   //  Escritura a reg MODE
+            end
+
+        MOD_L:
+            begin
+               next_state  = NUL_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
+            end				
+/////
+
+        NUL_L:
+            begin
+               next_state  = RBT_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h30A1;    //  Write to Command Register....
+            end
+
+        RBT_H:
+            begin
+               next_state  = RBT_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h000E;    // REBOOT Command 0x000E
+            end
+
+//--------------------
+
+        RBT_L:
+            begin
+               next_state  = NOOP_0;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    //  NOOP
+            end
+
+        NOOP_0:
+            begin
+               next_state  = NOOP_1;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+        NOOP_1:
+            begin
+               next_state  = NOOP_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+        NOOP_2:
+            begin
+               next_state  = NOOP_3;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+//--------------------
+
+        NOOP_3:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    // NULL value
+            end
+          
+        default:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    //  16'h1111"
+            end
+
+      endcase
+   end
+
+always @(posedge CLK)
+
+   begin:   SEQ
+      if (MBT_RESET)
+         state <= IDLE;
+      else
+         state <= next_state;
+   end
+
+
+always @(posedge CLK)
+
+   begin:   ICAP_FF
+   
+        ff_icap_din_reversed[0]  <= icap_din[7];   //need to reverse bits to ICAP module since D0 bit is read first
+        ff_icap_din_reversed[1]  <= icap_din[6]; 
+        ff_icap_din_reversed[2]  <= icap_din[5]; 
+        ff_icap_din_reversed[3]  <= icap_din[4]; 
+        ff_icap_din_reversed[4]  <= icap_din[3]; 
+        ff_icap_din_reversed[5]  <= icap_din[2]; 
+        ff_icap_din_reversed[6]  <= icap_din[1]; 
+        ff_icap_din_reversed[7]  <= icap_din[0]; 
+        ff_icap_din_reversed[8]  <= icap_din[15];
+        ff_icap_din_reversed[9]  <= icap_din[14];
+        ff_icap_din_reversed[10] <= icap_din[13];
+        ff_icap_din_reversed[11] <= icap_din[12];
+        ff_icap_din_reversed[12] <= icap_din[11];
+        ff_icap_din_reversed[13] <= icap_din[10];
+        ff_icap_din_reversed[14] <= icap_din[9]; 
+        ff_icap_din_reversed[15] <= icap_din[8]; 
+        
+        ff_icap_ce  <= icap_ce;
+        ff_icap_wr  <= icap_wr;
+   end  
+        
+        
+endmodule
diff --git a/cores/SamCoupe/samcoupe.v b/cores/SamCoupe/samcoupe.v
index 9700164..12d82b5 100644
--- a/cores/SamCoupe/samcoupe.v
+++ b/cores/SamCoupe/samcoupe.v
@@ -31,7 +31,8 @@ module samcoupe (
     output wire [1:0] g,
     output wire [1:0] b,
     output wire bright,
-    output wire csync,
+    output wire hsync_pal,
+    output wire vsync_pal,
     // Audio output
     input wire ear,
     output wire audio_out_left,
@@ -61,6 +62,7 @@ module samcoupe (
     wire [7:0] kbcolumns;
     wire kb_nmi_n;
     wire kb_rst_n;
+    wire kb_mrst_n;
     wire rdmsel;
     assign kbrows = {rdmsel, cpuaddr[15:8]};
     
@@ -91,7 +93,7 @@ module samcoupe (
                          (asic_oe_n == 1'b0)? data_from_asic :
                          8'hFF;
 
-    tv80n el_z80 (
+    tv80a el_z80 (
       .m1_n(),
       .mreq_n(mreq_n),
       .iorq_n(iorq_n),
@@ -148,12 +150,13 @@ module samcoupe (
         .g(g),
         .b(b),
         .bright(bright),
-        .csync(csync),
+        .hsync_pal(hsync_pal),
+        .vsync_pal(vsync_pal),
         .int_n(int_n)
     );
     
     rom rom_32k (
-        .clk(clk12),
+        .clk(clk24),
         .a(romaddr),
         .dout(data_from_rom)
     );
@@ -200,7 +203,7 @@ module samcoupe (
         .cols(kbcolumns),
         .rst_out_n(kb_rst_n),
         .nmi_out_n(kb_nmi_n),
-        .mrst_out_n(),
+        .mrst_out_n(kb_mrst_n),
         .user_toggles(),
         //---------------------------------
         .zxuno_addr(8'h00),
@@ -239,4 +242,8 @@ module samcoupe (
         .audio_right(audio_out_right)
 	);
     
+    multiboot back_to_bios (
+        .clk_icap(clk24),   // WARNING: this clock must not be greater than 20MHz (50ns period)
+        .mrst_n(kb_mrst_n)
+    );
 endmodule
diff --git a/cores/SamCoupe/scancode_to_speccy.v b/cores/SamCoupe/scancode_to_sam.v
similarity index 100%
rename from cores/SamCoupe/scancode_to_speccy.v
rename to cores/SamCoupe/scancode_to_sam.v
diff --git a/cores/SamCoupe/timings.xcf b/cores/SamCoupe/timings.xcf
new file mode 100644
index 0000000..8fdd74d
--- /dev/null
+++ b/cores/SamCoupe/timings.xcf
@@ -0,0 +1,5 @@
+#NET "clk50mhz" PERIOD=20 ns;
+NET "clk24" KEEP | S | PERIOD=41 ns;
+NET "clk12" KEEP | S | PERIOD=82 ns;
+NET "clk6" KEEP | S | PERIOD=164 ns;
+NET "clk8" KEEP | S | PERIOD=125 ns;
\ No newline at end of file
diff --git a/cores/SamCoupe/tld_sam.prj b/cores/SamCoupe/tld_sam.prj
index 1ad0847..013fdc6 100644
--- a/cores/SamCoupe/tld_sam.prj
+++ b/cores/SamCoupe/tld_sam.prj
@@ -2,15 +2,17 @@ verilog work "tv80_reg.v"
 verilog work "tv80_mcode.v"
 verilog work "tv80_alu.v"
 verilog work "tv80_core.v"
-verilog work "scancode_to_speccy.v"
+verilog work "scancode_to_sam.v"
 verilog work "ps2_port.v"
-verilog work "tv80n.v"
+verilog work "tv80a.v"
 verilog work "saa1099.v"
 verilog work "rom.v"
 verilog work "ram.v"
 verilog work "ps2_keyb.v"
+verilog work "multiboot.v"
 verilog work "audio_management.v"
 verilog work "asic.v"
+verilog work "vga_scandoubler.v"
 verilog work "samcoupe.v"
 verilog work "relojes.v"
 verilog work "tld_sam.v"
diff --git a/cores/SamCoupe/tld_sam.ut b/cores/SamCoupe/tld_sam.ut
index 8440878..a9facca 100644
--- a/cores/SamCoupe/tld_sam.ut
+++ b/cores/SamCoupe/tld_sam.ut
@@ -3,7 +3,7 @@
 -g Compress
 -g CRC:Enable
 -g Reset_on_err:No
--g ConfigRate:4
+-g ConfigRate:2
 -g ProgPin:PullUp
 -g TckPin:PullUp
 -g TdiPin:PullUp
diff --git a/cores/SamCoupe/tld_sam.v b/cores/SamCoupe/tld_sam.v
index 37d5ae2..4bc1cec 100644
--- a/cores/SamCoupe/tld_sam.v
+++ b/cores/SamCoupe/tld_sam.v
@@ -30,11 +30,12 @@ module tld_sam (
     output wire [2:0] r,
     output wire [2:0] g,
     output wire [2:0] b,
-    output wire csync,
+    output wire hsync,
+	 output wire vsync,
     output wire stdn,
     output wire stdnb,
     // SRAM interface
-    output wire [18:0] sram_addr,
+    output wire [20:0] sram_addr,
     inout wire [7:0] sram_data,
     output wire sram_we_n,
     // PS/2 keyoard interface
@@ -43,24 +44,34 @@ module tld_sam (
     );
 
     // Interface with RAM
-    wire [18:0] ramaddr;
-    wire [7:0] data_from_ram;
-    wire [7:0] data_to_ram;
-    wire ram_we_n;
+    wire [18:0] sram_addr_from_sam;
+    wire sram_we_n_from_sam;
     
     // Audio and video
     wire [1:0] sam_r, sam_g, sam_b;
     wire sam_bright;
     
-    assign r = {sam_r, sam_bright};
-    assign g = {sam_g, sam_bright};
-    assign b = {sam_b, sam_bright};
+	 // scandoubler
+	 wire hsync_pal, vsync_pal;
+    wire [2:0] ri = {sam_r, sam_bright};
+    wire [2:0] gi = {sam_g, sam_bright};
+    wire [2:0] bi = {sam_b, sam_bright};
 
     assign stdn = 1'b0;  // fijar norma PAL
 	assign stdnb = 1'b1; // y conectamos reloj PAL
     
     wire clk24, clk12, clk6, clk8;
 
+    reg [7:0] poweron_reset = 8'h00;
+    reg [1:0] scandoubler_ctrl = 2'b00;
+    always @(posedge clk6) begin
+        poweron_reset <= {poweron_reset[6:0], 1'b1};
+        if (poweron_reset[6] == 1'b0)
+            scandoubler_ctrl <= sram_data[1:0];
+    end
+    assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
+    assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
+
     relojes los_relojes (
         .CLK_IN1            (clk50mhz),      // IN
         // Clock out ports
@@ -75,13 +86,14 @@ module tld_sam (
         .clk12(clk12),
         .clk6(clk6),
         .clk8(clk8),
-        .master_reset_n(1'b1),  // esta señal es sólo para simulación
+        .master_reset_n(poweron_reset[7]),
         // Video output
         .r(sam_r),
         .g(sam_g),
         .b(sam_b),
         .bright(sam_bright),
-        .csync(csync),
+	    .hsync_pal(hsync_pal),
+		.vsync_pal(vsync_pal),
         // Audio output
         .ear(~ear),
         .audio_out_left(audio_out_left),
@@ -90,8 +102,26 @@ module tld_sam (
         .clkps2(clkps2),
         .dataps2(dataps2),
         // SRAM external interface
-        .sram_addr(sram_addr),
+        .sram_addr(sram_addr_from_sam),
         .sram_data(sram_data),
-        .sram_we_n(sram_we_n)
+        .sram_we_n(sram_we_n_from_sam)
     );        
+	 
+	vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
+		.clkvideo(clk12),
+		.clkvga(clk24),
+		.enable_scandoubling(scandoubler_ctrl[0]),
+        .disable_scaneffect(~scandoubler_ctrl[1]),
+		.ri(ri),
+		.gi(gi),
+		.bi(bi),
+		.hsync_ext_n(hsync_pal),
+		.vsync_ext_n(vsync_pal),
+		.ro(r),
+		.go(g),
+		.bo(b),
+		.hsync(hsync),
+		.vsync(vsync)
+   );	 	 
+	 
 endmodule
diff --git a/cores/SamCoupe/tld_sam.xst b/cores/SamCoupe/tld_sam.xst
index 9b8b64c..635afd7 100644
--- a/cores/SamCoupe/tld_sam.xst
+++ b/cores/SamCoupe/tld_sam.xst
@@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
 set -xsthdpdir "xst"
 run
 -ifn tld_sam.prj
+-infer_ramb8 No
 -ofn tld_sam
 -ofmt NGC
 -p xc6slx9-2-tqg144
 -top tld_sam
 -opt_mode Speed
--opt_level 1
+-opt_level 2
 -power NO
+-uc "timings.xcf"
 -iuc NO
 -keep_hierarchy No
 -netlist_hierarchy As_Optimized
 -rtlview Yes
 -glob_opt AllClockNets
 -read_cores YES
--write_timing_constraints NO
+-write_timing_constraints YES
 -cross_clock_analysis NO
 -hierarchy_separator /
 -bus_delimiter <>
@@ -35,7 +37,7 @@ run
 -shreg_extract YES
 -rom_style Auto
 -auto_bram_packing NO
--resource_sharing NO
+-resource_sharing YES
 -async_to_sync NO
 -shreg_min_size 2
 -use_dsp48 Auto
diff --git a/cores/SamCoupe/tv80n.v b/cores/SamCoupe/tv80a.v
similarity index 65%
rename from cores/SamCoupe/tv80n.v
rename to cores/SamCoupe/tv80a.v
index 70454a1..17b82ef 100644
--- a/cores/SamCoupe/tv80n.v
+++ b/cores/SamCoupe/tv80a.v
@@ -25,7 +25,7 @@
 // Negative-edge based wrapper allows memory wait_n signal to work
 // correctly without resorting to asynchronous logic.
 
-module tv80n (/*AUTOARG*/
+module tv80a (/*AUTOARG*/
   // Outputs
   m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
   // Inputs
@@ -33,7 +33,7 @@ module tv80n (/*AUTOARG*/
   );
 
   parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
+  parameter T2Write = 1; // 1 => wr_n active in T3, 0 => wr_n active in T2
   parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
 
 
@@ -59,10 +59,6 @@ module tv80n (/*AUTOARG*/
   reg           iorq_n; 
   reg           rd_n; 
   reg           wr_n; 
-  reg           nxt_mreq_n; 
-  reg           nxt_iorq_n; 
-  reg           nxt_rd_n; 
-  reg           nxt_wr_n; 
   
   wire          cen;
   wire          intcycle_n;
@@ -102,56 +98,71 @@ module tv80n (/*AUTOARG*/
      .intcycle_n (intcycle_n)
      );  
 
+    reg [6:0] tstate_r = 7'h00;
+    reg [6:0] tstate_rr = 7'h00;
+    always @(negedge clk) begin
+        tstate_r <= tstate;
+    end
+    always @(posedge clk) begin
+        tstate_rr <= tstate;
+    end
+
+    wire mreq_read  = ~iorq & ~no_read & ~write;
+    wire mreq_write = ~iorq & ~no_read & write;
+    wire iorq_read  = iorq & ~no_read & ~write;
+    wire iorq_write = iorq & ~no_read & write;
+
     always @* begin
-        nxt_mreq_n = 1;
-        nxt_rd_n   = 1;
-        nxt_iorq_n = 1;
-        nxt_wr_n   = 1;
+        mreq_n = 1;
+        rd_n   = 1;
+        iorq_n = 1;
+        wr_n   = 1;
           
         if (mcycle[0]) begin
-            if (tstate[1] || tstate[2]) begin
-                nxt_rd_n = ~ intcycle_n;
-                nxt_mreq_n = ~ intcycle_n;
-                nxt_iorq_n = intcycle_n;
-            end
-        end // if (mcycle[0])          
-        else begin
-            if ((tstate[1] || tstate[2]) && !no_read && !write) begin
-                nxt_rd_n = 1'b0;
-                nxt_iorq_n = ~ iorq;
-                nxt_mreq_n = iorq;
-            end
-            if (T2Write == 0) begin                          
-                if (tstate[2] && write) begin
-                    nxt_wr_n = 1'b0;
-                    nxt_iorq_n = ~ iorq;
-                    nxt_mreq_n = iorq;
+            if (intcycle_n == 1'b1) begin
+                if (tstate_r[1] || tstate[2]) begin
+                    mreq_n = 1'b0;
+                    rd_n = 1'b0;
+                end
+                else if (rfsh_n == 1'b0 && tstate_r[3]) begin
+                    mreq_n = 1'b0;
                 end
             end
             else begin
-                if ((tstate[1] || (tstate[2] && !wait_n)) && write) begin
-                    nxt_wr_n = 1'b0;
-                    nxt_iorq_n = ~ iorq;
-                    nxt_mreq_n = iorq;
+                if (tstate[2]) begin
+                    iorq_n = 1'b0;
                 end
-            end // else: !if(T2write == 0)          
-        end // else: !if(mcycle[0])
-    end // always @ *
-
-    always @(negedge clk) begin
-        if (!reset_n) begin
-            rd_n   <= #1 1'b1;
-            wr_n   <= #1 1'b1;
-            iorq_n <= #1 1'b1;
-            mreq_n <= #1 1'b1;
+            end
         end
         else begin
-            rd_n <= #1 nxt_rd_n;
-            wr_n <= #1 nxt_wr_n;
-            iorq_n <= #1 nxt_iorq_n;
-            mreq_n <= #1 nxt_mreq_n;
-        end // else: !if(!reset_n)
-    end // always @ (posedge clk or negedge reset_n)
+            if (mreq_read == 1'b1) begin
+                if (tstate_r[1] || tstate_r[2]) begin
+                    mreq_n = 1'b0;
+                    rd_n = 1'b0;
+                end
+            end
+            else if (mreq_write == 1'b1) begin
+                if (tstate_r[1] || tstate_r[2]) begin
+                    mreq_n = 1'b0;
+                    if (tstate_r[2]) begin
+                        wr_n = 1'b0;
+                    end 
+                end
+            end
+            else if (iorq_read == 1'b1) begin
+                if (tstate_rr[1] || tstate_r[2]) begin
+                    iorq_n = 1'b0;
+                    rd_n = 1'b0;
+                end
+            end
+            else if (iorq_write == 1'b1) begin
+                if (tstate_rr[1] || tstate_r[2]) begin
+                    iorq_n = 1'b0;
+                    wr_n = 1'b0;
+                end
+            end
+        end
+    end
 
     always @(posedge clk) begin
         if (!reset_n) begin
@@ -164,4 +175,3 @@ module tv80n (/*AUTOARG*/
     end // always @ (posedge clk)
   
 endmodule // t80n
-
diff --git a/cores/SamCoupe/vga_scandoubler.v b/cores/SamCoupe/vga_scandoubler.v
new file mode 100644
index 0000000..844bb04
--- /dev/null
+++ b/cores/SamCoupe/vga_scandoubler.v
@@ -0,0 +1,207 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:57:54 11/09/2015 
+// Design Name: 
+// Module Name:    vga_scandoubler 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module vga_scandoubler (
+	input wire clkvideo,
+	input wire clkvga,
+    input wire enable_scandoubling,
+    input wire disable_scaneffect,  // 1 to disable scanlines
+	input wire [2:0] ri,
+	input wire [2:0] gi,
+	input wire [2:0] bi,
+	input wire hsync_ext_n,
+	input wire vsync_ext_n,
+	output reg [2:0] ro,
+	output reg [2:0] go,
+	output reg [2:0] bo,
+	output reg hsync,
+	output reg vsync
+   );
+	
+	parameter [31:0] CLKVIDEO = 12000;
+	
+	// http://www.epanorama.net/faq/vga2rgb/calc.html
+	// SVGA 800x600
+	// HSYNC = 3.36us  VSYNC = 114.32us
+	
+	parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
+	parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
+	
+	reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
+	reg [9:0] totalhor = 10'd0;
+
+	wire [2:0] rout, gout, bout;
+	// Memoria de doble puerto que guarda la información de dos scans
+	// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
+	// puntos en negro que se pintan durante el HBlank
+	vgascanline_dport memscan (
+		.clk(clkvga),
+		.addrwrite(addrvideo),
+		.addrread(addrvga),
+		.we(1'b1),
+		.din({ri,gi,bi}),
+		.dout({rout,gout,bout})
+	);
+
+	// Para generar scanlines:
+	reg scaneffect = 1'b0;
+    wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
+    color_dimmed apply_to_red   (rout, rout_dimmed);
+    color_dimmed apply_to_green (gout, gout_dimmed);
+    color_dimmed apply_to_blue  (bout, bout_dimmed);
+	wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
+	wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
+	wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
+		
+	// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
+	// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
+	// En "totalhor" mido el número de ciclos de reloj que hay en un scan
+	always @(posedge clkvideo) begin
+//        if (vsync_ext_n == 1'b0) begin
+//            addrvideo <= 11'd0;
+//        end    
+		if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
+			totalhor <= addrvideo[9:0];
+			addrvideo <= {~addrvideo[10],10'b0000000000};
+		end
+		else
+			addrvideo <= addrvideo + 11'd1;
+	end
+	
+	// Recorro el scanbuffer al doble de velocidad, generando direcciones para
+	// el scan buffer. Cada vez que el video original ha terminado una linea,
+	// cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
+	// estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
+	// desde el mismo origen
+	// Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
+	// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
+	// reducido para un efecto chachi de scanlines en la VGA
+	always @(posedge clkvga) begin
+//        if (vsync_ext_n == 1'b0) begin
+//            addrvga <= 11'b10000000000;
+//            scaneffect <= 1'b0;
+//        end    
+		if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
+			addrvga <= {addrvga[10], 10'b000000000};
+			scaneffect <= ~scaneffect;
+		end
+		else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
+			addrvga <= {~addrvga[10],10'b000000000};
+			scaneffect <= ~scaneffect;
+		end
+		else
+			addrvga <= addrvga + 11'd1;
+	end
+
+	// El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
+	// del barrido de un scanline
+    reg hsync_vga, vsync_vga;
+    
+	always @* begin
+		if (addrvga[9:0] < HSYNC_COUNT[9:0])
+			hsync_vga = 1'b0;
+		else
+			hsync_vga = 1'b1;
+	end
+	
+	// El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
+	// bajada de la señal de sincronismo vertical original
+	reg [15:0] cntvsync = 16'hFFFF;
+	initial vsync_vga = 1'b1;
+	always @(posedge clkvga) begin
+		if (vsync_ext_n == 1'b0) begin
+			if (cntvsync == 16'hFFFF) begin
+				cntvsync <= 16'd0;
+				vsync_vga <= 1'b0;
+			end
+			else if (cntvsync != 16'hFFFE) begin
+				if (cntvsync == VSYNC_COUNT[15:0]) begin
+					vsync_vga <= 1'b1;
+					cntvsync <= 16'hFFFE;
+				end
+				else
+					cntvsync <= cntvsync + 16'd1;
+			end
+		end
+		else if (vsync_ext_n == 1'b1)
+			cntvsync <= 16'hFFFF;
+	end
+
+    always @* begin
+        if (enable_scandoubling == 1'b0) begin // 15kHz output
+            ro = ri;
+            go = gi;
+            bo = bi;
+            hsync = hsync_ext_n ^ ~vsync_ext_n;
+            vsync = 1'b1;
+        end
+        else begin  // VGA output
+            ro = ro_vga;
+            go = go_vga;
+            bo = bo_vga;
+            hsync = hsync_vga;
+            vsync = vsync_vga;
+        end
+    end
+    
+endmodule
+
+// Una memoria de doble puerto: uno para leer, y otro para
+// escribir. Es de 2048 direcciones: 1024 se emplean para
+// guardar un scan, y otros 1024 para el siguiente scan
+module vgascanline_dport (
+	input wire clk,
+	input wire [10:0] addrwrite,
+	input wire [10:0] addrread,
+	input wire we,
+	input wire [8:0] din,
+	output reg [8:0] dout
+	);
+	
+	reg [8:0] scan[0:2047]; // two scanlines
+	always @(posedge clk) begin
+		dout <= scan[addrread];
+		if (we == 1'b1)
+			scan[addrwrite] <= din;
+	end
+endmodule
+
+module color_dimmed (
+    input wire [2:0] in,
+    output reg [2:0] out // out is scaled to roughly 70% of in
+    );
+    
+    always @* begin  // a LUT
+        case (in)  
+            3'd0 : out = 3'd0;
+            3'd1 : out = 3'd1;
+            3'd2 : out = 3'd1;
+            3'd3 : out = 3'd2;
+            3'd4 : out = 3'd3;
+            3'd5 : out = 3'd3;
+            3'd6 : out = 3'd4;
+            3'd7 : out = 3'd5;
+            default: out = 3'd0;
+        endcase
+    end
+endmodule
+        
\ No newline at end of file