From 79befe6f6b70b24bd424fa33826ca138ad1f3203 Mon Sep 17 00:00:00 2001 From: byrtolet Date: Sat, 17 Nov 2018 18:29:26 +0200 Subject: [PATCH] Fixed visual glitches & timer quirck --- cores/Oric/source/m6522.vhd | 8 +++++++- cores/Oric/source/ula.vhd | 7 ++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/cores/Oric/source/m6522.vhd b/cores/Oric/source/m6522.vhd index e40e5d5..104b143 100644 --- a/cores/Oric/source/m6522.vhd +++ b/cores/Oric/source/m6522.vhd @@ -200,7 +200,13 @@ begin if (p2_h_t1 = '0') and (I_P2_H = '1') then phase <= "11"; else - phase <= phase + "1"; + case phase is + when "00" => phase <= "01"; + when "01" => phase <= "10"; + when "10" => phase <= "11"; + when "11" => phase <= "00"; + when others => null; + end case; end if; end if; end process; diff --git a/cores/Oric/source/ula.vhd b/cores/Oric/source/ula.vhd index 2a51526..ea0dbe9 100644 --- a/cores/Oric/source/ula.vhd +++ b/cores/Oric/source/ula.vhd @@ -295,7 +295,10 @@ begin CLK_1_INT <= ph(2); -- VIA 6522 clock - CLK_4_INT <= c(0) or c(1) or c(2) or c(6) or c(7) or c(8) or c(12) or c(13) or c(14) or c(18) or c(19) or c(20); + CLK_4_INT <= c(23) or c(0) or c(1) + or c(5) or c(6) or c(7) + or c(11) or c(12) or c(13) + or c(17) or c(18) or c(19); -- LD_REG_0 <= isAttrib and c(5); @@ -413,6 +416,8 @@ begin IsATTRIB <= not (DB_INT(6) or DB_INT(5)); -- 1 = attribute, 0 = not an attribute lATTRIBHOLD <= DB_INT(6 downto 0); lInv_hold <= DB_INT(7); + elsif (ATTRIB_DEC = '1') then + IsATTRIB <= '0'; end if; end if; end process;