diff --git a/cores/Spectrum/audio_management.v b/cores/Spectrum/audio_management.v index 0d68da9..86c427e 100644 --- a/cores/Spectrum/audio_management.v +++ b/cores/Spectrum/audio_management.v @@ -23,64 +23,64 @@ //This is a Delta-Sigma Digital to Analog Converter module dac (DACout, DACin, Clk, Reset); - output DACout; // This is the average output that feeds low pass filter - input [`MSBI:0] DACin; // DAC input (excess 2**MSBI) - input Clk; - input Reset; + output DACout; // This is the average output that feeds low pass filter + input [`MSBI:0] DACin; // DAC input (excess 2**MSBI) + input Clk; + input Reset; - reg DACout; // for optimum performance, ensure that this ff is in IOB - reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder - reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder - reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder - reg [`MSBI+2:0] DeltaB; // B input of Delta adder + reg DACout; // for optimum performance, ensure that this ff is in IOB + reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder + reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder + reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder + reg [`MSBI+2:0] DeltaB; // B input of Delta adder - always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1); - always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB; - always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch; - always @(posedge Clk or posedge Reset) - begin - if(Reset) - begin - SigmaLatch <= #1 1'b1 << (`MSBI+1); - DACout <= #1 1'b0; - end - else - begin - SigmaLatch <= #1 SigmaAdder; - DACout <= #1 SigmaLatch[`MSBI+2]; - end - end + always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1); + always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB; + always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch; + always @(posedge Clk or posedge Reset) + begin + if(Reset) + begin + SigmaLatch <= #1 1'b1 << (`MSBI+1); + DACout <= #1 1'b0; + end + else + begin + SigmaLatch <= #1 SigmaAdder; + DACout <= #1 SigmaLatch[`MSBI+2]; + end + end endmodule module mixer ( - input wire clkdac, - input wire reset, - input wire ear, - input wire mic, - input wire spk, - input wire [7:0] ay1, - input wire [7:0] ay2, - output wire audio - ); + input wire clkdac, + input wire reset, + input wire ear, + input wire mic, + input wire spk, + input wire [7:0] ay1, + input wire [7:0] ay2, + output wire audio + ); + + reg [9:0] mezcla = 10'h000; + wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 : + ({ear,spk,mic}==3'b001)? 8'd36 : + ({ear,spk,mic}==3'b010)? 8'd184 : + ({ear,spk,mic}==3'b011)? 8'd192 : + ({ear,spk,mic}==3'b100)? 8'd22 : + ({ear,spk,mic}==3'b101)? 8'd48 : + ({ear,spk,mic}==3'b110)? 8'd244 : 8'd255; - reg [9:0] mezcla = 10'h000; - wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 : - ({ear,spk,mic}==3'b001)? 8'd36 : - ({ear,spk,mic}==3'b010)? 8'd184 : - ({ear,spk,mic}==3'b011)? 8'd192 : - ({ear,spk,mic}==3'b100)? 8'd22 : - ({ear,spk,mic}==3'b101)? 8'd48 : - ({ear,spk,mic}==3'b110)? 8'd244 : 8'd255; - wire [9:0] mezcla10bits = {2'b00,ay1} + {2'b00,ay2} + {2'b00,beeper} ; - - always @(posedge clkdac) - mezcla <= mezcla10bits; - dac audio_dac ( - .DACout(audio), - .DACin(mezcla), - .Clk(clkdac), - .Reset(reset) - ); + always @(posedge clkdac) + mezcla <= mezcla10bits; + + dac audio_dac ( + .DACout(audio), + .DACin(mezcla), + .Clk(clkdac), + .Reset(reset) + ); endmodule diff --git a/cores/Spectrum/coreid.v b/cores/Spectrum/coreid.v index 8218390..06b5ec3 100644 --- a/cores/Spectrum/coreid.v +++ b/cores/Spectrum/coreid.v @@ -37,16 +37,16 @@ module coreid ( text[i] = 8'h00; text[ 0] = "T"; text[ 1] = "2"; - text[ 2] = "0"; + text[ 2] = "1"; text[ 3] = "-"; text[ 4] = "0"; - text[ 5] = "7"; - text[ 6] = "1"; - text[ 7] = "2"; + text[ 5] = "5"; + text[ 6] = "0"; + text[ 7] = "5"; text[ 8] = "2"; text[ 9] = "0"; text[10] = "1"; - text[11] = "5"; + text[11] = "6"; end reg [3:0] textindx = 4'h0; diff --git a/cores/Spectrum/pll_drp.v b/cores/Spectrum/pll_drp.v index 41be9f7..9a305bd 100644 --- a/cores/Spectrum/pll_drp.v +++ b/cores/Spectrum/pll_drp.v @@ -29,10 +29,10 @@ // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // PURPOSE. -// +// // (c) Copyright 2008 Xilinx, Inc. // All rights reserved. -// +// /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps @@ -46,7 +46,7 @@ module pll_drp // 50 Hz, Salida RGB/VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -59,16 +59,16 @@ module pll_drp parameter S1_CLKFBOUT_MULT = 9, parameter S1_CLKFBOUT_PHASE = 0, - // The bandwidth parameter effects the phase error and the jitter filter + // The bandwidth parameter effects the phase error and the jitter filter // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S1_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S1_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -108,7 +108,7 @@ module pll_drp // State 2 Parameters - These are for the second reconfiguration state. // 51 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -125,12 +125,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S2_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S2_DIVCLK_DIVIDE = 1, - - // The following parameters describe the configuration that each clock + + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -139,21 +139,21 @@ module pll_drp // _PHASE: This is the phase multiplied by 1000. For example if // a phase of 24.567 deg was desired the input value would be // 24567. The range for the phase is from -360000 to 360000 - // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // _DUTY: This is the duty cycle multiplied by 100,000. For example if // a duty cycle of .24567 was desired the input would be // 24567. parameter S2_CLKOUT0_DIVIDE = 14, parameter S2_CLKOUT0_PHASE = 0, parameter S2_CLKOUT0_DUTY = 50000, - + parameter S2_CLKOUT1_DIVIDE = 28, parameter S2_CLKOUT1_PHASE = 0, parameter S2_CLKOUT1_DUTY = 50000, - + parameter S2_CLKOUT2_DIVIDE = 56, parameter S2_CLKOUT2_PHASE = 0, parameter S2_CLKOUT2_DUTY = 50000, - + parameter S2_CLKOUT3_DIVIDE = 112, parameter S2_CLKOUT3_PHASE = 0, parameter S2_CLKOUT3_DUTY = 50000, @@ -170,7 +170,7 @@ module pll_drp // State 3 Parameters - These are for the second reconfiguration state. // 53.50 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -187,12 +187,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S3_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S3_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -232,7 +232,7 @@ module pll_drp // State 4 Parameters - These are for the second reconfiguration state. // 55.80 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -249,12 +249,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S4_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S4_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -294,7 +294,7 @@ module pll_drp // State 5 Parameters - These are for the second reconfiguration state. // 57.39 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -311,12 +311,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S5_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S5_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -356,7 +356,7 @@ module pll_drp // State 6 Parameters - These are for the second reconfiguration state. // 59.52 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -373,12 +373,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S6_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S6_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -418,7 +418,7 @@ module pll_drp // State 7 Parameters - These are for the second reconfiguration state. // 61.8 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -435,12 +435,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S7_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S7_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -480,7 +480,7 @@ module pll_drp // State 8 Parameters - These are for the second reconfiguration state. // 63.77 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -497,12 +497,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S8_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S8_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -580,84 +580,84 @@ module pll_drp // Integer used to initialize remainder of unused ROM integer ii; - + // Pass SCLK to DCLK for the PLL assign DCLK = SCLK; // include the PLL reconfiguration functions. This contains the constant // functions that are used in the calculations below. This file is // required. `include "pll_drp_func.h" - + //************************************************************************** // State 1 Calculations //************************************************************************** localparam [22:0] S1_CLKFBOUT = s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); - + localparam [22:0] S1_CLKFBOUT2 = s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); - - localparam [9:0] S1_DIGITAL_FILT = + + localparam [9:0] S1_DIGITAL_FILT = s6_pll_filter_lookup(S1_CLKFBOUT_MULT, S1_BANDWIDTH); - + localparam [39:0] S1_LOCK = s6_pll_lock_lookup(S1_CLKFBOUT_MULT); - - localparam [22:0] S1_DIVCLK = - s6_pll_count_calc(S1_DIVCLK_DIVIDE, 0, 50000); - + + localparam [22:0] S1_DIVCLK = + s6_pll_count_calc(S1_DIVCLK_DIVIDE, 0, 50000); + localparam [22:0] S1_CLKOUT0 = - s6_pll_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY); - - localparam [22:0] S1_CLKOUT1 = - s6_pll_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY); - - localparam [22:0] S1_CLKOUT2 = - s6_pll_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY); - - localparam [22:0] S1_CLKOUT3 = - s6_pll_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY); - - localparam [22:0] S1_CLKOUT4 = - s6_pll_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY); - - localparam [22:0] S1_CLKOUT5 = - s6_pll_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY); - + s6_pll_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY); + + localparam [22:0] S1_CLKOUT1 = + s6_pll_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY); + + localparam [22:0] S1_CLKOUT2 = + s6_pll_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY); + + localparam [22:0] S1_CLKOUT3 = + s6_pll_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY); + + localparam [22:0] S1_CLKOUT4 = + s6_pll_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY); + + localparam [22:0] S1_CLKOUT5 = + s6_pll_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY); + //************************************************************************** // State 2 Calculations //************************************************************************** - localparam [22:0] S2_CLKFBOUT = + localparam [22:0] S2_CLKFBOUT = s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); - - localparam [22:0] S2_CLKFBOUT2 = + + localparam [22:0] S2_CLKFBOUT2 = s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); - - localparam [9:0] S2_DIGITAL_FILT = + + localparam [9:0] S2_DIGITAL_FILT = s6_pll_filter_lookup(S2_CLKFBOUT_MULT, S2_BANDWIDTH); - - localparam [39:0] S2_LOCK = + + localparam [39:0] S2_LOCK = s6_pll_lock_lookup(S2_CLKFBOUT_MULT); - - localparam [22:0] S2_DIVCLK = + + localparam [22:0] S2_DIVCLK = s6_pll_count_calc(S2_DIVCLK_DIVIDE, 0, 50000); - - localparam [22:0] S2_CLKOUT0 = + + localparam [22:0] S2_CLKOUT0 = s6_pll_count_calc(S2_CLKOUT0_DIVIDE, S2_CLKOUT0_PHASE, S2_CLKOUT0_DUTY); - localparam [22:0] S2_CLKOUT1 = + localparam [22:0] S2_CLKOUT1 = s6_pll_count_calc(S2_CLKOUT1_DIVIDE, S2_CLKOUT1_PHASE, S2_CLKOUT1_DUTY); - - localparam [22:0] S2_CLKOUT2 = + + localparam [22:0] S2_CLKOUT2 = s6_pll_count_calc(S2_CLKOUT2_DIVIDE, S2_CLKOUT2_PHASE, S2_CLKOUT2_DUTY); - - localparam [22:0] S2_CLKOUT3 = + + localparam [22:0] S2_CLKOUT3 = s6_pll_count_calc(S2_CLKOUT3_DIVIDE, S2_CLKOUT3_PHASE, S2_CLKOUT3_DUTY); - - localparam [22:0] S2_CLKOUT4 = + + localparam [22:0] S2_CLKOUT4 = s6_pll_count_calc(S2_CLKOUT4_DIVIDE, S2_CLKOUT4_PHASE, S2_CLKOUT4_DUTY); - - localparam [22:0] S2_CLKOUT5 = + + localparam [22:0] S2_CLKOUT5 = s6_pll_count_calc(S2_CLKOUT5_DIVIDE, S2_CLKOUT5_PHASE, S2_CLKOUT5_DUTY); //************************************************************************** @@ -881,644 +881,644 @@ module pll_drp //*********************************************************************** // State 1 Initialization //*********************************************************************** - + rom[0] = {5'h05, 16'h50FF, S1_CLKOUT0[19], 1'b0, S1_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S1_CLKOUT0[16], S1_CLKOUT0[17], S1_CLKOUT0[15], S1_CLKOUT0[14], 8'h00};//bits 11 downto 0 - - rom[1] = {5'h06, 16'h010B, S1_CLKOUT1[4], S1_CLKOUT1[5], S1_CLKOUT1[3], S1_CLKOUT1[12], //bits 15 down to 12 - S1_CLKOUT1[1], S1_CLKOUT1[2], S1_CLKOUT1[19], 1'b0, S1_CLKOUT1[17], S1_CLKOUT1[16], //bits 11 down to 6 - S1_CLKOUT1[14], S1_CLKOUT1[15], 1'b0, S1_CLKOUT0[13], 2'b00}; //bits 5 down to 0 - - rom[2] = {5'h07, 16'hE02C, 3'b000, S1_CLKOUT1[11], S1_CLKOUT1[9], S1_CLKOUT1[10], //bits 15 down to 10 - S1_CLKOUT1[8], S1_CLKOUT1[7], S1_CLKOUT1[6], S1_CLKOUT1[20], 1'b0, S1_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S1_CLKOUT1[21], S1_CLKOUT1[22]}; //bits 3 down to 0 - - rom[3] = {5'h08, 16'h4001, S1_CLKOUT2[22], 1'b0, S1_CLKOUT2[5], S1_CLKOUT2[21], //bits 15 downto 12 - S1_CLKOUT2[12], S1_CLKOUT2[4], S1_CLKOUT2[3], S1_CLKOUT2[2], S1_CLKOUT2[0], S1_CLKOUT2[19], //bits 11 down to 6 - S1_CLKOUT2[17], S1_CLKOUT2[18], S1_CLKOUT2[15], S1_CLKOUT2[16], S1_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - - rom[4] = {5'h09, 16'h0D03, S1_CLKOUT3[14], S1_CLKOUT3[15], S1_CLKOUT0[21], S1_CLKOUT0[22], 2'b00, S1_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S1_CLKOUT2[9], S1_CLKOUT2[8], S1_CLKOUT2[6], S1_CLKOUT2[7], S1_CLKOUT2[13], S1_CLKOUT2[20], 2'b00}; //bits 7 downto 0 - - rom[5] = {5'h0A, 16'hB001, 1'b0, S1_CLKOUT3[13], 2'b00, S1_CLKOUT3[21], S1_CLKOUT3[22], S1_CLKOUT3[5], S1_CLKOUT3[4], //bits 15 downto 8 - S1_CLKOUT3[12], S1_CLKOUT3[2], S1_CLKOUT3[0], S1_CLKOUT3[1], S1_CLKOUT3[18], S1_CLKOUT3[19], //bits 7 downto 2 - S1_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - - rom[6] = {5'h0B, 16'h0110, S1_CLKOUT0[5], S1_CLKOUT4[19], S1_CLKOUT4[14], S1_CLKOUT4[17], //bits 15 downto 12 - S1_CLKOUT4[15], S1_CLKOUT4[16], S1_CLKOUT0[4], 1'b0, S1_CLKOUT3[11], S1_CLKOUT3[10], //bits 11 downto 6 - S1_CLKOUT3[9], 1'b0, S1_CLKOUT3[7], S1_CLKOUT3[8], S1_CLKOUT3[20], S1_CLKOUT3[6]}; //bits 5 downto 0 - - rom[7] = {5'h0C, 16'h0B00, S1_CLKOUT4[7], S1_CLKOUT4[8], S1_CLKOUT4[20], S1_CLKOUT4[6], 1'b0, S1_CLKOUT4[13], //bits 15 downto 10 - 2'b00, S1_CLKOUT4[22], S1_CLKOUT4[21], S1_CLKOUT4[4], S1_CLKOUT4[5], S1_CLKOUT4[3], //bits 9 downto 3 - S1_CLKOUT4[12], S1_CLKOUT4[1], S1_CLKOUT4[2]}; //bits 2 downto 0 - - rom[8] = {5'h0D, 16'h0008, S1_CLKOUT5[2], S1_CLKOUT5[3], S1_CLKOUT5[0], S1_CLKOUT5[1], S1_CLKOUT5[18], //bits 15 downto 11 - S1_CLKOUT5[19], S1_CLKOUT5[17], S1_CLKOUT5[16], S1_CLKOUT5[15], S1_CLKOUT0[3], //bits 10 downto 6 - S1_CLKOUT0[0], S1_CLKOUT0[2], 1'b0, S1_CLKOUT4[11], S1_CLKOUT4[9], S1_CLKOUT4[10]}; //bits 5 downto 0 - - rom[9] = {5'h0E, 16'h00D0, S1_CLKOUT5[10], S1_CLKOUT5[11], S1_CLKOUT5[8], S1_CLKOUT5[9], S1_CLKOUT5[6], //bits 15 downto 11 - S1_CLKOUT5[7], S1_CLKOUT5[20], S1_CLKOUT5[13], 2'b00, S1_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S1_CLKOUT5[5], S1_CLKOUT5[21], S1_CLKOUT5[12], S1_CLKOUT5[4]}; //bits 3 downto 0 - - rom[10] = {5'h0F, 16'h0003, S1_CLKFBOUT[4], S1_CLKFBOUT[5], S1_CLKFBOUT[3], S1_CLKFBOUT[12], S1_CLKFBOUT[1], //bits 15 downto 11 - S1_CLKFBOUT[2], S1_CLKFBOUT[0], S1_CLKFBOUT[19], S1_CLKFBOUT[18], S1_CLKFBOUT[17], //bits 10 downto 6 - S1_CLKFBOUT[15], S1_CLKFBOUT[16], S1_CLKOUT0[12], S1_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - - rom[11] = {5'h10, 16'h800C, 1'b0, S1_CLKOUT0[9], S1_CLKOUT0[11], S1_CLKOUT0[10], S1_CLKFBOUT[10], S1_CLKFBOUT[11], //bits 15 downto 10 - S1_CLKFBOUT[9], S1_CLKFBOUT[8], S1_CLKFBOUT[7], S1_CLKFBOUT[6], S1_CLKFBOUT[13], //bits 9 downto 5 - S1_CLKFBOUT[20], 2'b00, S1_CLKFBOUT[21], S1_CLKFBOUT[22]}; //bits 4 downto 0 - - rom[12] = {5'h11, 16'hFC00, 6'h00, S1_CLKOUT3[3], S1_CLKOUT3[16], S1_CLKOUT2[11], S1_CLKOUT2[1], S1_CLKOUT1[18], //bits 15 downto 6 - S1_CLKOUT1[0], S1_CLKOUT0[6], S1_CLKOUT0[20], S1_CLKOUT0[8], S1_CLKOUT0[7]}; //bits 5 downto 0 - - rom[13] = {5'h12, 16'hF0FF, 4'h0, S1_CLKOUT5[14], S1_CLKFBOUT[14], S1_CLKOUT4[0], S1_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - - rom[14] = {5'h13, 16'h5120, S1_DIVCLK[11], 1'b0, S1_DIVCLK[10], 1'b0, S1_DIVCLK[7], S1_DIVCLK[8], //bits 15 downto 10 - S1_DIVCLK[0], 1'b0, S1_DIVCLK[5], S1_DIVCLK[2], 1'b0, S1_DIVCLK[13], 4'h0}; //bits 9 downto 0 - - rom[15] = {5'h14, 16'h2FFF, S1_LOCK[1], S1_LOCK[2], 1'b0, S1_LOCK[0], 12'h000}; //bits 15 downto 0 - - rom[16] = {5'h15, 16'hBFF4, 1'b0, S1_DIVCLK[12], 10'h000, S1_LOCK[38], 1'b0, S1_LOCK[32], S1_LOCK[39]}; //bits 15 downto 0 - - rom[17] = {5'h16, 16'h0A55, S1_LOCK[15], S1_LOCK[13], S1_LOCK[27], S1_LOCK[16], 1'b0, S1_LOCK[10], //bits 15 downto 10 - 1'b0, S1_DIVCLK[9], S1_DIVCLK[1], 1'b0, S1_DIVCLK[6], 1'b0, S1_DIVCLK[3], //bits 9 downto 3 - 1'b0, S1_DIVCLK[4], 1'b0}; //bits 2 downto 0 - - rom[18] = {5'h17, 16'hFFD0, 10'h000, S1_LOCK[17], 1'b0, S1_LOCK[8], S1_LOCK[9], S1_LOCK[23], S1_LOCK[22]}; //bits 15 downto 0 - - rom[19] = {5'h18, 16'h1039, S1_DIGITAL_FILT[6], S1_DIGITAL_FILT[7], S1_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S1_DIGITAL_FILT[2], S1_DIGITAL_FILT[1], S1_DIGITAL_FILT[3], S1_DIGITAL_FILT[9], //bits 11 downto 8 - S1_DIGITAL_FILT[8], S1_LOCK[26], 3'h0, S1_LOCK[19], S1_LOCK[18], 1'b0}; //bits 7 downto 0 - - rom[20] = {5'h19, 16'h0000, S1_LOCK[24], S1_LOCK[25], S1_LOCK[21], S1_LOCK[14], S1_LOCK[11], //bits 15 downto 11 - S1_LOCK[12], S1_LOCK[20], S1_LOCK[6], S1_LOCK[35], S1_LOCK[36], //bits 10 downto 6 - S1_LOCK[37], S1_LOCK[3], S1_LOCK[33], S1_LOCK[31], S1_LOCK[34], S1_LOCK[30]}; //bits 5 downto 0 - - rom[21] = {5'h1A, 16'hFFFC, 14'h0000, S1_LOCK[28], S1_LOCK[29]}; //bits 15 downto 0 - - rom[22] = {5'h1D, 16'h2FFF, S1_LOCK[7], S1_LOCK[4], 1'b0, S1_LOCK[5], 12'h000}; //bits 15 downto 0 - + S1_CLKOUT0[16], S1_CLKOUT0[17], S1_CLKOUT0[15], S1_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[1] = {5'h06, 16'h010B, S1_CLKOUT1[4], S1_CLKOUT1[5], S1_CLKOUT1[3], S1_CLKOUT1[12], //bits 15 down to 12 + S1_CLKOUT1[1], S1_CLKOUT1[2], S1_CLKOUT1[19], 1'b0, S1_CLKOUT1[17], S1_CLKOUT1[16], //bits 11 down to 6 + S1_CLKOUT1[14], S1_CLKOUT1[15], 1'b0, S1_CLKOUT0[13], 2'b00}; //bits 5 down to 0 + + rom[2] = {5'h07, 16'hE02C, 3'b000, S1_CLKOUT1[11], S1_CLKOUT1[9], S1_CLKOUT1[10], //bits 15 down to 10 + S1_CLKOUT1[8], S1_CLKOUT1[7], S1_CLKOUT1[6], S1_CLKOUT1[20], 1'b0, S1_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S1_CLKOUT1[21], S1_CLKOUT1[22]}; //bits 3 down to 0 + + rom[3] = {5'h08, 16'h4001, S1_CLKOUT2[22], 1'b0, S1_CLKOUT2[5], S1_CLKOUT2[21], //bits 15 downto 12 + S1_CLKOUT2[12], S1_CLKOUT2[4], S1_CLKOUT2[3], S1_CLKOUT2[2], S1_CLKOUT2[0], S1_CLKOUT2[19], //bits 11 down to 6 + S1_CLKOUT2[17], S1_CLKOUT2[18], S1_CLKOUT2[15], S1_CLKOUT2[16], S1_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[4] = {5'h09, 16'h0D03, S1_CLKOUT3[14], S1_CLKOUT3[15], S1_CLKOUT0[21], S1_CLKOUT0[22], 2'b00, S1_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S1_CLKOUT2[9], S1_CLKOUT2[8], S1_CLKOUT2[6], S1_CLKOUT2[7], S1_CLKOUT2[13], S1_CLKOUT2[20], 2'b00}; //bits 7 downto 0 + + rom[5] = {5'h0A, 16'hB001, 1'b0, S1_CLKOUT3[13], 2'b00, S1_CLKOUT3[21], S1_CLKOUT3[22], S1_CLKOUT3[5], S1_CLKOUT3[4], //bits 15 downto 8 + S1_CLKOUT3[12], S1_CLKOUT3[2], S1_CLKOUT3[0], S1_CLKOUT3[1], S1_CLKOUT3[18], S1_CLKOUT3[19], //bits 7 downto 2 + S1_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[6] = {5'h0B, 16'h0110, S1_CLKOUT0[5], S1_CLKOUT4[19], S1_CLKOUT4[14], S1_CLKOUT4[17], //bits 15 downto 12 + S1_CLKOUT4[15], S1_CLKOUT4[16], S1_CLKOUT0[4], 1'b0, S1_CLKOUT3[11], S1_CLKOUT3[10], //bits 11 downto 6 + S1_CLKOUT3[9], 1'b0, S1_CLKOUT3[7], S1_CLKOUT3[8], S1_CLKOUT3[20], S1_CLKOUT3[6]}; //bits 5 downto 0 + + rom[7] = {5'h0C, 16'h0B00, S1_CLKOUT4[7], S1_CLKOUT4[8], S1_CLKOUT4[20], S1_CLKOUT4[6], 1'b0, S1_CLKOUT4[13], //bits 15 downto 10 + 2'b00, S1_CLKOUT4[22], S1_CLKOUT4[21], S1_CLKOUT4[4], S1_CLKOUT4[5], S1_CLKOUT4[3], //bits 9 downto 3 + S1_CLKOUT4[12], S1_CLKOUT4[1], S1_CLKOUT4[2]}; //bits 2 downto 0 + + rom[8] = {5'h0D, 16'h0008, S1_CLKOUT5[2], S1_CLKOUT5[3], S1_CLKOUT5[0], S1_CLKOUT5[1], S1_CLKOUT5[18], //bits 15 downto 11 + S1_CLKOUT5[19], S1_CLKOUT5[17], S1_CLKOUT5[16], S1_CLKOUT5[15], S1_CLKOUT0[3], //bits 10 downto 6 + S1_CLKOUT0[0], S1_CLKOUT0[2], 1'b0, S1_CLKOUT4[11], S1_CLKOUT4[9], S1_CLKOUT4[10]}; //bits 5 downto 0 + + rom[9] = {5'h0E, 16'h00D0, S1_CLKOUT5[10], S1_CLKOUT5[11], S1_CLKOUT5[8], S1_CLKOUT5[9], S1_CLKOUT5[6], //bits 15 downto 11 + S1_CLKOUT5[7], S1_CLKOUT5[20], S1_CLKOUT5[13], 2'b00, S1_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S1_CLKOUT5[5], S1_CLKOUT5[21], S1_CLKOUT5[12], S1_CLKOUT5[4]}; //bits 3 downto 0 + + rom[10] = {5'h0F, 16'h0003, S1_CLKFBOUT[4], S1_CLKFBOUT[5], S1_CLKFBOUT[3], S1_CLKFBOUT[12], S1_CLKFBOUT[1], //bits 15 downto 11 + S1_CLKFBOUT[2], S1_CLKFBOUT[0], S1_CLKFBOUT[19], S1_CLKFBOUT[18], S1_CLKFBOUT[17], //bits 10 downto 6 + S1_CLKFBOUT[15], S1_CLKFBOUT[16], S1_CLKOUT0[12], S1_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[11] = {5'h10, 16'h800C, 1'b0, S1_CLKOUT0[9], S1_CLKOUT0[11], S1_CLKOUT0[10], S1_CLKFBOUT[10], S1_CLKFBOUT[11], //bits 15 downto 10 + S1_CLKFBOUT[9], S1_CLKFBOUT[8], S1_CLKFBOUT[7], S1_CLKFBOUT[6], S1_CLKFBOUT[13], //bits 9 downto 5 + S1_CLKFBOUT[20], 2'b00, S1_CLKFBOUT[21], S1_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[12] = {5'h11, 16'hFC00, 6'h00, S1_CLKOUT3[3], S1_CLKOUT3[16], S1_CLKOUT2[11], S1_CLKOUT2[1], S1_CLKOUT1[18], //bits 15 downto 6 + S1_CLKOUT1[0], S1_CLKOUT0[6], S1_CLKOUT0[20], S1_CLKOUT0[8], S1_CLKOUT0[7]}; //bits 5 downto 0 + + rom[13] = {5'h12, 16'hF0FF, 4'h0, S1_CLKOUT5[14], S1_CLKFBOUT[14], S1_CLKOUT4[0], S1_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[14] = {5'h13, 16'h5120, S1_DIVCLK[11], 1'b0, S1_DIVCLK[10], 1'b0, S1_DIVCLK[7], S1_DIVCLK[8], //bits 15 downto 10 + S1_DIVCLK[0], 1'b0, S1_DIVCLK[5], S1_DIVCLK[2], 1'b0, S1_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[15] = {5'h14, 16'h2FFF, S1_LOCK[1], S1_LOCK[2], 1'b0, S1_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[16] = {5'h15, 16'hBFF4, 1'b0, S1_DIVCLK[12], 10'h000, S1_LOCK[38], 1'b0, S1_LOCK[32], S1_LOCK[39]}; //bits 15 downto 0 + + rom[17] = {5'h16, 16'h0A55, S1_LOCK[15], S1_LOCK[13], S1_LOCK[27], S1_LOCK[16], 1'b0, S1_LOCK[10], //bits 15 downto 10 + 1'b0, S1_DIVCLK[9], S1_DIVCLK[1], 1'b0, S1_DIVCLK[6], 1'b0, S1_DIVCLK[3], //bits 9 downto 3 + 1'b0, S1_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[18] = {5'h17, 16'hFFD0, 10'h000, S1_LOCK[17], 1'b0, S1_LOCK[8], S1_LOCK[9], S1_LOCK[23], S1_LOCK[22]}; //bits 15 downto 0 + + rom[19] = {5'h18, 16'h1039, S1_DIGITAL_FILT[6], S1_DIGITAL_FILT[7], S1_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S1_DIGITAL_FILT[2], S1_DIGITAL_FILT[1], S1_DIGITAL_FILT[3], S1_DIGITAL_FILT[9], //bits 11 downto 8 + S1_DIGITAL_FILT[8], S1_LOCK[26], 3'h0, S1_LOCK[19], S1_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[20] = {5'h19, 16'h0000, S1_LOCK[24], S1_LOCK[25], S1_LOCK[21], S1_LOCK[14], S1_LOCK[11], //bits 15 downto 11 + S1_LOCK[12], S1_LOCK[20], S1_LOCK[6], S1_LOCK[35], S1_LOCK[36], //bits 10 downto 6 + S1_LOCK[37], S1_LOCK[3], S1_LOCK[33], S1_LOCK[31], S1_LOCK[34], S1_LOCK[30]}; //bits 5 downto 0 + + rom[21] = {5'h1A, 16'hFFFC, 14'h0000, S1_LOCK[28], S1_LOCK[29]}; //bits 15 downto 0 + + rom[22] = {5'h1D, 16'h2FFF, S1_LOCK[7], S1_LOCK[4], 1'b0, S1_LOCK[5], 12'h000}; //bits 15 downto 0 + //*********************************************************************** // State 2 Initialization //*********************************************************************** - + rom[23] = {5'h05, 16'h50FF, S2_CLKOUT0[19], 1'b0, S2_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S2_CLKOUT0[16], S2_CLKOUT0[17], S2_CLKOUT0[15], S2_CLKOUT0[14], 8'h00};//bits 11 downto 0 - - rom[24] = {5'h06, 16'h010B, S2_CLKOUT1[4], S2_CLKOUT1[5], S2_CLKOUT1[3], S2_CLKOUT1[12], //bits 15 down to 12 - S2_CLKOUT1[1], S2_CLKOUT1[2], S2_CLKOUT1[19], 1'b0, S2_CLKOUT1[17], S2_CLKOUT1[16], //bits 11 down to 6 - S2_CLKOUT1[14], S2_CLKOUT1[15], 1'b0, S2_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - - rom[25] = {5'h07, 16'hE02C, 3'h0, S2_CLKOUT1[11], S2_CLKOUT1[9], S2_CLKOUT1[10], //bits 15 down to 10 - S2_CLKOUT1[8], S2_CLKOUT1[7], S2_CLKOUT1[6], S2_CLKOUT1[20], 1'b0, S2_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S2_CLKOUT1[21], S2_CLKOUT1[22]}; //bits 3 down to 0 - - rom[26] = {5'h08, 16'h4001, S2_CLKOUT2[22], 1'b0, S2_CLKOUT2[5], S2_CLKOUT2[21], //bits 15 downto 12 - S2_CLKOUT2[12], S2_CLKOUT2[4], S2_CLKOUT2[3], S2_CLKOUT2[2], S2_CLKOUT2[0], S2_CLKOUT2[19], //bits 11 down to 6 - S2_CLKOUT2[17], S2_CLKOUT2[18], S2_CLKOUT2[15], S2_CLKOUT2[16], S2_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - - rom[27] = {5'h09, 16'h0D03, S2_CLKOUT3[14], S2_CLKOUT3[15], S2_CLKOUT0[21], S2_CLKOUT0[22], 2'h0, S2_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S2_CLKOUT2[9], S2_CLKOUT2[8], S2_CLKOUT2[6], S2_CLKOUT2[7], S2_CLKOUT2[13], S2_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - - rom[28] = {5'h0A, 16'hB001, 1'b0, S2_CLKOUT3[13], 2'h0, S2_CLKOUT3[21], S2_CLKOUT3[22], S2_CLKOUT3[5], S2_CLKOUT3[4], //bits 15 downto 8 - S2_CLKOUT3[12], S2_CLKOUT3[2], S2_CLKOUT3[0], S2_CLKOUT3[1], S2_CLKOUT3[18], S2_CLKOUT3[19], //bits 7 downto 2 - S2_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - - rom[29] = {5'h0B, 16'h0110, S2_CLKOUT0[5], S2_CLKOUT4[19], S2_CLKOUT4[14], S2_CLKOUT4[17], //bits 15 downto 12 - S2_CLKOUT4[15], S2_CLKOUT4[16], S2_CLKOUT0[4], 1'b0, S2_CLKOUT3[11], S2_CLKOUT3[10], //bits 11 downto 6 - S2_CLKOUT3[9], 1'b0, S2_CLKOUT3[7], S2_CLKOUT3[8], S2_CLKOUT3[20], S2_CLKOUT3[6]}; //bits 5 downto 0 - - rom[30] = {5'h0C, 16'h0B00, S2_CLKOUT4[7], S2_CLKOUT4[8], S2_CLKOUT4[20], S2_CLKOUT4[6], 1'b0, S2_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S2_CLKOUT4[22], S2_CLKOUT4[21], S2_CLKOUT4[4], S2_CLKOUT4[5], S2_CLKOUT4[3], //bits 9 downto 3 - S2_CLKOUT4[12], S2_CLKOUT4[1], S2_CLKOUT4[2]}; //bits 2 downto 0 - - rom[31] = {5'h0D, 16'h0008, S2_CLKOUT5[2], S2_CLKOUT5[3], S2_CLKOUT5[0], S2_CLKOUT5[1], S2_CLKOUT5[18], //bits 15 downto 11 - S2_CLKOUT5[19], S2_CLKOUT5[17], S2_CLKOUT5[16], S2_CLKOUT5[15], S2_CLKOUT0[3], //bits 10 downto 6 - S2_CLKOUT0[0], S2_CLKOUT0[2], 1'b0, S2_CLKOUT4[11], S2_CLKOUT4[9], S2_CLKOUT4[10]}; //bits 5 downto 0 - - rom[32] = {5'h0E, 16'h00D0, S2_CLKOUT5[10], S2_CLKOUT5[11], S2_CLKOUT5[8], S2_CLKOUT5[9], S2_CLKOUT5[6], //bits 15 downto 11 - S2_CLKOUT5[7], S2_CLKOUT5[20], S2_CLKOUT5[13], 2'h0, S2_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S2_CLKOUT5[5], S2_CLKOUT5[21], S2_CLKOUT5[12], S2_CLKOUT5[4]}; //bits 3 downto 0 - - rom[33] = {5'h0F, 16'h0003, S2_CLKFBOUT[4], S2_CLKFBOUT[5], S2_CLKFBOUT[3], S2_CLKFBOUT[12], S2_CLKFBOUT[1], //bits 15 downto 11 - S2_CLKFBOUT[2], S2_CLKFBOUT[0], S2_CLKFBOUT[19], S2_CLKFBOUT[18], S2_CLKFBOUT[17], //bits 10 downto 6 - S2_CLKFBOUT[15], S2_CLKFBOUT[16], S2_CLKOUT0[12], S2_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - - rom[34] = {5'h10, 16'h800C, 1'b0, S2_CLKOUT0[9], S2_CLKOUT0[11], S2_CLKOUT0[10], S2_CLKFBOUT[10], S2_CLKFBOUT[11], //bits 15 downto 10 - S2_CLKFBOUT[9], S2_CLKFBOUT[8], S2_CLKFBOUT[7], S2_CLKFBOUT[6], S2_CLKFBOUT[13], //bits 9 downto 5 - S2_CLKFBOUT[20], 2'h0, S2_CLKFBOUT[21], S2_CLKFBOUT[22]}; //bits 4 downto 0 - - rom[35] = {5'h11, 16'hFC00, 6'h00, S2_CLKOUT3[3], S2_CLKOUT3[16], S2_CLKOUT2[11], S2_CLKOUT2[1], S2_CLKOUT1[18], //bits 15 downto 6 - S2_CLKOUT1[0], S2_CLKOUT0[6], S2_CLKOUT0[20], S2_CLKOUT0[8], S2_CLKOUT0[7]}; //bits 5 downto 0 - - rom[36] = {5'h12, 16'hF0FF, 4'h0, S2_CLKOUT5[14], S2_CLKFBOUT[14], S2_CLKOUT4[0], S2_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + S2_CLKOUT0[16], S2_CLKOUT0[17], S2_CLKOUT0[15], S2_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[37] = {5'h13, 16'h5120, S2_DIVCLK[11], 1'b0, S2_DIVCLK[10], 1'b0, S2_DIVCLK[7], S2_DIVCLK[8], //bits 15 downto 10 - S2_DIVCLK[0], 1'b0, S2_DIVCLK[5], S2_DIVCLK[2], 1'b0, S2_DIVCLK[13], 4'h0}; //bits 9 downto 0 - - rom[38] = {5'h14, 16'h2FFF, S2_LOCK[1], S2_LOCK[2], 1'b0, S2_LOCK[0], 12'h000}; //bits 15 downto 0 - - rom[39] = {5'h15, 16'hBFF4, 1'b0, S2_DIVCLK[12], 10'h000, S2_LOCK[38], 1'b0, S2_LOCK[32], S2_LOCK[39]}; //bits 15 downto 0 - - rom[40] = {5'h16, 16'h0A55, S2_LOCK[15], S2_LOCK[13], S2_LOCK[27], S2_LOCK[16], 1'b0, S2_LOCK[10], //bits 15 downto 10 - 1'b0, S2_DIVCLK[9], S2_DIVCLK[1], 1'b0, S2_DIVCLK[6], 1'b0, S2_DIVCLK[3], //bits 9 downto 3 - 1'b0, S2_DIVCLK[4], 1'b0}; //bits 2 downto 0 - - rom[41] = {5'h17, 16'hFFD0, 10'h000, S2_LOCK[17], 1'b0, S2_LOCK[8], S2_LOCK[9], S2_LOCK[23], S2_LOCK[22]}; //bits 15 downto 0 - - rom[42] = {5'h18, 16'h1039, S2_DIGITAL_FILT[6], S2_DIGITAL_FILT[7], S2_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S2_DIGITAL_FILT[2], S2_DIGITAL_FILT[1], S2_DIGITAL_FILT[3], S2_DIGITAL_FILT[9], //bits 11 downto 8 - S2_DIGITAL_FILT[8], S2_LOCK[26], 3'h0, S2_LOCK[19], S2_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[24] = {5'h06, 16'h010B, S2_CLKOUT1[4], S2_CLKOUT1[5], S2_CLKOUT1[3], S2_CLKOUT1[12], //bits 15 down to 12 + S2_CLKOUT1[1], S2_CLKOUT1[2], S2_CLKOUT1[19], 1'b0, S2_CLKOUT1[17], S2_CLKOUT1[16], //bits 11 down to 6 + S2_CLKOUT1[14], S2_CLKOUT1[15], 1'b0, S2_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[43] = {5'h19, 16'h0000, S2_LOCK[24], S2_LOCK[25], S2_LOCK[21], S2_LOCK[14], S2_LOCK[11], //bits 15 downto 11 - S2_LOCK[12], S2_LOCK[20], S2_LOCK[6], S2_LOCK[35], S2_LOCK[36], //bits 10 downto 6 - S2_LOCK[37], S2_LOCK[3], S2_LOCK[33], S2_LOCK[31], S2_LOCK[34], S2_LOCK[30]}; //bits 5 downto 0 + rom[25] = {5'h07, 16'hE02C, 3'h0, S2_CLKOUT1[11], S2_CLKOUT1[9], S2_CLKOUT1[10], //bits 15 down to 10 + S2_CLKOUT1[8], S2_CLKOUT1[7], S2_CLKOUT1[6], S2_CLKOUT1[20], 1'b0, S2_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S2_CLKOUT1[21], S2_CLKOUT1[22]}; //bits 3 down to 0 - rom[44] = {5'h1A, 16'hFFFC, 14'h0000, S2_LOCK[28], S2_LOCK[29]}; //bits 15 downto 0 + rom[26] = {5'h08, 16'h4001, S2_CLKOUT2[22], 1'b0, S2_CLKOUT2[5], S2_CLKOUT2[21], //bits 15 downto 12 + S2_CLKOUT2[12], S2_CLKOUT2[4], S2_CLKOUT2[3], S2_CLKOUT2[2], S2_CLKOUT2[0], S2_CLKOUT2[19], //bits 11 down to 6 + S2_CLKOUT2[17], S2_CLKOUT2[18], S2_CLKOUT2[15], S2_CLKOUT2[16], S2_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[45] = {5'h1D, 16'h2FFF, S2_LOCK[7], S2_LOCK[4], 1'b0, S2_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[27] = {5'h09, 16'h0D03, S2_CLKOUT3[14], S2_CLKOUT3[15], S2_CLKOUT0[21], S2_CLKOUT0[22], 2'h0, S2_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S2_CLKOUT2[9], S2_CLKOUT2[8], S2_CLKOUT2[6], S2_CLKOUT2[7], S2_CLKOUT2[13], S2_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[28] = {5'h0A, 16'hB001, 1'b0, S2_CLKOUT3[13], 2'h0, S2_CLKOUT3[21], S2_CLKOUT3[22], S2_CLKOUT3[5], S2_CLKOUT3[4], //bits 15 downto 8 + S2_CLKOUT3[12], S2_CLKOUT3[2], S2_CLKOUT3[0], S2_CLKOUT3[1], S2_CLKOUT3[18], S2_CLKOUT3[19], //bits 7 downto 2 + S2_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[29] = {5'h0B, 16'h0110, S2_CLKOUT0[5], S2_CLKOUT4[19], S2_CLKOUT4[14], S2_CLKOUT4[17], //bits 15 downto 12 + S2_CLKOUT4[15], S2_CLKOUT4[16], S2_CLKOUT0[4], 1'b0, S2_CLKOUT3[11], S2_CLKOUT3[10], //bits 11 downto 6 + S2_CLKOUT3[9], 1'b0, S2_CLKOUT3[7], S2_CLKOUT3[8], S2_CLKOUT3[20], S2_CLKOUT3[6]}; //bits 5 downto 0 + + rom[30] = {5'h0C, 16'h0B00, S2_CLKOUT4[7], S2_CLKOUT4[8], S2_CLKOUT4[20], S2_CLKOUT4[6], 1'b0, S2_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S2_CLKOUT4[22], S2_CLKOUT4[21], S2_CLKOUT4[4], S2_CLKOUT4[5], S2_CLKOUT4[3], //bits 9 downto 3 + S2_CLKOUT4[12], S2_CLKOUT4[1], S2_CLKOUT4[2]}; //bits 2 downto 0 + + rom[31] = {5'h0D, 16'h0008, S2_CLKOUT5[2], S2_CLKOUT5[3], S2_CLKOUT5[0], S2_CLKOUT5[1], S2_CLKOUT5[18], //bits 15 downto 11 + S2_CLKOUT5[19], S2_CLKOUT5[17], S2_CLKOUT5[16], S2_CLKOUT5[15], S2_CLKOUT0[3], //bits 10 downto 6 + S2_CLKOUT0[0], S2_CLKOUT0[2], 1'b0, S2_CLKOUT4[11], S2_CLKOUT4[9], S2_CLKOUT4[10]}; //bits 5 downto 0 + + rom[32] = {5'h0E, 16'h00D0, S2_CLKOUT5[10], S2_CLKOUT5[11], S2_CLKOUT5[8], S2_CLKOUT5[9], S2_CLKOUT5[6], //bits 15 downto 11 + S2_CLKOUT5[7], S2_CLKOUT5[20], S2_CLKOUT5[13], 2'h0, S2_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S2_CLKOUT5[5], S2_CLKOUT5[21], S2_CLKOUT5[12], S2_CLKOUT5[4]}; //bits 3 downto 0 + + rom[33] = {5'h0F, 16'h0003, S2_CLKFBOUT[4], S2_CLKFBOUT[5], S2_CLKFBOUT[3], S2_CLKFBOUT[12], S2_CLKFBOUT[1], //bits 15 downto 11 + S2_CLKFBOUT[2], S2_CLKFBOUT[0], S2_CLKFBOUT[19], S2_CLKFBOUT[18], S2_CLKFBOUT[17], //bits 10 downto 6 + S2_CLKFBOUT[15], S2_CLKFBOUT[16], S2_CLKOUT0[12], S2_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[34] = {5'h10, 16'h800C, 1'b0, S2_CLKOUT0[9], S2_CLKOUT0[11], S2_CLKOUT0[10], S2_CLKFBOUT[10], S2_CLKFBOUT[11], //bits 15 downto 10 + S2_CLKFBOUT[9], S2_CLKFBOUT[8], S2_CLKFBOUT[7], S2_CLKFBOUT[6], S2_CLKFBOUT[13], //bits 9 downto 5 + S2_CLKFBOUT[20], 2'h0, S2_CLKFBOUT[21], S2_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[35] = {5'h11, 16'hFC00, 6'h00, S2_CLKOUT3[3], S2_CLKOUT3[16], S2_CLKOUT2[11], S2_CLKOUT2[1], S2_CLKOUT1[18], //bits 15 downto 6 + S2_CLKOUT1[0], S2_CLKOUT0[6], S2_CLKOUT0[20], S2_CLKOUT0[8], S2_CLKOUT0[7]}; //bits 5 downto 0 + + rom[36] = {5'h12, 16'hF0FF, 4'h0, S2_CLKOUT5[14], S2_CLKFBOUT[14], S2_CLKOUT4[0], S2_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[37] = {5'h13, 16'h5120, S2_DIVCLK[11], 1'b0, S2_DIVCLK[10], 1'b0, S2_DIVCLK[7], S2_DIVCLK[8], //bits 15 downto 10 + S2_DIVCLK[0], 1'b0, S2_DIVCLK[5], S2_DIVCLK[2], 1'b0, S2_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[38] = {5'h14, 16'h2FFF, S2_LOCK[1], S2_LOCK[2], 1'b0, S2_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[39] = {5'h15, 16'hBFF4, 1'b0, S2_DIVCLK[12], 10'h000, S2_LOCK[38], 1'b0, S2_LOCK[32], S2_LOCK[39]}; //bits 15 downto 0 + + rom[40] = {5'h16, 16'h0A55, S2_LOCK[15], S2_LOCK[13], S2_LOCK[27], S2_LOCK[16], 1'b0, S2_LOCK[10], //bits 15 downto 10 + 1'b0, S2_DIVCLK[9], S2_DIVCLK[1], 1'b0, S2_DIVCLK[6], 1'b0, S2_DIVCLK[3], //bits 9 downto 3 + 1'b0, S2_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[41] = {5'h17, 16'hFFD0, 10'h000, S2_LOCK[17], 1'b0, S2_LOCK[8], S2_LOCK[9], S2_LOCK[23], S2_LOCK[22]}; //bits 15 downto 0 + + rom[42] = {5'h18, 16'h1039, S2_DIGITAL_FILT[6], S2_DIGITAL_FILT[7], S2_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S2_DIGITAL_FILT[2], S2_DIGITAL_FILT[1], S2_DIGITAL_FILT[3], S2_DIGITAL_FILT[9], //bits 11 downto 8 + S2_DIGITAL_FILT[8], S2_LOCK[26], 3'h0, S2_LOCK[19], S2_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[43] = {5'h19, 16'h0000, S2_LOCK[24], S2_LOCK[25], S2_LOCK[21], S2_LOCK[14], S2_LOCK[11], //bits 15 downto 11 + S2_LOCK[12], S2_LOCK[20], S2_LOCK[6], S2_LOCK[35], S2_LOCK[36], //bits 10 downto 6 + S2_LOCK[37], S2_LOCK[3], S2_LOCK[33], S2_LOCK[31], S2_LOCK[34], S2_LOCK[30]}; //bits 5 downto 0 + + rom[44] = {5'h1A, 16'hFFFC, 14'h0000, S2_LOCK[28], S2_LOCK[29]}; //bits 15 downto 0 + + rom[45] = {5'h1D, 16'h2FFF, S2_LOCK[7], S2_LOCK[4], 1'b0, S2_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 3 Initialization //*********************************************************************** rom[46] = {5'h05, 16'h50FF, S3_CLKOUT0[19], 1'b0, S3_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S3_CLKOUT0[16], S3_CLKOUT0[17], S3_CLKOUT0[15], S3_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S3_CLKOUT0[16], S3_CLKOUT0[17], S3_CLKOUT0[15], S3_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[47] = {5'h06, 16'h010B, S3_CLKOUT1[4], S3_CLKOUT1[5], S3_CLKOUT1[3], S3_CLKOUT1[12], //bits 15 down to 12 - S3_CLKOUT1[1], S3_CLKOUT1[2], S3_CLKOUT1[19], 1'b0, S3_CLKOUT1[17], S3_CLKOUT1[16], //bits 11 down to 6 - S3_CLKOUT1[14], S3_CLKOUT1[15], 1'b0, S3_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[47] = {5'h06, 16'h010B, S3_CLKOUT1[4], S3_CLKOUT1[5], S3_CLKOUT1[3], S3_CLKOUT1[12], //bits 15 down to 12 + S3_CLKOUT1[1], S3_CLKOUT1[2], S3_CLKOUT1[19], 1'b0, S3_CLKOUT1[17], S3_CLKOUT1[16], //bits 11 down to 6 + S3_CLKOUT1[14], S3_CLKOUT1[15], 1'b0, S3_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[48] = {5'h07, 16'hE02C, 3'h0, S3_CLKOUT1[11], S3_CLKOUT1[9], S3_CLKOUT1[10], //bits 15 down to 10 - S3_CLKOUT1[8], S3_CLKOUT1[7], S3_CLKOUT1[6], S3_CLKOUT1[20], 1'b0, S3_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S3_CLKOUT1[21], S3_CLKOUT1[22]}; //bits 3 down to 0 + rom[48] = {5'h07, 16'hE02C, 3'h0, S3_CLKOUT1[11], S3_CLKOUT1[9], S3_CLKOUT1[10], //bits 15 down to 10 + S3_CLKOUT1[8], S3_CLKOUT1[7], S3_CLKOUT1[6], S3_CLKOUT1[20], 1'b0, S3_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S3_CLKOUT1[21], S3_CLKOUT1[22]}; //bits 3 down to 0 - rom[49] = {5'h08, 16'h4001, S3_CLKOUT2[22], 1'b0, S3_CLKOUT2[5], S3_CLKOUT2[21], //bits 15 downto 12 - S3_CLKOUT2[12], S3_CLKOUT2[4], S3_CLKOUT2[3], S3_CLKOUT2[2], S3_CLKOUT2[0], S3_CLKOUT2[19], //bits 11 down to 6 - S3_CLKOUT2[17], S3_CLKOUT2[18], S3_CLKOUT2[15], S3_CLKOUT2[16], S3_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[49] = {5'h08, 16'h4001, S3_CLKOUT2[22], 1'b0, S3_CLKOUT2[5], S3_CLKOUT2[21], //bits 15 downto 12 + S3_CLKOUT2[12], S3_CLKOUT2[4], S3_CLKOUT2[3], S3_CLKOUT2[2], S3_CLKOUT2[0], S3_CLKOUT2[19], //bits 11 down to 6 + S3_CLKOUT2[17], S3_CLKOUT2[18], S3_CLKOUT2[15], S3_CLKOUT2[16], S3_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[50] = {5'h09, 16'h0D03, S3_CLKOUT3[14], S3_CLKOUT3[15], S3_CLKOUT0[21], S3_CLKOUT0[22], 2'h0, S3_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S3_CLKOUT2[9], S3_CLKOUT2[8], S3_CLKOUT2[6], S3_CLKOUT2[7], S3_CLKOUT2[13], S3_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[50] = {5'h09, 16'h0D03, S3_CLKOUT3[14], S3_CLKOUT3[15], S3_CLKOUT0[21], S3_CLKOUT0[22], 2'h0, S3_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S3_CLKOUT2[9], S3_CLKOUT2[8], S3_CLKOUT2[6], S3_CLKOUT2[7], S3_CLKOUT2[13], S3_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[51] = {5'h0A, 16'hB001, 1'b0, S3_CLKOUT3[13], 2'h0, S3_CLKOUT3[21], S3_CLKOUT3[22], S3_CLKOUT3[5], S3_CLKOUT3[4], //bits 15 downto 8 - S3_CLKOUT3[12], S3_CLKOUT3[2], S3_CLKOUT3[0], S3_CLKOUT3[1], S3_CLKOUT3[18], S3_CLKOUT3[19], //bits 7 downto 2 - S3_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[51] = {5'h0A, 16'hB001, 1'b0, S3_CLKOUT3[13], 2'h0, S3_CLKOUT3[21], S3_CLKOUT3[22], S3_CLKOUT3[5], S3_CLKOUT3[4], //bits 15 downto 8 + S3_CLKOUT3[12], S3_CLKOUT3[2], S3_CLKOUT3[0], S3_CLKOUT3[1], S3_CLKOUT3[18], S3_CLKOUT3[19], //bits 7 downto 2 + S3_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[52] = {5'h0B, 16'h0110, S3_CLKOUT0[5], S3_CLKOUT4[19], S3_CLKOUT4[14], S3_CLKOUT4[17], //bits 15 downto 12 - S3_CLKOUT4[15], S3_CLKOUT4[16], S3_CLKOUT0[4], 1'b0, S3_CLKOUT3[11], S3_CLKOUT3[10], //bits 11 downto 6 - S3_CLKOUT3[9], 1'b0, S3_CLKOUT3[7], S3_CLKOUT3[8], S3_CLKOUT3[20], S3_CLKOUT3[6]}; //bits 5 downto 0 + rom[52] = {5'h0B, 16'h0110, S3_CLKOUT0[5], S3_CLKOUT4[19], S3_CLKOUT4[14], S3_CLKOUT4[17], //bits 15 downto 12 + S3_CLKOUT4[15], S3_CLKOUT4[16], S3_CLKOUT0[4], 1'b0, S3_CLKOUT3[11], S3_CLKOUT3[10], //bits 11 downto 6 + S3_CLKOUT3[9], 1'b0, S3_CLKOUT3[7], S3_CLKOUT3[8], S3_CLKOUT3[20], S3_CLKOUT3[6]}; //bits 5 downto 0 - rom[53] = {5'h0C, 16'h0B00, S3_CLKOUT4[7], S3_CLKOUT4[8], S3_CLKOUT4[20], S3_CLKOUT4[6], 1'b0, S3_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S3_CLKOUT4[22], S3_CLKOUT4[21], S3_CLKOUT4[4], S3_CLKOUT4[5], S3_CLKOUT4[3], //bits 9 downto 3 - S3_CLKOUT4[12], S3_CLKOUT4[1], S3_CLKOUT4[2]}; //bits 2 downto 0 + rom[53] = {5'h0C, 16'h0B00, S3_CLKOUT4[7], S3_CLKOUT4[8], S3_CLKOUT4[20], S3_CLKOUT4[6], 1'b0, S3_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S3_CLKOUT4[22], S3_CLKOUT4[21], S3_CLKOUT4[4], S3_CLKOUT4[5], S3_CLKOUT4[3], //bits 9 downto 3 + S3_CLKOUT4[12], S3_CLKOUT4[1], S3_CLKOUT4[2]}; //bits 2 downto 0 - rom[54] = {5'h0D, 16'h0008, S3_CLKOUT5[2], S3_CLKOUT5[3], S3_CLKOUT5[0], S3_CLKOUT5[1], S3_CLKOUT5[18], //bits 15 downto 11 - S3_CLKOUT5[19], S3_CLKOUT5[17], S3_CLKOUT5[16], S3_CLKOUT5[15], S3_CLKOUT0[3], //bits 10 downto 6 - S3_CLKOUT0[0], S3_CLKOUT0[2], 1'b0, S3_CLKOUT4[11], S3_CLKOUT4[9], S3_CLKOUT4[10]}; //bits 5 downto 0 + rom[54] = {5'h0D, 16'h0008, S3_CLKOUT5[2], S3_CLKOUT5[3], S3_CLKOUT5[0], S3_CLKOUT5[1], S3_CLKOUT5[18], //bits 15 downto 11 + S3_CLKOUT5[19], S3_CLKOUT5[17], S3_CLKOUT5[16], S3_CLKOUT5[15], S3_CLKOUT0[3], //bits 10 downto 6 + S3_CLKOUT0[0], S3_CLKOUT0[2], 1'b0, S3_CLKOUT4[11], S3_CLKOUT4[9], S3_CLKOUT4[10]}; //bits 5 downto 0 - rom[55] = {5'h0E, 16'h00D0, S3_CLKOUT5[10], S3_CLKOUT5[11], S3_CLKOUT5[8], S3_CLKOUT5[9], S3_CLKOUT5[6], //bits 15 downto 11 - S3_CLKOUT5[7], S3_CLKOUT5[20], S3_CLKOUT5[13], 2'h0, S3_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S3_CLKOUT5[5], S3_CLKOUT5[21], S3_CLKOUT5[12], S3_CLKOUT5[4]}; //bits 3 downto 0 + rom[55] = {5'h0E, 16'h00D0, S3_CLKOUT5[10], S3_CLKOUT5[11], S3_CLKOUT5[8], S3_CLKOUT5[9], S3_CLKOUT5[6], //bits 15 downto 11 + S3_CLKOUT5[7], S3_CLKOUT5[20], S3_CLKOUT5[13], 2'h0, S3_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S3_CLKOUT5[5], S3_CLKOUT5[21], S3_CLKOUT5[12], S3_CLKOUT5[4]}; //bits 3 downto 0 - rom[56] = {5'h0F, 16'h0003, S3_CLKFBOUT[4], S3_CLKFBOUT[5], S3_CLKFBOUT[3], S3_CLKFBOUT[12], S3_CLKFBOUT[1], //bits 15 downto 11 - S3_CLKFBOUT[2], S3_CLKFBOUT[0], S3_CLKFBOUT[19], S3_CLKFBOUT[18], S3_CLKFBOUT[17], //bits 10 downto 6 - S3_CLKFBOUT[15], S3_CLKFBOUT[16], S3_CLKOUT0[12], S3_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[56] = {5'h0F, 16'h0003, S3_CLKFBOUT[4], S3_CLKFBOUT[5], S3_CLKFBOUT[3], S3_CLKFBOUT[12], S3_CLKFBOUT[1], //bits 15 downto 11 + S3_CLKFBOUT[2], S3_CLKFBOUT[0], S3_CLKFBOUT[19], S3_CLKFBOUT[18], S3_CLKFBOUT[17], //bits 10 downto 6 + S3_CLKFBOUT[15], S3_CLKFBOUT[16], S3_CLKOUT0[12], S3_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[57] = {5'h10, 16'h800C, 1'b0, S3_CLKOUT0[9], S3_CLKOUT0[11], S3_CLKOUT0[10], S3_CLKFBOUT[10], S3_CLKFBOUT[11], //bits 15 downto 10 - S3_CLKFBOUT[9], S3_CLKFBOUT[8], S3_CLKFBOUT[7], S3_CLKFBOUT[6], S3_CLKFBOUT[13], //bits 9 downto 5 - S3_CLKFBOUT[20], 2'h0, S3_CLKFBOUT[21], S3_CLKFBOUT[22]}; //bits 4 downto 0 + rom[57] = {5'h10, 16'h800C, 1'b0, S3_CLKOUT0[9], S3_CLKOUT0[11], S3_CLKOUT0[10], S3_CLKFBOUT[10], S3_CLKFBOUT[11], //bits 15 downto 10 + S3_CLKFBOUT[9], S3_CLKFBOUT[8], S3_CLKFBOUT[7], S3_CLKFBOUT[6], S3_CLKFBOUT[13], //bits 9 downto 5 + S3_CLKFBOUT[20], 2'h0, S3_CLKFBOUT[21], S3_CLKFBOUT[22]}; //bits 4 downto 0 - rom[58] = {5'h11, 16'hFC00, 6'h00, S3_CLKOUT3[3], S3_CLKOUT3[16], S3_CLKOUT2[11], S3_CLKOUT2[1], S3_CLKOUT1[18], //bits 15 downto 6 - S3_CLKOUT1[0], S3_CLKOUT0[6], S3_CLKOUT0[20], S3_CLKOUT0[8], S3_CLKOUT0[7]}; //bits 5 downto 0 + rom[58] = {5'h11, 16'hFC00, 6'h00, S3_CLKOUT3[3], S3_CLKOUT3[16], S3_CLKOUT2[11], S3_CLKOUT2[1], S3_CLKOUT1[18], //bits 15 downto 6 + S3_CLKOUT1[0], S3_CLKOUT0[6], S3_CLKOUT0[20], S3_CLKOUT0[8], S3_CLKOUT0[7]}; //bits 5 downto 0 - rom[59] = {5'h12, 16'hF0FF, 4'h0, S3_CLKOUT5[14], S3_CLKFBOUT[14], S3_CLKOUT4[0], S3_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[59] = {5'h12, 16'hF0FF, 4'h0, S3_CLKOUT5[14], S3_CLKFBOUT[14], S3_CLKOUT4[0], S3_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[60] = {5'h13, 16'h5120, S3_DIVCLK[11], 1'b0, S3_DIVCLK[10], 1'b0, S3_DIVCLK[7], S3_DIVCLK[8], //bits 15 downto 10 - S3_DIVCLK[0], 1'b0, S3_DIVCLK[5], S3_DIVCLK[2], 1'b0, S3_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[60] = {5'h13, 16'h5120, S3_DIVCLK[11], 1'b0, S3_DIVCLK[10], 1'b0, S3_DIVCLK[7], S3_DIVCLK[8], //bits 15 downto 10 + S3_DIVCLK[0], 1'b0, S3_DIVCLK[5], S3_DIVCLK[2], 1'b0, S3_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[61] = {5'h14, 16'h2FFF, S3_LOCK[1], S3_LOCK[2], 1'b0, S3_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[61] = {5'h14, 16'h2FFF, S3_LOCK[1], S3_LOCK[2], 1'b0, S3_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[62] = {5'h15, 16'hBFF4, 1'b0, S3_DIVCLK[12], 10'h000, S3_LOCK[38], 1'b0, S3_LOCK[32], S3_LOCK[39]}; //bits 15 downto 0 + rom[62] = {5'h15, 16'hBFF4, 1'b0, S3_DIVCLK[12], 10'h000, S3_LOCK[38], 1'b0, S3_LOCK[32], S3_LOCK[39]}; //bits 15 downto 0 - rom[63] = {5'h16, 16'h0A55, S3_LOCK[15], S3_LOCK[13], S3_LOCK[27], S3_LOCK[16], 1'b0, S3_LOCK[10], //bits 15 downto 10 - 1'b0, S3_DIVCLK[9], S3_DIVCLK[1], 1'b0, S3_DIVCLK[6], 1'b0, S3_DIVCLK[3], //bits 9 downto 3 - 1'b0, S3_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[63] = {5'h16, 16'h0A55, S3_LOCK[15], S3_LOCK[13], S3_LOCK[27], S3_LOCK[16], 1'b0, S3_LOCK[10], //bits 15 downto 10 + 1'b0, S3_DIVCLK[9], S3_DIVCLK[1], 1'b0, S3_DIVCLK[6], 1'b0, S3_DIVCLK[3], //bits 9 downto 3 + 1'b0, S3_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[64] = {5'h17, 16'hFFD0, 10'h000, S3_LOCK[17], 1'b0, S3_LOCK[8], S3_LOCK[9], S3_LOCK[23], S3_LOCK[22]}; //bits 15 downto 0 + rom[64] = {5'h17, 16'hFFD0, 10'h000, S3_LOCK[17], 1'b0, S3_LOCK[8], S3_LOCK[9], S3_LOCK[23], S3_LOCK[22]}; //bits 15 downto 0 - rom[65] = {5'h18, 16'h1039, S3_DIGITAL_FILT[6], S3_DIGITAL_FILT[7], S3_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S3_DIGITAL_FILT[2], S3_DIGITAL_FILT[1], S3_DIGITAL_FILT[3], S3_DIGITAL_FILT[9], //bits 11 downto 8 - S3_DIGITAL_FILT[8], S3_LOCK[26], 3'h0, S3_LOCK[19], S3_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[65] = {5'h18, 16'h1039, S3_DIGITAL_FILT[6], S3_DIGITAL_FILT[7], S3_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S3_DIGITAL_FILT[2], S3_DIGITAL_FILT[1], S3_DIGITAL_FILT[3], S3_DIGITAL_FILT[9], //bits 11 downto 8 + S3_DIGITAL_FILT[8], S3_LOCK[26], 3'h0, S3_LOCK[19], S3_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[66] = {5'h19, 16'h0000, S3_LOCK[24], S3_LOCK[25], S3_LOCK[21], S3_LOCK[14], S3_LOCK[11], //bits 15 downto 11 - S3_LOCK[12], S3_LOCK[20], S3_LOCK[6], S3_LOCK[35], S3_LOCK[36], //bits 10 downto 6 - S3_LOCK[37], S3_LOCK[3], S3_LOCK[33], S3_LOCK[31], S3_LOCK[34], S3_LOCK[30]}; //bits 5 downto 0 + rom[66] = {5'h19, 16'h0000, S3_LOCK[24], S3_LOCK[25], S3_LOCK[21], S3_LOCK[14], S3_LOCK[11], //bits 15 downto 11 + S3_LOCK[12], S3_LOCK[20], S3_LOCK[6], S3_LOCK[35], S3_LOCK[36], //bits 10 downto 6 + S3_LOCK[37], S3_LOCK[3], S3_LOCK[33], S3_LOCK[31], S3_LOCK[34], S3_LOCK[30]}; //bits 5 downto 0 - rom[67] = {5'h1A, 16'hFFFC, 14'h0000, S3_LOCK[28], S3_LOCK[29]}; //bits 15 downto 0 + rom[67] = {5'h1A, 16'hFFFC, 14'h0000, S3_LOCK[28], S3_LOCK[29]}; //bits 15 downto 0 - rom[68] = {5'h1D, 16'h2FFF, S3_LOCK[7], S3_LOCK[4], 1'b0, S3_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[68] = {5'h1D, 16'h2FFF, S3_LOCK[7], S3_LOCK[4], 1'b0, S3_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 4 Initialization //*********************************************************************** rom[69] = {5'h05, 16'h50FF, S4_CLKOUT0[19], 1'b0, S4_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S4_CLKOUT0[16], S4_CLKOUT0[17], S4_CLKOUT0[15], S4_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S4_CLKOUT0[16], S4_CLKOUT0[17], S4_CLKOUT0[15], S4_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[70] = {5'h06, 16'h010B, S4_CLKOUT1[4], S4_CLKOUT1[5], S4_CLKOUT1[3], S4_CLKOUT1[12], //bits 15 down to 12 - S4_CLKOUT1[1], S4_CLKOUT1[2], S4_CLKOUT1[19], 1'b0, S4_CLKOUT1[17], S4_CLKOUT1[16], //bits 11 down to 6 - S4_CLKOUT1[14], S4_CLKOUT1[15], 1'b0, S4_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[70] = {5'h06, 16'h010B, S4_CLKOUT1[4], S4_CLKOUT1[5], S4_CLKOUT1[3], S4_CLKOUT1[12], //bits 15 down to 12 + S4_CLKOUT1[1], S4_CLKOUT1[2], S4_CLKOUT1[19], 1'b0, S4_CLKOUT1[17], S4_CLKOUT1[16], //bits 11 down to 6 + S4_CLKOUT1[14], S4_CLKOUT1[15], 1'b0, S4_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[71] = {5'h07, 16'hE02C, 3'h0, S4_CLKOUT1[11], S4_CLKOUT1[9], S4_CLKOUT1[10], //bits 15 down to 10 - S4_CLKOUT1[8], S4_CLKOUT1[7], S4_CLKOUT1[6], S4_CLKOUT1[20], 1'b0, S4_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S4_CLKOUT1[21], S4_CLKOUT1[22]}; //bits 3 down to 0 + rom[71] = {5'h07, 16'hE02C, 3'h0, S4_CLKOUT1[11], S4_CLKOUT1[9], S4_CLKOUT1[10], //bits 15 down to 10 + S4_CLKOUT1[8], S4_CLKOUT1[7], S4_CLKOUT1[6], S4_CLKOUT1[20], 1'b0, S4_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S4_CLKOUT1[21], S4_CLKOUT1[22]}; //bits 3 down to 0 - rom[72] = {5'h08, 16'h4001, S4_CLKOUT2[22], 1'b0, S4_CLKOUT2[5], S4_CLKOUT2[21], //bits 15 downto 12 - S4_CLKOUT2[12], S4_CLKOUT2[4], S4_CLKOUT2[3], S4_CLKOUT2[2], S4_CLKOUT2[0], S4_CLKOUT2[19], //bits 11 down to 6 - S4_CLKOUT2[17], S4_CLKOUT2[18], S4_CLKOUT2[15], S4_CLKOUT2[16], S4_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[72] = {5'h08, 16'h4001, S4_CLKOUT2[22], 1'b0, S4_CLKOUT2[5], S4_CLKOUT2[21], //bits 15 downto 12 + S4_CLKOUT2[12], S4_CLKOUT2[4], S4_CLKOUT2[3], S4_CLKOUT2[2], S4_CLKOUT2[0], S4_CLKOUT2[19], //bits 11 down to 6 + S4_CLKOUT2[17], S4_CLKOUT2[18], S4_CLKOUT2[15], S4_CLKOUT2[16], S4_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[73] = {5'h09, 16'h0D03, S4_CLKOUT3[14], S4_CLKOUT3[15], S4_CLKOUT0[21], S4_CLKOUT0[22], 2'h0, S4_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S4_CLKOUT2[9], S4_CLKOUT2[8], S4_CLKOUT2[6], S4_CLKOUT2[7], S4_CLKOUT2[13], S4_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[73] = {5'h09, 16'h0D03, S4_CLKOUT3[14], S4_CLKOUT3[15], S4_CLKOUT0[21], S4_CLKOUT0[22], 2'h0, S4_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S4_CLKOUT2[9], S4_CLKOUT2[8], S4_CLKOUT2[6], S4_CLKOUT2[7], S4_CLKOUT2[13], S4_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[74] = {5'h0A, 16'hB001, 1'b0, S4_CLKOUT3[13], 2'h0, S4_CLKOUT3[21], S4_CLKOUT3[22], S4_CLKOUT3[5], S4_CLKOUT3[4], //bits 15 downto 8 - S4_CLKOUT3[12], S4_CLKOUT3[2], S4_CLKOUT3[0], S4_CLKOUT3[1], S4_CLKOUT3[18], S4_CLKOUT3[19], //bits 7 downto 2 - S4_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[74] = {5'h0A, 16'hB001, 1'b0, S4_CLKOUT3[13], 2'h0, S4_CLKOUT3[21], S4_CLKOUT3[22], S4_CLKOUT3[5], S4_CLKOUT3[4], //bits 15 downto 8 + S4_CLKOUT3[12], S4_CLKOUT3[2], S4_CLKOUT3[0], S4_CLKOUT3[1], S4_CLKOUT3[18], S4_CLKOUT3[19], //bits 7 downto 2 + S4_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[75] = {5'h0B, 16'h0110, S4_CLKOUT0[5], S4_CLKOUT4[19], S4_CLKOUT4[14], S4_CLKOUT4[17], //bits 15 downto 12 - S4_CLKOUT4[15], S4_CLKOUT4[16], S4_CLKOUT0[4], 1'b0, S4_CLKOUT3[11], S4_CLKOUT3[10], //bits 11 downto 6 - S4_CLKOUT3[9], 1'b0, S4_CLKOUT3[7], S4_CLKOUT3[8], S4_CLKOUT3[20], S4_CLKOUT3[6]}; //bits 5 downto 0 + rom[75] = {5'h0B, 16'h0110, S4_CLKOUT0[5], S4_CLKOUT4[19], S4_CLKOUT4[14], S4_CLKOUT4[17], //bits 15 downto 12 + S4_CLKOUT4[15], S4_CLKOUT4[16], S4_CLKOUT0[4], 1'b0, S4_CLKOUT3[11], S4_CLKOUT3[10], //bits 11 downto 6 + S4_CLKOUT3[9], 1'b0, S4_CLKOUT3[7], S4_CLKOUT3[8], S4_CLKOUT3[20], S4_CLKOUT3[6]}; //bits 5 downto 0 - rom[76] = {5'h0C, 16'h0B00, S4_CLKOUT4[7], S4_CLKOUT4[8], S4_CLKOUT4[20], S4_CLKOUT4[6], 1'b0, S4_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S4_CLKOUT4[22], S4_CLKOUT4[21], S4_CLKOUT4[4], S4_CLKOUT4[5], S4_CLKOUT4[3], //bits 9 downto 3 - S4_CLKOUT4[12], S4_CLKOUT4[1], S4_CLKOUT4[2]}; //bits 2 downto 0 + rom[76] = {5'h0C, 16'h0B00, S4_CLKOUT4[7], S4_CLKOUT4[8], S4_CLKOUT4[20], S4_CLKOUT4[6], 1'b0, S4_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S4_CLKOUT4[22], S4_CLKOUT4[21], S4_CLKOUT4[4], S4_CLKOUT4[5], S4_CLKOUT4[3], //bits 9 downto 3 + S4_CLKOUT4[12], S4_CLKOUT4[1], S4_CLKOUT4[2]}; //bits 2 downto 0 - rom[77] = {5'h0D, 16'h0008, S4_CLKOUT5[2], S4_CLKOUT5[3], S4_CLKOUT5[0], S4_CLKOUT5[1], S4_CLKOUT5[18], //bits 15 downto 11 - S4_CLKOUT5[19], S4_CLKOUT5[17], S4_CLKOUT5[16], S4_CLKOUT5[15], S4_CLKOUT0[3], //bits 10 downto 6 - S4_CLKOUT0[0], S4_CLKOUT0[2], 1'b0, S4_CLKOUT4[11], S4_CLKOUT4[9], S4_CLKOUT4[10]}; //bits 5 downto 0 + rom[77] = {5'h0D, 16'h0008, S4_CLKOUT5[2], S4_CLKOUT5[3], S4_CLKOUT5[0], S4_CLKOUT5[1], S4_CLKOUT5[18], //bits 15 downto 11 + S4_CLKOUT5[19], S4_CLKOUT5[17], S4_CLKOUT5[16], S4_CLKOUT5[15], S4_CLKOUT0[3], //bits 10 downto 6 + S4_CLKOUT0[0], S4_CLKOUT0[2], 1'b0, S4_CLKOUT4[11], S4_CLKOUT4[9], S4_CLKOUT4[10]}; //bits 5 downto 0 - rom[78] = {5'h0E, 16'h00D0, S4_CLKOUT5[10], S4_CLKOUT5[11], S4_CLKOUT5[8], S4_CLKOUT5[9], S4_CLKOUT5[6], //bits 15 downto 11 - S4_CLKOUT5[7], S4_CLKOUT5[20], S4_CLKOUT5[13], 2'h0, S4_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S4_CLKOUT5[5], S4_CLKOUT5[21], S4_CLKOUT5[12], S4_CLKOUT5[4]}; //bits 3 downto 0 + rom[78] = {5'h0E, 16'h00D0, S4_CLKOUT5[10], S4_CLKOUT5[11], S4_CLKOUT5[8], S4_CLKOUT5[9], S4_CLKOUT5[6], //bits 15 downto 11 + S4_CLKOUT5[7], S4_CLKOUT5[20], S4_CLKOUT5[13], 2'h0, S4_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S4_CLKOUT5[5], S4_CLKOUT5[21], S4_CLKOUT5[12], S4_CLKOUT5[4]}; //bits 3 downto 0 - rom[79] = {5'h0F, 16'h0003, S4_CLKFBOUT[4], S4_CLKFBOUT[5], S4_CLKFBOUT[3], S4_CLKFBOUT[12], S4_CLKFBOUT[1], //bits 15 downto 11 - S4_CLKFBOUT[2], S4_CLKFBOUT[0], S4_CLKFBOUT[19], S4_CLKFBOUT[18], S4_CLKFBOUT[17], //bits 10 downto 6 - S4_CLKFBOUT[15], S4_CLKFBOUT[16], S4_CLKOUT0[12], S4_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[79] = {5'h0F, 16'h0003, S4_CLKFBOUT[4], S4_CLKFBOUT[5], S4_CLKFBOUT[3], S4_CLKFBOUT[12], S4_CLKFBOUT[1], //bits 15 downto 11 + S4_CLKFBOUT[2], S4_CLKFBOUT[0], S4_CLKFBOUT[19], S4_CLKFBOUT[18], S4_CLKFBOUT[17], //bits 10 downto 6 + S4_CLKFBOUT[15], S4_CLKFBOUT[16], S4_CLKOUT0[12], S4_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[80] = {5'h10, 16'h800C, 1'b0, S4_CLKOUT0[9], S4_CLKOUT0[11], S4_CLKOUT0[10], S4_CLKFBOUT[10], S4_CLKFBOUT[11], //bits 15 downto 10 - S4_CLKFBOUT[9], S4_CLKFBOUT[8], S4_CLKFBOUT[7], S4_CLKFBOUT[6], S4_CLKFBOUT[13], //bits 9 downto 5 - S4_CLKFBOUT[20], 2'h0, S4_CLKFBOUT[21], S4_CLKFBOUT[22]}; //bits 4 downto 0 + rom[80] = {5'h10, 16'h800C, 1'b0, S4_CLKOUT0[9], S4_CLKOUT0[11], S4_CLKOUT0[10], S4_CLKFBOUT[10], S4_CLKFBOUT[11], //bits 15 downto 10 + S4_CLKFBOUT[9], S4_CLKFBOUT[8], S4_CLKFBOUT[7], S4_CLKFBOUT[6], S4_CLKFBOUT[13], //bits 9 downto 5 + S4_CLKFBOUT[20], 2'h0, S4_CLKFBOUT[21], S4_CLKFBOUT[22]}; //bits 4 downto 0 - rom[81] = {5'h11, 16'hFC00, 6'h00, S4_CLKOUT3[3], S4_CLKOUT3[16], S4_CLKOUT2[11], S4_CLKOUT2[1], S4_CLKOUT1[18], //bits 15 downto 6 - S4_CLKOUT1[0], S4_CLKOUT0[6], S4_CLKOUT0[20], S4_CLKOUT0[8], S4_CLKOUT0[7]}; //bits 5 downto 0 + rom[81] = {5'h11, 16'hFC00, 6'h00, S4_CLKOUT3[3], S4_CLKOUT3[16], S4_CLKOUT2[11], S4_CLKOUT2[1], S4_CLKOUT1[18], //bits 15 downto 6 + S4_CLKOUT1[0], S4_CLKOUT0[6], S4_CLKOUT0[20], S4_CLKOUT0[8], S4_CLKOUT0[7]}; //bits 5 downto 0 - rom[82] = {5'h12, 16'hF0FF, 4'h0, S4_CLKOUT5[14], S4_CLKFBOUT[14], S4_CLKOUT4[0], S4_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[82] = {5'h12, 16'hF0FF, 4'h0, S4_CLKOUT5[14], S4_CLKFBOUT[14], S4_CLKOUT4[0], S4_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[83] = {5'h13, 16'h5120, S4_DIVCLK[11], 1'b0, S4_DIVCLK[10], 1'b0, S4_DIVCLK[7], S4_DIVCLK[8], //bits 15 downto 10 - S4_DIVCLK[0], 1'b0, S4_DIVCLK[5], S4_DIVCLK[2], 1'b0, S4_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[83] = {5'h13, 16'h5120, S4_DIVCLK[11], 1'b0, S4_DIVCLK[10], 1'b0, S4_DIVCLK[7], S4_DIVCLK[8], //bits 15 downto 10 + S4_DIVCLK[0], 1'b0, S4_DIVCLK[5], S4_DIVCLK[2], 1'b0, S4_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[84] = {5'h14, 16'h2FFF, S4_LOCK[1], S4_LOCK[2], 1'b0, S4_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[84] = {5'h14, 16'h2FFF, S4_LOCK[1], S4_LOCK[2], 1'b0, S4_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[85] = {5'h15, 16'hBFF4, 1'b0, S4_DIVCLK[12], 10'h000, S4_LOCK[38], 1'b0, S4_LOCK[32], S4_LOCK[39]}; //bits 15 downto 0 + rom[85] = {5'h15, 16'hBFF4, 1'b0, S4_DIVCLK[12], 10'h000, S4_LOCK[38], 1'b0, S4_LOCK[32], S4_LOCK[39]}; //bits 15 downto 0 - rom[86] = {5'h16, 16'h0A55, S4_LOCK[15], S4_LOCK[13], S4_LOCK[27], S4_LOCK[16], 1'b0, S4_LOCK[10], //bits 15 downto 10 - 1'b0, S4_DIVCLK[9], S4_DIVCLK[1], 1'b0, S4_DIVCLK[6], 1'b0, S4_DIVCLK[3], //bits 9 downto 3 - 1'b0, S4_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[86] = {5'h16, 16'h0A55, S4_LOCK[15], S4_LOCK[13], S4_LOCK[27], S4_LOCK[16], 1'b0, S4_LOCK[10], //bits 15 downto 10 + 1'b0, S4_DIVCLK[9], S4_DIVCLK[1], 1'b0, S4_DIVCLK[6], 1'b0, S4_DIVCLK[3], //bits 9 downto 3 + 1'b0, S4_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[87] = {5'h17, 16'hFFD0, 10'h000, S4_LOCK[17], 1'b0, S4_LOCK[8], S4_LOCK[9], S4_LOCK[23], S4_LOCK[22]}; //bits 15 downto 0 + rom[87] = {5'h17, 16'hFFD0, 10'h000, S4_LOCK[17], 1'b0, S4_LOCK[8], S4_LOCK[9], S4_LOCK[23], S4_LOCK[22]}; //bits 15 downto 0 - rom[88] = {5'h18, 16'h1039, S4_DIGITAL_FILT[6], S4_DIGITAL_FILT[7], S4_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S4_DIGITAL_FILT[2], S4_DIGITAL_FILT[1], S4_DIGITAL_FILT[3], S4_DIGITAL_FILT[9], //bits 11 downto 8 - S4_DIGITAL_FILT[8], S4_LOCK[26], 3'h0, S4_LOCK[19], S4_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[88] = {5'h18, 16'h1039, S4_DIGITAL_FILT[6], S4_DIGITAL_FILT[7], S4_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S4_DIGITAL_FILT[2], S4_DIGITAL_FILT[1], S4_DIGITAL_FILT[3], S4_DIGITAL_FILT[9], //bits 11 downto 8 + S4_DIGITAL_FILT[8], S4_LOCK[26], 3'h0, S4_LOCK[19], S4_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[89] = {5'h19, 16'h0000, S4_LOCK[24], S4_LOCK[25], S4_LOCK[21], S4_LOCK[14], S4_LOCK[11], //bits 15 downto 11 - S4_LOCK[12], S4_LOCK[20], S4_LOCK[6], S4_LOCK[35], S4_LOCK[36], //bits 10 downto 6 - S4_LOCK[37], S4_LOCK[3], S4_LOCK[33], S4_LOCK[31], S4_LOCK[34], S4_LOCK[30]}; //bits 5 downto 0 + rom[89] = {5'h19, 16'h0000, S4_LOCK[24], S4_LOCK[25], S4_LOCK[21], S4_LOCK[14], S4_LOCK[11], //bits 15 downto 11 + S4_LOCK[12], S4_LOCK[20], S4_LOCK[6], S4_LOCK[35], S4_LOCK[36], //bits 10 downto 6 + S4_LOCK[37], S4_LOCK[3], S4_LOCK[33], S4_LOCK[31], S4_LOCK[34], S4_LOCK[30]}; //bits 5 downto 0 - rom[90] = {5'h1A, 16'hFFFC, 14'h0000, S4_LOCK[28], S4_LOCK[29]}; //bits 15 downto 0 + rom[90] = {5'h1A, 16'hFFFC, 14'h0000, S4_LOCK[28], S4_LOCK[29]}; //bits 15 downto 0 - rom[91] = {5'h1D, 16'h2FFF, S4_LOCK[7], S4_LOCK[4], 1'b0, S4_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[91] = {5'h1D, 16'h2FFF, S4_LOCK[7], S4_LOCK[4], 1'b0, S4_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 5 Initialization //*********************************************************************** rom[92] = {5'h05, 16'h50FF, S5_CLKOUT0[19], 1'b0, S5_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S5_CLKOUT0[16], S5_CLKOUT0[17], S5_CLKOUT0[15], S5_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S5_CLKOUT0[16], S5_CLKOUT0[17], S5_CLKOUT0[15], S5_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[93] = {5'h06, 16'h010B, S5_CLKOUT1[4], S5_CLKOUT1[5], S5_CLKOUT1[3], S5_CLKOUT1[12], //bits 15 down to 12 - S5_CLKOUT1[1], S5_CLKOUT1[2], S5_CLKOUT1[19], 1'b0, S5_CLKOUT1[17], S5_CLKOUT1[16], //bits 11 down to 6 - S5_CLKOUT1[14], S5_CLKOUT1[15], 1'b0, S5_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[93] = {5'h06, 16'h010B, S5_CLKOUT1[4], S5_CLKOUT1[5], S5_CLKOUT1[3], S5_CLKOUT1[12], //bits 15 down to 12 + S5_CLKOUT1[1], S5_CLKOUT1[2], S5_CLKOUT1[19], 1'b0, S5_CLKOUT1[17], S5_CLKOUT1[16], //bits 11 down to 6 + S5_CLKOUT1[14], S5_CLKOUT1[15], 1'b0, S5_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[94] = {5'h07, 16'hE02C, 3'h0, S5_CLKOUT1[11], S5_CLKOUT1[9], S5_CLKOUT1[10], //bits 15 down to 10 - S5_CLKOUT1[8], S5_CLKOUT1[7], S5_CLKOUT1[6], S5_CLKOUT1[20], 1'b0, S5_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S5_CLKOUT1[21], S5_CLKOUT1[22]}; //bits 3 down to 0 + rom[94] = {5'h07, 16'hE02C, 3'h0, S5_CLKOUT1[11], S5_CLKOUT1[9], S5_CLKOUT1[10], //bits 15 down to 10 + S5_CLKOUT1[8], S5_CLKOUT1[7], S5_CLKOUT1[6], S5_CLKOUT1[20], 1'b0, S5_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S5_CLKOUT1[21], S5_CLKOUT1[22]}; //bits 3 down to 0 - rom[95] = {5'h08, 16'h4001, S5_CLKOUT2[22], 1'b0, S5_CLKOUT2[5], S5_CLKOUT2[21], //bits 15 downto 12 - S5_CLKOUT2[12], S5_CLKOUT2[4], S5_CLKOUT2[3], S5_CLKOUT2[2], S5_CLKOUT2[0], S5_CLKOUT2[19], //bits 11 down to 6 - S5_CLKOUT2[17], S5_CLKOUT2[18], S5_CLKOUT2[15], S5_CLKOUT2[16], S5_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[95] = {5'h08, 16'h4001, S5_CLKOUT2[22], 1'b0, S5_CLKOUT2[5], S5_CLKOUT2[21], //bits 15 downto 12 + S5_CLKOUT2[12], S5_CLKOUT2[4], S5_CLKOUT2[3], S5_CLKOUT2[2], S5_CLKOUT2[0], S5_CLKOUT2[19], //bits 11 down to 6 + S5_CLKOUT2[17], S5_CLKOUT2[18], S5_CLKOUT2[15], S5_CLKOUT2[16], S5_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[96] = {5'h09, 16'h0D03, S5_CLKOUT3[14], S5_CLKOUT3[15], S5_CLKOUT0[21], S5_CLKOUT0[22], 2'h0, S5_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S5_CLKOUT2[9], S5_CLKOUT2[8], S5_CLKOUT2[6], S5_CLKOUT2[7], S5_CLKOUT2[13], S5_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[96] = {5'h09, 16'h0D03, S5_CLKOUT3[14], S5_CLKOUT3[15], S5_CLKOUT0[21], S5_CLKOUT0[22], 2'h0, S5_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S5_CLKOUT2[9], S5_CLKOUT2[8], S5_CLKOUT2[6], S5_CLKOUT2[7], S5_CLKOUT2[13], S5_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[97] = {5'h0A, 16'hB001, 1'b0, S5_CLKOUT3[13], 2'h0, S5_CLKOUT3[21], S5_CLKOUT3[22], S5_CLKOUT3[5], S5_CLKOUT3[4], //bits 15 downto 8 - S5_CLKOUT3[12], S5_CLKOUT3[2], S5_CLKOUT3[0], S5_CLKOUT3[1], S5_CLKOUT3[18], S5_CLKOUT3[19], //bits 7 downto 2 - S5_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[97] = {5'h0A, 16'hB001, 1'b0, S5_CLKOUT3[13], 2'h0, S5_CLKOUT3[21], S5_CLKOUT3[22], S5_CLKOUT3[5], S5_CLKOUT3[4], //bits 15 downto 8 + S5_CLKOUT3[12], S5_CLKOUT3[2], S5_CLKOUT3[0], S5_CLKOUT3[1], S5_CLKOUT3[18], S5_CLKOUT3[19], //bits 7 downto 2 + S5_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[98] = {5'h0B, 16'h0110, S5_CLKOUT0[5], S5_CLKOUT4[19], S5_CLKOUT4[14], S5_CLKOUT4[17], //bits 15 downto 12 - S5_CLKOUT4[15], S5_CLKOUT4[16], S5_CLKOUT0[4], 1'b0, S5_CLKOUT3[11], S5_CLKOUT3[10], //bits 11 downto 6 - S5_CLKOUT3[9], 1'b0, S5_CLKOUT3[7], S5_CLKOUT3[8], S5_CLKOUT3[20], S5_CLKOUT3[6]}; //bits 5 downto 0 + rom[98] = {5'h0B, 16'h0110, S5_CLKOUT0[5], S5_CLKOUT4[19], S5_CLKOUT4[14], S5_CLKOUT4[17], //bits 15 downto 12 + S5_CLKOUT4[15], S5_CLKOUT4[16], S5_CLKOUT0[4], 1'b0, S5_CLKOUT3[11], S5_CLKOUT3[10], //bits 11 downto 6 + S5_CLKOUT3[9], 1'b0, S5_CLKOUT3[7], S5_CLKOUT3[8], S5_CLKOUT3[20], S5_CLKOUT3[6]}; //bits 5 downto 0 - rom[99] = {5'h0C, 16'h0B00, S5_CLKOUT4[7], S5_CLKOUT4[8], S5_CLKOUT4[20], S5_CLKOUT4[6], 1'b0, S5_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S5_CLKOUT4[22], S5_CLKOUT4[21], S5_CLKOUT4[4], S5_CLKOUT4[5], S5_CLKOUT4[3], //bits 9 downto 3 - S5_CLKOUT4[12], S5_CLKOUT4[1], S5_CLKOUT4[2]}; //bits 2 downto 0 + rom[99] = {5'h0C, 16'h0B00, S5_CLKOUT4[7], S5_CLKOUT4[8], S5_CLKOUT4[20], S5_CLKOUT4[6], 1'b0, S5_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S5_CLKOUT4[22], S5_CLKOUT4[21], S5_CLKOUT4[4], S5_CLKOUT4[5], S5_CLKOUT4[3], //bits 9 downto 3 + S5_CLKOUT4[12], S5_CLKOUT4[1], S5_CLKOUT4[2]}; //bits 2 downto 0 - rom[100] = {5'h0D, 16'h0008, S5_CLKOUT5[2], S5_CLKOUT5[3], S5_CLKOUT5[0], S5_CLKOUT5[1], S5_CLKOUT5[18], //bits 15 downto 11 - S5_CLKOUT5[19], S5_CLKOUT5[17], S5_CLKOUT5[16], S5_CLKOUT5[15], S5_CLKOUT0[3], //bits 10 downto 6 - S5_CLKOUT0[0], S5_CLKOUT0[2], 1'b0, S5_CLKOUT4[11], S5_CLKOUT4[9], S5_CLKOUT4[10]}; //bits 5 downto 0 + rom[100] = {5'h0D, 16'h0008, S5_CLKOUT5[2], S5_CLKOUT5[3], S5_CLKOUT5[0], S5_CLKOUT5[1], S5_CLKOUT5[18], //bits 15 downto 11 + S5_CLKOUT5[19], S5_CLKOUT5[17], S5_CLKOUT5[16], S5_CLKOUT5[15], S5_CLKOUT0[3], //bits 10 downto 6 + S5_CLKOUT0[0], S5_CLKOUT0[2], 1'b0, S5_CLKOUT4[11], S5_CLKOUT4[9], S5_CLKOUT4[10]}; //bits 5 downto 0 - rom[101] = {5'h0E, 16'h00D0, S5_CLKOUT5[10], S5_CLKOUT5[11], S5_CLKOUT5[8], S5_CLKOUT5[9], S5_CLKOUT5[6], //bits 15 downto 11 - S5_CLKOUT5[7], S5_CLKOUT5[20], S5_CLKOUT5[13], 2'h0, S5_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S5_CLKOUT5[5], S5_CLKOUT5[21], S5_CLKOUT5[12], S5_CLKOUT5[4]}; //bits 3 downto 0 + rom[101] = {5'h0E, 16'h00D0, S5_CLKOUT5[10], S5_CLKOUT5[11], S5_CLKOUT5[8], S5_CLKOUT5[9], S5_CLKOUT5[6], //bits 15 downto 11 + S5_CLKOUT5[7], S5_CLKOUT5[20], S5_CLKOUT5[13], 2'h0, S5_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S5_CLKOUT5[5], S5_CLKOUT5[21], S5_CLKOUT5[12], S5_CLKOUT5[4]}; //bits 3 downto 0 - rom[102] = {5'h0F, 16'h0003, S5_CLKFBOUT[4], S5_CLKFBOUT[5], S5_CLKFBOUT[3], S5_CLKFBOUT[12], S5_CLKFBOUT[1], //bits 15 downto 11 - S5_CLKFBOUT[2], S5_CLKFBOUT[0], S5_CLKFBOUT[19], S5_CLKFBOUT[18], S5_CLKFBOUT[17], //bits 10 downto 6 - S5_CLKFBOUT[15], S5_CLKFBOUT[16], S5_CLKOUT0[12], S5_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[102] = {5'h0F, 16'h0003, S5_CLKFBOUT[4], S5_CLKFBOUT[5], S5_CLKFBOUT[3], S5_CLKFBOUT[12], S5_CLKFBOUT[1], //bits 15 downto 11 + S5_CLKFBOUT[2], S5_CLKFBOUT[0], S5_CLKFBOUT[19], S5_CLKFBOUT[18], S5_CLKFBOUT[17], //bits 10 downto 6 + S5_CLKFBOUT[15], S5_CLKFBOUT[16], S5_CLKOUT0[12], S5_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[103] = {5'h10, 16'h800C, 1'b0, S5_CLKOUT0[9], S5_CLKOUT0[11], S5_CLKOUT0[10], S5_CLKFBOUT[10], S5_CLKFBOUT[11], //bits 15 downto 10 - S5_CLKFBOUT[9], S5_CLKFBOUT[8], S5_CLKFBOUT[7], S5_CLKFBOUT[6], S5_CLKFBOUT[13], //bits 9 downto 5 - S5_CLKFBOUT[20], 2'h0, S5_CLKFBOUT[21], S5_CLKFBOUT[22]}; //bits 4 downto 0 + rom[103] = {5'h10, 16'h800C, 1'b0, S5_CLKOUT0[9], S5_CLKOUT0[11], S5_CLKOUT0[10], S5_CLKFBOUT[10], S5_CLKFBOUT[11], //bits 15 downto 10 + S5_CLKFBOUT[9], S5_CLKFBOUT[8], S5_CLKFBOUT[7], S5_CLKFBOUT[6], S5_CLKFBOUT[13], //bits 9 downto 5 + S5_CLKFBOUT[20], 2'h0, S5_CLKFBOUT[21], S5_CLKFBOUT[22]}; //bits 4 downto 0 - rom[104] = {5'h11, 16'hFC00, 6'h00, S5_CLKOUT3[3], S5_CLKOUT3[16], S5_CLKOUT2[11], S5_CLKOUT2[1], S5_CLKOUT1[18], //bits 15 downto 6 - S5_CLKOUT1[0], S5_CLKOUT0[6], S5_CLKOUT0[20], S5_CLKOUT0[8], S5_CLKOUT0[7]}; //bits 5 downto 0 + rom[104] = {5'h11, 16'hFC00, 6'h00, S5_CLKOUT3[3], S5_CLKOUT3[16], S5_CLKOUT2[11], S5_CLKOUT2[1], S5_CLKOUT1[18], //bits 15 downto 6 + S5_CLKOUT1[0], S5_CLKOUT0[6], S5_CLKOUT0[20], S5_CLKOUT0[8], S5_CLKOUT0[7]}; //bits 5 downto 0 - rom[105] = {5'h12, 16'hF0FF, 4'h0, S5_CLKOUT5[14], S5_CLKFBOUT[14], S5_CLKOUT4[0], S5_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[105] = {5'h12, 16'hF0FF, 4'h0, S5_CLKOUT5[14], S5_CLKFBOUT[14], S5_CLKOUT4[0], S5_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[106] = {5'h13, 16'h5120, S5_DIVCLK[11], 1'b0, S5_DIVCLK[10], 1'b0, S5_DIVCLK[7], S5_DIVCLK[8], //bits 15 downto 10 - S5_DIVCLK[0], 1'b0, S5_DIVCLK[5], S5_DIVCLK[2], 1'b0, S5_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[106] = {5'h13, 16'h5120, S5_DIVCLK[11], 1'b0, S5_DIVCLK[10], 1'b0, S5_DIVCLK[7], S5_DIVCLK[8], //bits 15 downto 10 + S5_DIVCLK[0], 1'b0, S5_DIVCLK[5], S5_DIVCLK[2], 1'b0, S5_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[107] = {5'h14, 16'h2FFF, S5_LOCK[1], S5_LOCK[2], 1'b0, S5_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[107] = {5'h14, 16'h2FFF, S5_LOCK[1], S5_LOCK[2], 1'b0, S5_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[108] = {5'h15, 16'hBFF4, 1'b0, S5_DIVCLK[12], 10'h000, S5_LOCK[38], 1'b0, S5_LOCK[32], S5_LOCK[39]}; //bits 15 downto 0 + rom[108] = {5'h15, 16'hBFF4, 1'b0, S5_DIVCLK[12], 10'h000, S5_LOCK[38], 1'b0, S5_LOCK[32], S5_LOCK[39]}; //bits 15 downto 0 - rom[109] = {5'h16, 16'h0A55, S5_LOCK[15], S5_LOCK[13], S5_LOCK[27], S5_LOCK[16], 1'b0, S5_LOCK[10], //bits 15 downto 10 - 1'b0, S5_DIVCLK[9], S5_DIVCLK[1], 1'b0, S5_DIVCLK[6], 1'b0, S5_DIVCLK[3], //bits 9 downto 3 - 1'b0, S5_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[109] = {5'h16, 16'h0A55, S5_LOCK[15], S5_LOCK[13], S5_LOCK[27], S5_LOCK[16], 1'b0, S5_LOCK[10], //bits 15 downto 10 + 1'b0, S5_DIVCLK[9], S5_DIVCLK[1], 1'b0, S5_DIVCLK[6], 1'b0, S5_DIVCLK[3], //bits 9 downto 3 + 1'b0, S5_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[110] = {5'h17, 16'hFFD0, 10'h000, S5_LOCK[17], 1'b0, S5_LOCK[8], S5_LOCK[9], S5_LOCK[23], S5_LOCK[22]}; //bits 15 downto 0 + rom[110] = {5'h17, 16'hFFD0, 10'h000, S5_LOCK[17], 1'b0, S5_LOCK[8], S5_LOCK[9], S5_LOCK[23], S5_LOCK[22]}; //bits 15 downto 0 - rom[111] = {5'h18, 16'h1039, S5_DIGITAL_FILT[6], S5_DIGITAL_FILT[7], S5_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S5_DIGITAL_FILT[2], S5_DIGITAL_FILT[1], S5_DIGITAL_FILT[3], S5_DIGITAL_FILT[9], //bits 11 downto 8 - S5_DIGITAL_FILT[8], S5_LOCK[26], 3'h0, S5_LOCK[19], S5_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[111] = {5'h18, 16'h1039, S5_DIGITAL_FILT[6], S5_DIGITAL_FILT[7], S5_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S5_DIGITAL_FILT[2], S5_DIGITAL_FILT[1], S5_DIGITAL_FILT[3], S5_DIGITAL_FILT[9], //bits 11 downto 8 + S5_DIGITAL_FILT[8], S5_LOCK[26], 3'h0, S5_LOCK[19], S5_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[112] = {5'h19, 16'h0000, S5_LOCK[24], S5_LOCK[25], S5_LOCK[21], S5_LOCK[14], S5_LOCK[11], //bits 15 downto 11 - S5_LOCK[12], S5_LOCK[20], S5_LOCK[6], S5_LOCK[35], S5_LOCK[36], //bits 10 downto 6 - S5_LOCK[37], S5_LOCK[3], S5_LOCK[33], S5_LOCK[31], S5_LOCK[34], S5_LOCK[30]}; //bits 5 downto 0 + rom[112] = {5'h19, 16'h0000, S5_LOCK[24], S5_LOCK[25], S5_LOCK[21], S5_LOCK[14], S5_LOCK[11], //bits 15 downto 11 + S5_LOCK[12], S5_LOCK[20], S5_LOCK[6], S5_LOCK[35], S5_LOCK[36], //bits 10 downto 6 + S5_LOCK[37], S5_LOCK[3], S5_LOCK[33], S5_LOCK[31], S5_LOCK[34], S5_LOCK[30]}; //bits 5 downto 0 - rom[113] = {5'h1A, 16'hFFFC, 14'h0000, S5_LOCK[28], S5_LOCK[29]}; //bits 15 downto 0 + rom[113] = {5'h1A, 16'hFFFC, 14'h0000, S5_LOCK[28], S5_LOCK[29]}; //bits 15 downto 0 - rom[114] = {5'h1D, 16'h2FFF, S5_LOCK[7], S5_LOCK[4], 1'b0, S5_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[114] = {5'h1D, 16'h2FFF, S5_LOCK[7], S5_LOCK[4], 1'b0, S5_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 6 Initialization //*********************************************************************** rom[115] = {5'h05, 16'h50FF, S6_CLKOUT0[19], 1'b0, S6_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S6_CLKOUT0[16], S6_CLKOUT0[17], S6_CLKOUT0[15], S6_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S6_CLKOUT0[16], S6_CLKOUT0[17], S6_CLKOUT0[15], S6_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[116] = {5'h06, 16'h010B, S6_CLKOUT1[4], S6_CLKOUT1[5], S6_CLKOUT1[3], S6_CLKOUT1[12], //bits 15 down to 12 - S6_CLKOUT1[1], S6_CLKOUT1[2], S6_CLKOUT1[19], 1'b0, S6_CLKOUT1[17], S6_CLKOUT1[16], //bits 11 down to 6 - S6_CLKOUT1[14], S6_CLKOUT1[15], 1'b0, S6_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[116] = {5'h06, 16'h010B, S6_CLKOUT1[4], S6_CLKOUT1[5], S6_CLKOUT1[3], S6_CLKOUT1[12], //bits 15 down to 12 + S6_CLKOUT1[1], S6_CLKOUT1[2], S6_CLKOUT1[19], 1'b0, S6_CLKOUT1[17], S6_CLKOUT1[16], //bits 11 down to 6 + S6_CLKOUT1[14], S6_CLKOUT1[15], 1'b0, S6_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[117] = {5'h07, 16'hE02C, 3'h0, S6_CLKOUT1[11], S6_CLKOUT1[9], S6_CLKOUT1[10], //bits 15 down to 10 - S6_CLKOUT1[8], S6_CLKOUT1[7], S6_CLKOUT1[6], S6_CLKOUT1[20], 1'b0, S6_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S6_CLKOUT1[21], S6_CLKOUT1[22]}; //bits 3 down to 0 + rom[117] = {5'h07, 16'hE02C, 3'h0, S6_CLKOUT1[11], S6_CLKOUT1[9], S6_CLKOUT1[10], //bits 15 down to 10 + S6_CLKOUT1[8], S6_CLKOUT1[7], S6_CLKOUT1[6], S6_CLKOUT1[20], 1'b0, S6_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S6_CLKOUT1[21], S6_CLKOUT1[22]}; //bits 3 down to 0 - rom[118] = {5'h08, 16'h4001, S6_CLKOUT2[22], 1'b0, S6_CLKOUT2[5], S6_CLKOUT2[21], //bits 15 downto 12 - S6_CLKOUT2[12], S6_CLKOUT2[4], S6_CLKOUT2[3], S6_CLKOUT2[2], S6_CLKOUT2[0], S6_CLKOUT2[19], //bits 11 down to 6 - S6_CLKOUT2[17], S6_CLKOUT2[18], S6_CLKOUT2[15], S6_CLKOUT2[16], S6_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[118] = {5'h08, 16'h4001, S6_CLKOUT2[22], 1'b0, S6_CLKOUT2[5], S6_CLKOUT2[21], //bits 15 downto 12 + S6_CLKOUT2[12], S6_CLKOUT2[4], S6_CLKOUT2[3], S6_CLKOUT2[2], S6_CLKOUT2[0], S6_CLKOUT2[19], //bits 11 down to 6 + S6_CLKOUT2[17], S6_CLKOUT2[18], S6_CLKOUT2[15], S6_CLKOUT2[16], S6_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[119] = {5'h09, 16'h0D03, S6_CLKOUT3[14], S6_CLKOUT3[15], S6_CLKOUT0[21], S6_CLKOUT0[22], 2'h0, S6_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S6_CLKOUT2[9], S6_CLKOUT2[8], S6_CLKOUT2[6], S6_CLKOUT2[7], S6_CLKOUT2[13], S6_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[119] = {5'h09, 16'h0D03, S6_CLKOUT3[14], S6_CLKOUT3[15], S6_CLKOUT0[21], S6_CLKOUT0[22], 2'h0, S6_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S6_CLKOUT2[9], S6_CLKOUT2[8], S6_CLKOUT2[6], S6_CLKOUT2[7], S6_CLKOUT2[13], S6_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[120] = {5'h0A, 16'hB001, 1'b0, S6_CLKOUT3[13], 2'h0, S6_CLKOUT3[21], S6_CLKOUT3[22], S6_CLKOUT3[5], S6_CLKOUT3[4], //bits 15 downto 8 - S6_CLKOUT3[12], S6_CLKOUT3[2], S6_CLKOUT3[0], S6_CLKOUT3[1], S6_CLKOUT3[18], S6_CLKOUT3[19], //bits 7 downto 2 - S6_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[120] = {5'h0A, 16'hB001, 1'b0, S6_CLKOUT3[13], 2'h0, S6_CLKOUT3[21], S6_CLKOUT3[22], S6_CLKOUT3[5], S6_CLKOUT3[4], //bits 15 downto 8 + S6_CLKOUT3[12], S6_CLKOUT3[2], S6_CLKOUT3[0], S6_CLKOUT3[1], S6_CLKOUT3[18], S6_CLKOUT3[19], //bits 7 downto 2 + S6_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[121] = {5'h0B, 16'h0110, S6_CLKOUT0[5], S6_CLKOUT4[19], S6_CLKOUT4[14], S6_CLKOUT4[17], //bits 15 downto 12 - S6_CLKOUT4[15], S6_CLKOUT4[16], S6_CLKOUT0[4], 1'b0, S6_CLKOUT3[11], S6_CLKOUT3[10], //bits 11 downto 6 - S6_CLKOUT3[9], 1'b0, S6_CLKOUT3[7], S6_CLKOUT3[8], S6_CLKOUT3[20], S6_CLKOUT3[6]}; //bits 5 downto 0 + rom[121] = {5'h0B, 16'h0110, S6_CLKOUT0[5], S6_CLKOUT4[19], S6_CLKOUT4[14], S6_CLKOUT4[17], //bits 15 downto 12 + S6_CLKOUT4[15], S6_CLKOUT4[16], S6_CLKOUT0[4], 1'b0, S6_CLKOUT3[11], S6_CLKOUT3[10], //bits 11 downto 6 + S6_CLKOUT3[9], 1'b0, S6_CLKOUT3[7], S6_CLKOUT3[8], S6_CLKOUT3[20], S6_CLKOUT3[6]}; //bits 5 downto 0 - rom[122] = {5'h0C, 16'h0B00, S6_CLKOUT4[7], S6_CLKOUT4[8], S6_CLKOUT4[20], S6_CLKOUT4[6], 1'b0, S6_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S6_CLKOUT4[22], S6_CLKOUT4[21], S6_CLKOUT4[4], S6_CLKOUT4[5], S6_CLKOUT4[3], //bits 9 downto 3 - S6_CLKOUT4[12], S6_CLKOUT4[1], S6_CLKOUT4[2]}; //bits 2 downto 0 + rom[122] = {5'h0C, 16'h0B00, S6_CLKOUT4[7], S6_CLKOUT4[8], S6_CLKOUT4[20], S6_CLKOUT4[6], 1'b0, S6_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S6_CLKOUT4[22], S6_CLKOUT4[21], S6_CLKOUT4[4], S6_CLKOUT4[5], S6_CLKOUT4[3], //bits 9 downto 3 + S6_CLKOUT4[12], S6_CLKOUT4[1], S6_CLKOUT4[2]}; //bits 2 downto 0 - rom[123] = {5'h0D, 16'h0008, S6_CLKOUT5[2], S6_CLKOUT5[3], S6_CLKOUT5[0], S6_CLKOUT5[1], S6_CLKOUT5[18], //bits 15 downto 11 - S6_CLKOUT5[19], S6_CLKOUT5[17], S6_CLKOUT5[16], S6_CLKOUT5[15], S6_CLKOUT0[3], //bits 10 downto 6 - S6_CLKOUT0[0], S6_CLKOUT0[2], 1'b0, S6_CLKOUT4[11], S6_CLKOUT4[9], S6_CLKOUT4[10]}; //bits 5 downto 0 + rom[123] = {5'h0D, 16'h0008, S6_CLKOUT5[2], S6_CLKOUT5[3], S6_CLKOUT5[0], S6_CLKOUT5[1], S6_CLKOUT5[18], //bits 15 downto 11 + S6_CLKOUT5[19], S6_CLKOUT5[17], S6_CLKOUT5[16], S6_CLKOUT5[15], S6_CLKOUT0[3], //bits 10 downto 6 + S6_CLKOUT0[0], S6_CLKOUT0[2], 1'b0, S6_CLKOUT4[11], S6_CLKOUT4[9], S6_CLKOUT4[10]}; //bits 5 downto 0 - rom[124] = {5'h0E, 16'h00D0, S6_CLKOUT5[10], S6_CLKOUT5[11], S6_CLKOUT5[8], S6_CLKOUT5[9], S6_CLKOUT5[6], //bits 15 downto 11 - S6_CLKOUT5[7], S6_CLKOUT5[20], S6_CLKOUT5[13], 2'h0, S6_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S6_CLKOUT5[5], S6_CLKOUT5[21], S6_CLKOUT5[12], S6_CLKOUT5[4]}; //bits 3 downto 0 + rom[124] = {5'h0E, 16'h00D0, S6_CLKOUT5[10], S6_CLKOUT5[11], S6_CLKOUT5[8], S6_CLKOUT5[9], S6_CLKOUT5[6], //bits 15 downto 11 + S6_CLKOUT5[7], S6_CLKOUT5[20], S6_CLKOUT5[13], 2'h0, S6_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S6_CLKOUT5[5], S6_CLKOUT5[21], S6_CLKOUT5[12], S6_CLKOUT5[4]}; //bits 3 downto 0 - rom[125] = {5'h0F, 16'h0003, S6_CLKFBOUT[4], S6_CLKFBOUT[5], S6_CLKFBOUT[3], S6_CLKFBOUT[12], S6_CLKFBOUT[1], //bits 15 downto 11 - S6_CLKFBOUT[2], S6_CLKFBOUT[0], S6_CLKFBOUT[19], S6_CLKFBOUT[18], S6_CLKFBOUT[17], //bits 10 downto 6 - S6_CLKFBOUT[15], S6_CLKFBOUT[16], S6_CLKOUT0[12], S6_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[125] = {5'h0F, 16'h0003, S6_CLKFBOUT[4], S6_CLKFBOUT[5], S6_CLKFBOUT[3], S6_CLKFBOUT[12], S6_CLKFBOUT[1], //bits 15 downto 11 + S6_CLKFBOUT[2], S6_CLKFBOUT[0], S6_CLKFBOUT[19], S6_CLKFBOUT[18], S6_CLKFBOUT[17], //bits 10 downto 6 + S6_CLKFBOUT[15], S6_CLKFBOUT[16], S6_CLKOUT0[12], S6_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[126] = {5'h10, 16'h800C, 1'b0, S6_CLKOUT0[9], S6_CLKOUT0[11], S6_CLKOUT0[10], S6_CLKFBOUT[10], S6_CLKFBOUT[11], //bits 15 downto 10 - S6_CLKFBOUT[9], S6_CLKFBOUT[8], S6_CLKFBOUT[7], S6_CLKFBOUT[6], S6_CLKFBOUT[13], //bits 9 downto 5 - S6_CLKFBOUT[20], 2'h0, S6_CLKFBOUT[21], S6_CLKFBOUT[22]}; //bits 4 downto 0 + rom[126] = {5'h10, 16'h800C, 1'b0, S6_CLKOUT0[9], S6_CLKOUT0[11], S6_CLKOUT0[10], S6_CLKFBOUT[10], S6_CLKFBOUT[11], //bits 15 downto 10 + S6_CLKFBOUT[9], S6_CLKFBOUT[8], S6_CLKFBOUT[7], S6_CLKFBOUT[6], S6_CLKFBOUT[13], //bits 9 downto 5 + S6_CLKFBOUT[20], 2'h0, S6_CLKFBOUT[21], S6_CLKFBOUT[22]}; //bits 4 downto 0 - rom[127] = {5'h11, 16'hFC00, 6'h00, S6_CLKOUT3[3], S6_CLKOUT3[16], S6_CLKOUT2[11], S6_CLKOUT2[1], S6_CLKOUT1[18], //bits 15 downto 6 - S6_CLKOUT1[0], S6_CLKOUT0[6], S6_CLKOUT0[20], S6_CLKOUT0[8], S6_CLKOUT0[7]}; //bits 5 downto 0 + rom[127] = {5'h11, 16'hFC00, 6'h00, S6_CLKOUT3[3], S6_CLKOUT3[16], S6_CLKOUT2[11], S6_CLKOUT2[1], S6_CLKOUT1[18], //bits 15 downto 6 + S6_CLKOUT1[0], S6_CLKOUT0[6], S6_CLKOUT0[20], S6_CLKOUT0[8], S6_CLKOUT0[7]}; //bits 5 downto 0 - rom[128] = {5'h12, 16'hF0FF, 4'h0, S6_CLKOUT5[14], S6_CLKFBOUT[14], S6_CLKOUT4[0], S6_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[128] = {5'h12, 16'hF0FF, 4'h0, S6_CLKOUT5[14], S6_CLKFBOUT[14], S6_CLKOUT4[0], S6_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[129] = {5'h13, 16'h5120, S6_DIVCLK[11], 1'b0, S6_DIVCLK[10], 1'b0, S6_DIVCLK[7], S6_DIVCLK[8], //bits 15 downto 10 - S6_DIVCLK[0], 1'b0, S6_DIVCLK[5], S6_DIVCLK[2], 1'b0, S6_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[129] = {5'h13, 16'h5120, S6_DIVCLK[11], 1'b0, S6_DIVCLK[10], 1'b0, S6_DIVCLK[7], S6_DIVCLK[8], //bits 15 downto 10 + S6_DIVCLK[0], 1'b0, S6_DIVCLK[5], S6_DIVCLK[2], 1'b0, S6_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[130] = {5'h14, 16'h2FFF, S6_LOCK[1], S6_LOCK[2], 1'b0, S6_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[130] = {5'h14, 16'h2FFF, S6_LOCK[1], S6_LOCK[2], 1'b0, S6_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[131] = {5'h15, 16'hBFF4, 1'b0, S6_DIVCLK[12], 10'h000, S6_LOCK[38], 1'b0, S6_LOCK[32], S6_LOCK[39]}; //bits 15 downto 0 + rom[131] = {5'h15, 16'hBFF4, 1'b0, S6_DIVCLK[12], 10'h000, S6_LOCK[38], 1'b0, S6_LOCK[32], S6_LOCK[39]}; //bits 15 downto 0 - rom[132] = {5'h16, 16'h0A55, S6_LOCK[15], S6_LOCK[13], S6_LOCK[27], S6_LOCK[16], 1'b0, S6_LOCK[10], //bits 15 downto 10 - 1'b0, S6_DIVCLK[9], S6_DIVCLK[1], 1'b0, S6_DIVCLK[6], 1'b0, S6_DIVCLK[3], //bits 9 downto 3 - 1'b0, S6_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[132] = {5'h16, 16'h0A55, S6_LOCK[15], S6_LOCK[13], S6_LOCK[27], S6_LOCK[16], 1'b0, S6_LOCK[10], //bits 15 downto 10 + 1'b0, S6_DIVCLK[9], S6_DIVCLK[1], 1'b0, S6_DIVCLK[6], 1'b0, S6_DIVCLK[3], //bits 9 downto 3 + 1'b0, S6_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[133] = {5'h17, 16'hFFD0, 10'h000, S6_LOCK[17], 1'b0, S6_LOCK[8], S6_LOCK[9], S6_LOCK[23], S6_LOCK[22]}; //bits 15 downto 0 + rom[133] = {5'h17, 16'hFFD0, 10'h000, S6_LOCK[17], 1'b0, S6_LOCK[8], S6_LOCK[9], S6_LOCK[23], S6_LOCK[22]}; //bits 15 downto 0 - rom[134] = {5'h18, 16'h1039, S6_DIGITAL_FILT[6], S6_DIGITAL_FILT[7], S6_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S6_DIGITAL_FILT[2], S6_DIGITAL_FILT[1], S6_DIGITAL_FILT[3], S6_DIGITAL_FILT[9], //bits 11 downto 8 - S6_DIGITAL_FILT[8], S6_LOCK[26], 3'h0, S6_LOCK[19], S6_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[134] = {5'h18, 16'h1039, S6_DIGITAL_FILT[6], S6_DIGITAL_FILT[7], S6_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S6_DIGITAL_FILT[2], S6_DIGITAL_FILT[1], S6_DIGITAL_FILT[3], S6_DIGITAL_FILT[9], //bits 11 downto 8 + S6_DIGITAL_FILT[8], S6_LOCK[26], 3'h0, S6_LOCK[19], S6_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[135] = {5'h19, 16'h0000, S6_LOCK[24], S6_LOCK[25], S6_LOCK[21], S6_LOCK[14], S6_LOCK[11], //bits 15 downto 11 - S6_LOCK[12], S6_LOCK[20], S6_LOCK[6], S6_LOCK[35], S6_LOCK[36], //bits 10 downto 6 - S6_LOCK[37], S6_LOCK[3], S6_LOCK[33], S6_LOCK[31], S6_LOCK[34], S6_LOCK[30]}; //bits 5 downto 0 + rom[135] = {5'h19, 16'h0000, S6_LOCK[24], S6_LOCK[25], S6_LOCK[21], S6_LOCK[14], S6_LOCK[11], //bits 15 downto 11 + S6_LOCK[12], S6_LOCK[20], S6_LOCK[6], S6_LOCK[35], S6_LOCK[36], //bits 10 downto 6 + S6_LOCK[37], S6_LOCK[3], S6_LOCK[33], S6_LOCK[31], S6_LOCK[34], S6_LOCK[30]}; //bits 5 downto 0 - rom[136] = {5'h1A, 16'hFFFC, 14'h0000, S6_LOCK[28], S6_LOCK[29]}; //bits 15 downto 0 + rom[136] = {5'h1A, 16'hFFFC, 14'h0000, S6_LOCK[28], S6_LOCK[29]}; //bits 15 downto 0 - rom[137] = {5'h1D, 16'h2FFF, S6_LOCK[7], S6_LOCK[4], 1'b0, S6_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[137] = {5'h1D, 16'h2FFF, S6_LOCK[7], S6_LOCK[4], 1'b0, S6_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 7 Initialization //*********************************************************************** rom[138] = {5'h05, 16'h50FF, S7_CLKOUT0[19], 1'b0, S7_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S7_CLKOUT0[16], S7_CLKOUT0[17], S7_CLKOUT0[15], S7_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S7_CLKOUT0[16], S7_CLKOUT0[17], S7_CLKOUT0[15], S7_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[139] = {5'h06, 16'h010B, S7_CLKOUT1[4], S7_CLKOUT1[5], S7_CLKOUT1[3], S7_CLKOUT1[12], //bits 15 down to 12 - S7_CLKOUT1[1], S7_CLKOUT1[2], S7_CLKOUT1[19], 1'b0, S7_CLKOUT1[17], S7_CLKOUT1[16], //bits 11 down to 6 - S7_CLKOUT1[14], S7_CLKOUT1[15], 1'b0, S7_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[139] = {5'h06, 16'h010B, S7_CLKOUT1[4], S7_CLKOUT1[5], S7_CLKOUT1[3], S7_CLKOUT1[12], //bits 15 down to 12 + S7_CLKOUT1[1], S7_CLKOUT1[2], S7_CLKOUT1[19], 1'b0, S7_CLKOUT1[17], S7_CLKOUT1[16], //bits 11 down to 6 + S7_CLKOUT1[14], S7_CLKOUT1[15], 1'b0, S7_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[140] = {5'h07, 16'hE02C, 3'h0, S7_CLKOUT1[11], S7_CLKOUT1[9], S7_CLKOUT1[10], //bits 15 down to 10 - S7_CLKOUT1[8], S7_CLKOUT1[7], S7_CLKOUT1[6], S7_CLKOUT1[20], 1'b0, S7_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S7_CLKOUT1[21], S7_CLKOUT1[22]}; //bits 3 down to 0 + rom[140] = {5'h07, 16'hE02C, 3'h0, S7_CLKOUT1[11], S7_CLKOUT1[9], S7_CLKOUT1[10], //bits 15 down to 10 + S7_CLKOUT1[8], S7_CLKOUT1[7], S7_CLKOUT1[6], S7_CLKOUT1[20], 1'b0, S7_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S7_CLKOUT1[21], S7_CLKOUT1[22]}; //bits 3 down to 0 - rom[141] = {5'h08, 16'h4001, S7_CLKOUT2[22], 1'b0, S7_CLKOUT2[5], S7_CLKOUT2[21], //bits 15 downto 12 - S7_CLKOUT2[12], S7_CLKOUT2[4], S7_CLKOUT2[3], S7_CLKOUT2[2], S7_CLKOUT2[0], S7_CLKOUT2[19], //bits 11 down to 6 - S7_CLKOUT2[17], S7_CLKOUT2[18], S7_CLKOUT2[15], S7_CLKOUT2[16], S7_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[141] = {5'h08, 16'h4001, S7_CLKOUT2[22], 1'b0, S7_CLKOUT2[5], S7_CLKOUT2[21], //bits 15 downto 12 + S7_CLKOUT2[12], S7_CLKOUT2[4], S7_CLKOUT2[3], S7_CLKOUT2[2], S7_CLKOUT2[0], S7_CLKOUT2[19], //bits 11 down to 6 + S7_CLKOUT2[17], S7_CLKOUT2[18], S7_CLKOUT2[15], S7_CLKOUT2[16], S7_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[142] = {5'h09, 16'h0D03, S7_CLKOUT3[14], S7_CLKOUT3[15], S7_CLKOUT0[21], S7_CLKOUT0[22], 2'h0, S7_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S7_CLKOUT2[9], S7_CLKOUT2[8], S7_CLKOUT2[6], S7_CLKOUT2[7], S7_CLKOUT2[13], S7_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[142] = {5'h09, 16'h0D03, S7_CLKOUT3[14], S7_CLKOUT3[15], S7_CLKOUT0[21], S7_CLKOUT0[22], 2'h0, S7_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S7_CLKOUT2[9], S7_CLKOUT2[8], S7_CLKOUT2[6], S7_CLKOUT2[7], S7_CLKOUT2[13], S7_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[143] = {5'h0A, 16'hB001, 1'b0, S7_CLKOUT3[13], 2'h0, S7_CLKOUT3[21], S7_CLKOUT3[22], S7_CLKOUT3[5], S7_CLKOUT3[4], //bits 15 downto 8 - S7_CLKOUT3[12], S7_CLKOUT3[2], S7_CLKOUT3[0], S7_CLKOUT3[1], S7_CLKOUT3[18], S7_CLKOUT3[19], //bits 7 downto 2 - S7_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[143] = {5'h0A, 16'hB001, 1'b0, S7_CLKOUT3[13], 2'h0, S7_CLKOUT3[21], S7_CLKOUT3[22], S7_CLKOUT3[5], S7_CLKOUT3[4], //bits 15 downto 8 + S7_CLKOUT3[12], S7_CLKOUT3[2], S7_CLKOUT3[0], S7_CLKOUT3[1], S7_CLKOUT3[18], S7_CLKOUT3[19], //bits 7 downto 2 + S7_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[144] = {5'h0B, 16'h0110, S7_CLKOUT0[5], S7_CLKOUT4[19], S7_CLKOUT4[14], S7_CLKOUT4[17], //bits 15 downto 12 - S7_CLKOUT4[15], S7_CLKOUT4[16], S7_CLKOUT0[4], 1'b0, S7_CLKOUT3[11], S7_CLKOUT3[10], //bits 11 downto 6 - S7_CLKOUT3[9], 1'b0, S7_CLKOUT3[7], S7_CLKOUT3[8], S7_CLKOUT3[20], S7_CLKOUT3[6]}; //bits 5 downto 0 + rom[144] = {5'h0B, 16'h0110, S7_CLKOUT0[5], S7_CLKOUT4[19], S7_CLKOUT4[14], S7_CLKOUT4[17], //bits 15 downto 12 + S7_CLKOUT4[15], S7_CLKOUT4[16], S7_CLKOUT0[4], 1'b0, S7_CLKOUT3[11], S7_CLKOUT3[10], //bits 11 downto 6 + S7_CLKOUT3[9], 1'b0, S7_CLKOUT3[7], S7_CLKOUT3[8], S7_CLKOUT3[20], S7_CLKOUT3[6]}; //bits 5 downto 0 - rom[145] = {5'h0C, 16'h0B00, S7_CLKOUT4[7], S7_CLKOUT4[8], S7_CLKOUT4[20], S7_CLKOUT4[6], 1'b0, S7_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S7_CLKOUT4[22], S7_CLKOUT4[21], S7_CLKOUT4[4], S7_CLKOUT4[5], S7_CLKOUT4[3], //bits 9 downto 3 - S7_CLKOUT4[12], S7_CLKOUT4[1], S7_CLKOUT4[2]}; //bits 2 downto 0 + rom[145] = {5'h0C, 16'h0B00, S7_CLKOUT4[7], S7_CLKOUT4[8], S7_CLKOUT4[20], S7_CLKOUT4[6], 1'b0, S7_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S7_CLKOUT4[22], S7_CLKOUT4[21], S7_CLKOUT4[4], S7_CLKOUT4[5], S7_CLKOUT4[3], //bits 9 downto 3 + S7_CLKOUT4[12], S7_CLKOUT4[1], S7_CLKOUT4[2]}; //bits 2 downto 0 - rom[146] = {5'h0D, 16'h0008, S7_CLKOUT5[2], S7_CLKOUT5[3], S7_CLKOUT5[0], S7_CLKOUT5[1], S7_CLKOUT5[18], //bits 15 downto 11 - S7_CLKOUT5[19], S7_CLKOUT5[17], S7_CLKOUT5[16], S7_CLKOUT5[15], S7_CLKOUT0[3], //bits 10 downto 6 - S7_CLKOUT0[0], S7_CLKOUT0[2], 1'b0, S7_CLKOUT4[11], S7_CLKOUT4[9], S7_CLKOUT4[10]}; //bits 5 downto 0 + rom[146] = {5'h0D, 16'h0008, S7_CLKOUT5[2], S7_CLKOUT5[3], S7_CLKOUT5[0], S7_CLKOUT5[1], S7_CLKOUT5[18], //bits 15 downto 11 + S7_CLKOUT5[19], S7_CLKOUT5[17], S7_CLKOUT5[16], S7_CLKOUT5[15], S7_CLKOUT0[3], //bits 10 downto 6 + S7_CLKOUT0[0], S7_CLKOUT0[2], 1'b0, S7_CLKOUT4[11], S7_CLKOUT4[9], S7_CLKOUT4[10]}; //bits 5 downto 0 - rom[147] = {5'h0E, 16'h00D0, S7_CLKOUT5[10], S7_CLKOUT5[11], S7_CLKOUT5[8], S7_CLKOUT5[9], S7_CLKOUT5[6], //bits 15 downto 11 - S7_CLKOUT5[7], S7_CLKOUT5[20], S7_CLKOUT5[13], 2'h0, S7_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S7_CLKOUT5[5], S7_CLKOUT5[21], S7_CLKOUT5[12], S7_CLKOUT5[4]}; //bits 3 downto 0 + rom[147] = {5'h0E, 16'h00D0, S7_CLKOUT5[10], S7_CLKOUT5[11], S7_CLKOUT5[8], S7_CLKOUT5[9], S7_CLKOUT5[6], //bits 15 downto 11 + S7_CLKOUT5[7], S7_CLKOUT5[20], S7_CLKOUT5[13], 2'h0, S7_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S7_CLKOUT5[5], S7_CLKOUT5[21], S7_CLKOUT5[12], S7_CLKOUT5[4]}; //bits 3 downto 0 - rom[148] = {5'h0F, 16'h0003, S7_CLKFBOUT[4], S7_CLKFBOUT[5], S7_CLKFBOUT[3], S7_CLKFBOUT[12], S7_CLKFBOUT[1], //bits 15 downto 11 - S7_CLKFBOUT[2], S7_CLKFBOUT[0], S7_CLKFBOUT[19], S7_CLKFBOUT[18], S7_CLKFBOUT[17], //bits 10 downto 6 - S7_CLKFBOUT[15], S7_CLKFBOUT[16], S7_CLKOUT0[12], S7_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[148] = {5'h0F, 16'h0003, S7_CLKFBOUT[4], S7_CLKFBOUT[5], S7_CLKFBOUT[3], S7_CLKFBOUT[12], S7_CLKFBOUT[1], //bits 15 downto 11 + S7_CLKFBOUT[2], S7_CLKFBOUT[0], S7_CLKFBOUT[19], S7_CLKFBOUT[18], S7_CLKFBOUT[17], //bits 10 downto 6 + S7_CLKFBOUT[15], S7_CLKFBOUT[16], S7_CLKOUT0[12], S7_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[149] = {5'h10, 16'h800C, 1'b0, S7_CLKOUT0[9], S7_CLKOUT0[11], S7_CLKOUT0[10], S7_CLKFBOUT[10], S7_CLKFBOUT[11], //bits 15 downto 10 - S7_CLKFBOUT[9], S7_CLKFBOUT[8], S7_CLKFBOUT[7], S7_CLKFBOUT[6], S7_CLKFBOUT[13], //bits 9 downto 5 - S7_CLKFBOUT[20], 2'h0, S7_CLKFBOUT[21], S7_CLKFBOUT[22]}; //bits 4 downto 0 + rom[149] = {5'h10, 16'h800C, 1'b0, S7_CLKOUT0[9], S7_CLKOUT0[11], S7_CLKOUT0[10], S7_CLKFBOUT[10], S7_CLKFBOUT[11], //bits 15 downto 10 + S7_CLKFBOUT[9], S7_CLKFBOUT[8], S7_CLKFBOUT[7], S7_CLKFBOUT[6], S7_CLKFBOUT[13], //bits 9 downto 5 + S7_CLKFBOUT[20], 2'h0, S7_CLKFBOUT[21], S7_CLKFBOUT[22]}; //bits 4 downto 0 - rom[150] = {5'h11, 16'hFC00, 6'h00, S7_CLKOUT3[3], S7_CLKOUT3[16], S7_CLKOUT2[11], S7_CLKOUT2[1], S7_CLKOUT1[18], //bits 15 downto 6 - S7_CLKOUT1[0], S7_CLKOUT0[6], S7_CLKOUT0[20], S7_CLKOUT0[8], S7_CLKOUT0[7]}; //bits 5 downto 0 + rom[150] = {5'h11, 16'hFC00, 6'h00, S7_CLKOUT3[3], S7_CLKOUT3[16], S7_CLKOUT2[11], S7_CLKOUT2[1], S7_CLKOUT1[18], //bits 15 downto 6 + S7_CLKOUT1[0], S7_CLKOUT0[6], S7_CLKOUT0[20], S7_CLKOUT0[8], S7_CLKOUT0[7]}; //bits 5 downto 0 - rom[151] = {5'h12, 16'hF0FF, 4'h0, S7_CLKOUT5[14], S7_CLKFBOUT[14], S7_CLKOUT4[0], S7_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[151] = {5'h12, 16'hF0FF, 4'h0, S7_CLKOUT5[14], S7_CLKFBOUT[14], S7_CLKOUT4[0], S7_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[152] = {5'h13, 16'h5120, S7_DIVCLK[11], 1'b0, S7_DIVCLK[10], 1'b0, S7_DIVCLK[7], S7_DIVCLK[8], //bits 15 downto 10 - S7_DIVCLK[0], 1'b0, S7_DIVCLK[5], S7_DIVCLK[2], 1'b0, S7_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[152] = {5'h13, 16'h5120, S7_DIVCLK[11], 1'b0, S7_DIVCLK[10], 1'b0, S7_DIVCLK[7], S7_DIVCLK[8], //bits 15 downto 10 + S7_DIVCLK[0], 1'b0, S7_DIVCLK[5], S7_DIVCLK[2], 1'b0, S7_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[153] = {5'h14, 16'h2FFF, S7_LOCK[1], S7_LOCK[2], 1'b0, S7_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[153] = {5'h14, 16'h2FFF, S7_LOCK[1], S7_LOCK[2], 1'b0, S7_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[154] = {5'h15, 16'hBFF4, 1'b0, S7_DIVCLK[12], 10'h000, S7_LOCK[38], 1'b0, S7_LOCK[32], S7_LOCK[39]}; //bits 15 downto 0 + rom[154] = {5'h15, 16'hBFF4, 1'b0, S7_DIVCLK[12], 10'h000, S7_LOCK[38], 1'b0, S7_LOCK[32], S7_LOCK[39]}; //bits 15 downto 0 - rom[155] = {5'h16, 16'h0A55, S7_LOCK[15], S7_LOCK[13], S7_LOCK[27], S7_LOCK[16], 1'b0, S7_LOCK[10], //bits 15 downto 10 - 1'b0, S7_DIVCLK[9], S7_DIVCLK[1], 1'b0, S7_DIVCLK[6], 1'b0, S7_DIVCLK[3], //bits 9 downto 3 - 1'b0, S7_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[155] = {5'h16, 16'h0A55, S7_LOCK[15], S7_LOCK[13], S7_LOCK[27], S7_LOCK[16], 1'b0, S7_LOCK[10], //bits 15 downto 10 + 1'b0, S7_DIVCLK[9], S7_DIVCLK[1], 1'b0, S7_DIVCLK[6], 1'b0, S7_DIVCLK[3], //bits 9 downto 3 + 1'b0, S7_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[156] = {5'h17, 16'hFFD0, 10'h000, S7_LOCK[17], 1'b0, S7_LOCK[8], S7_LOCK[9], S7_LOCK[23], S7_LOCK[22]}; //bits 15 downto 0 + rom[156] = {5'h17, 16'hFFD0, 10'h000, S7_LOCK[17], 1'b0, S7_LOCK[8], S7_LOCK[9], S7_LOCK[23], S7_LOCK[22]}; //bits 15 downto 0 - rom[157] = {5'h18, 16'h1039, S7_DIGITAL_FILT[6], S7_DIGITAL_FILT[7], S7_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S7_DIGITAL_FILT[2], S7_DIGITAL_FILT[1], S7_DIGITAL_FILT[3], S7_DIGITAL_FILT[9], //bits 11 downto 8 - S7_DIGITAL_FILT[8], S7_LOCK[26], 3'h0, S7_LOCK[19], S7_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[157] = {5'h18, 16'h1039, S7_DIGITAL_FILT[6], S7_DIGITAL_FILT[7], S7_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S7_DIGITAL_FILT[2], S7_DIGITAL_FILT[1], S7_DIGITAL_FILT[3], S7_DIGITAL_FILT[9], //bits 11 downto 8 + S7_DIGITAL_FILT[8], S7_LOCK[26], 3'h0, S7_LOCK[19], S7_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[158] = {5'h19, 16'h0000, S7_LOCK[24], S7_LOCK[25], S7_LOCK[21], S7_LOCK[14], S7_LOCK[11], //bits 15 downto 11 - S7_LOCK[12], S7_LOCK[20], S7_LOCK[6], S7_LOCK[35], S7_LOCK[36], //bits 10 downto 6 - S7_LOCK[37], S7_LOCK[3], S7_LOCK[33], S7_LOCK[31], S7_LOCK[34], S7_LOCK[30]}; //bits 5 downto 0 + rom[158] = {5'h19, 16'h0000, S7_LOCK[24], S7_LOCK[25], S7_LOCK[21], S7_LOCK[14], S7_LOCK[11], //bits 15 downto 11 + S7_LOCK[12], S7_LOCK[20], S7_LOCK[6], S7_LOCK[35], S7_LOCK[36], //bits 10 downto 6 + S7_LOCK[37], S7_LOCK[3], S7_LOCK[33], S7_LOCK[31], S7_LOCK[34], S7_LOCK[30]}; //bits 5 downto 0 - rom[159] = {5'h1A, 16'hFFFC, 14'h0000, S7_LOCK[28], S7_LOCK[29]}; //bits 15 downto 0 + rom[159] = {5'h1A, 16'hFFFC, 14'h0000, S7_LOCK[28], S7_LOCK[29]}; //bits 15 downto 0 - rom[160] = {5'h1D, 16'h2FFF, S7_LOCK[7], S7_LOCK[4], 1'b0, S7_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[160] = {5'h1D, 16'h2FFF, S7_LOCK[7], S7_LOCK[4], 1'b0, S7_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 8 Initialization //*********************************************************************** rom[161] = {5'h05, 16'h50FF, S8_CLKOUT0[19], 1'b0, S8_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S8_CLKOUT0[16], S8_CLKOUT0[17], S8_CLKOUT0[15], S8_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S8_CLKOUT0[16], S8_CLKOUT0[17], S8_CLKOUT0[15], S8_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[162] = {5'h06, 16'h010B, S8_CLKOUT1[4], S8_CLKOUT1[5], S8_CLKOUT1[3], S8_CLKOUT1[12], //bits 15 down to 12 - S8_CLKOUT1[1], S8_CLKOUT1[2], S8_CLKOUT1[19], 1'b0, S8_CLKOUT1[17], S8_CLKOUT1[16], //bits 11 down to 6 - S8_CLKOUT1[14], S8_CLKOUT1[15], 1'b0, S8_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[162] = {5'h06, 16'h010B, S8_CLKOUT1[4], S8_CLKOUT1[5], S8_CLKOUT1[3], S8_CLKOUT1[12], //bits 15 down to 12 + S8_CLKOUT1[1], S8_CLKOUT1[2], S8_CLKOUT1[19], 1'b0, S8_CLKOUT1[17], S8_CLKOUT1[16], //bits 11 down to 6 + S8_CLKOUT1[14], S8_CLKOUT1[15], 1'b0, S8_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[163] = {5'h07, 16'hE02C, 3'h0, S8_CLKOUT1[11], S8_CLKOUT1[9], S8_CLKOUT1[10], //bits 15 down to 10 - S8_CLKOUT1[8], S8_CLKOUT1[7], S8_CLKOUT1[6], S8_CLKOUT1[20], 1'b0, S8_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S8_CLKOUT1[21], S8_CLKOUT1[22]}; //bits 3 down to 0 + rom[163] = {5'h07, 16'hE02C, 3'h0, S8_CLKOUT1[11], S8_CLKOUT1[9], S8_CLKOUT1[10], //bits 15 down to 10 + S8_CLKOUT1[8], S8_CLKOUT1[7], S8_CLKOUT1[6], S8_CLKOUT1[20], 1'b0, S8_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S8_CLKOUT1[21], S8_CLKOUT1[22]}; //bits 3 down to 0 - rom[164] = {5'h08, 16'h4001, S8_CLKOUT2[22], 1'b0, S8_CLKOUT2[5], S8_CLKOUT2[21], //bits 15 downto 12 - S8_CLKOUT2[12], S8_CLKOUT2[4], S8_CLKOUT2[3], S8_CLKOUT2[2], S8_CLKOUT2[0], S8_CLKOUT2[19], //bits 11 down to 6 - S8_CLKOUT2[17], S8_CLKOUT2[18], S8_CLKOUT2[15], S8_CLKOUT2[16], S8_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[164] = {5'h08, 16'h4001, S8_CLKOUT2[22], 1'b0, S8_CLKOUT2[5], S8_CLKOUT2[21], //bits 15 downto 12 + S8_CLKOUT2[12], S8_CLKOUT2[4], S8_CLKOUT2[3], S8_CLKOUT2[2], S8_CLKOUT2[0], S8_CLKOUT2[19], //bits 11 down to 6 + S8_CLKOUT2[17], S8_CLKOUT2[18], S8_CLKOUT2[15], S8_CLKOUT2[16], S8_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[165] = {5'h09, 16'h0D03, S8_CLKOUT3[14], S8_CLKOUT3[15], S8_CLKOUT0[21], S8_CLKOUT0[22], 2'h0, S8_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S8_CLKOUT2[9], S8_CLKOUT2[8], S8_CLKOUT2[6], S8_CLKOUT2[7], S8_CLKOUT2[13], S8_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[165] = {5'h09, 16'h0D03, S8_CLKOUT3[14], S8_CLKOUT3[15], S8_CLKOUT0[21], S8_CLKOUT0[22], 2'h0, S8_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S8_CLKOUT2[9], S8_CLKOUT2[8], S8_CLKOUT2[6], S8_CLKOUT2[7], S8_CLKOUT2[13], S8_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[166] = {5'h0A, 16'hB001, 1'b0, S8_CLKOUT3[13], 2'h0, S8_CLKOUT3[21], S8_CLKOUT3[22], S8_CLKOUT3[5], S8_CLKOUT3[4], //bits 15 downto 8 - S8_CLKOUT3[12], S8_CLKOUT3[2], S8_CLKOUT3[0], S8_CLKOUT3[1], S8_CLKOUT3[18], S8_CLKOUT3[19], //bits 7 downto 2 - S8_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[166] = {5'h0A, 16'hB001, 1'b0, S8_CLKOUT3[13], 2'h0, S8_CLKOUT3[21], S8_CLKOUT3[22], S8_CLKOUT3[5], S8_CLKOUT3[4], //bits 15 downto 8 + S8_CLKOUT3[12], S8_CLKOUT3[2], S8_CLKOUT3[0], S8_CLKOUT3[1], S8_CLKOUT3[18], S8_CLKOUT3[19], //bits 7 downto 2 + S8_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[167] = {5'h0B, 16'h0110, S8_CLKOUT0[5], S8_CLKOUT4[19], S8_CLKOUT4[14], S8_CLKOUT4[17], //bits 15 downto 12 - S8_CLKOUT4[15], S8_CLKOUT4[16], S8_CLKOUT0[4], 1'b0, S8_CLKOUT3[11], S8_CLKOUT3[10], //bits 11 downto 6 - S8_CLKOUT3[9], 1'b0, S8_CLKOUT3[7], S8_CLKOUT3[8], S8_CLKOUT3[20], S8_CLKOUT3[6]}; //bits 5 downto 0 + rom[167] = {5'h0B, 16'h0110, S8_CLKOUT0[5], S8_CLKOUT4[19], S8_CLKOUT4[14], S8_CLKOUT4[17], //bits 15 downto 12 + S8_CLKOUT4[15], S8_CLKOUT4[16], S8_CLKOUT0[4], 1'b0, S8_CLKOUT3[11], S8_CLKOUT3[10], //bits 11 downto 6 + S8_CLKOUT3[9], 1'b0, S8_CLKOUT3[7], S8_CLKOUT3[8], S8_CLKOUT3[20], S8_CLKOUT3[6]}; //bits 5 downto 0 - rom[168] = {5'h0C, 16'h0B00, S8_CLKOUT4[7], S8_CLKOUT4[8], S8_CLKOUT4[20], S8_CLKOUT4[6], 1'b0, S8_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S8_CLKOUT4[22], S8_CLKOUT4[21], S8_CLKOUT4[4], S8_CLKOUT4[5], S8_CLKOUT4[3], //bits 9 downto 3 - S8_CLKOUT4[12], S8_CLKOUT4[1], S8_CLKOUT4[2]}; //bits 2 downto 0 + rom[168] = {5'h0C, 16'h0B00, S8_CLKOUT4[7], S8_CLKOUT4[8], S8_CLKOUT4[20], S8_CLKOUT4[6], 1'b0, S8_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S8_CLKOUT4[22], S8_CLKOUT4[21], S8_CLKOUT4[4], S8_CLKOUT4[5], S8_CLKOUT4[3], //bits 9 downto 3 + S8_CLKOUT4[12], S8_CLKOUT4[1], S8_CLKOUT4[2]}; //bits 2 downto 0 - rom[169] = {5'h0D, 16'h0008, S8_CLKOUT5[2], S8_CLKOUT5[3], S8_CLKOUT5[0], S8_CLKOUT5[1], S8_CLKOUT5[18], //bits 15 downto 11 - S8_CLKOUT5[19], S8_CLKOUT5[17], S8_CLKOUT5[16], S8_CLKOUT5[15], S8_CLKOUT0[3], //bits 10 downto 6 - S8_CLKOUT0[0], S8_CLKOUT0[2], 1'b0, S8_CLKOUT4[11], S8_CLKOUT4[9], S8_CLKOUT4[10]}; //bits 5 downto 0 + rom[169] = {5'h0D, 16'h0008, S8_CLKOUT5[2], S8_CLKOUT5[3], S8_CLKOUT5[0], S8_CLKOUT5[1], S8_CLKOUT5[18], //bits 15 downto 11 + S8_CLKOUT5[19], S8_CLKOUT5[17], S8_CLKOUT5[16], S8_CLKOUT5[15], S8_CLKOUT0[3], //bits 10 downto 6 + S8_CLKOUT0[0], S8_CLKOUT0[2], 1'b0, S8_CLKOUT4[11], S8_CLKOUT4[9], S8_CLKOUT4[10]}; //bits 5 downto 0 - rom[170] = {5'h0E, 16'h00D0, S8_CLKOUT5[10], S8_CLKOUT5[11], S8_CLKOUT5[8], S8_CLKOUT5[9], S8_CLKOUT5[6], //bits 15 downto 11 - S8_CLKOUT5[7], S8_CLKOUT5[20], S8_CLKOUT5[13], 2'h0, S8_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S8_CLKOUT5[5], S8_CLKOUT5[21], S8_CLKOUT5[12], S8_CLKOUT5[4]}; //bits 3 downto 0 + rom[170] = {5'h0E, 16'h00D0, S8_CLKOUT5[10], S8_CLKOUT5[11], S8_CLKOUT5[8], S8_CLKOUT5[9], S8_CLKOUT5[6], //bits 15 downto 11 + S8_CLKOUT5[7], S8_CLKOUT5[20], S8_CLKOUT5[13], 2'h0, S8_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S8_CLKOUT5[5], S8_CLKOUT5[21], S8_CLKOUT5[12], S8_CLKOUT5[4]}; //bits 3 downto 0 - rom[171] = {5'h0F, 16'h0003, S8_CLKFBOUT[4], S8_CLKFBOUT[5], S8_CLKFBOUT[3], S8_CLKFBOUT[12], S8_CLKFBOUT[1], //bits 15 downto 11 - S8_CLKFBOUT[2], S8_CLKFBOUT[0], S8_CLKFBOUT[19], S8_CLKFBOUT[18], S8_CLKFBOUT[17], //bits 10 downto 6 - S8_CLKFBOUT[15], S8_CLKFBOUT[16], S8_CLKOUT0[12], S8_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[171] = {5'h0F, 16'h0003, S8_CLKFBOUT[4], S8_CLKFBOUT[5], S8_CLKFBOUT[3], S8_CLKFBOUT[12], S8_CLKFBOUT[1], //bits 15 downto 11 + S8_CLKFBOUT[2], S8_CLKFBOUT[0], S8_CLKFBOUT[19], S8_CLKFBOUT[18], S8_CLKFBOUT[17], //bits 10 downto 6 + S8_CLKFBOUT[15], S8_CLKFBOUT[16], S8_CLKOUT0[12], S8_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[172] = {5'h10, 16'h800C, 1'b0, S8_CLKOUT0[9], S8_CLKOUT0[11], S8_CLKOUT0[10], S8_CLKFBOUT[10], S8_CLKFBOUT[11], //bits 15 downto 10 - S8_CLKFBOUT[9], S8_CLKFBOUT[8], S8_CLKFBOUT[7], S8_CLKFBOUT[6], S8_CLKFBOUT[13], //bits 9 downto 5 - S8_CLKFBOUT[20], 2'h0, S8_CLKFBOUT[21], S8_CLKFBOUT[22]}; //bits 4 downto 0 + rom[172] = {5'h10, 16'h800C, 1'b0, S8_CLKOUT0[9], S8_CLKOUT0[11], S8_CLKOUT0[10], S8_CLKFBOUT[10], S8_CLKFBOUT[11], //bits 15 downto 10 + S8_CLKFBOUT[9], S8_CLKFBOUT[8], S8_CLKFBOUT[7], S8_CLKFBOUT[6], S8_CLKFBOUT[13], //bits 9 downto 5 + S8_CLKFBOUT[20], 2'h0, S8_CLKFBOUT[21], S8_CLKFBOUT[22]}; //bits 4 downto 0 - rom[173] = {5'h11, 16'hFC00, 6'h00, S8_CLKOUT3[3], S8_CLKOUT3[16], S8_CLKOUT2[11], S8_CLKOUT2[1], S8_CLKOUT1[18], //bits 15 downto 6 - S8_CLKOUT1[0], S8_CLKOUT0[6], S8_CLKOUT0[20], S8_CLKOUT0[8], S8_CLKOUT0[7]}; //bits 5 downto 0 + rom[173] = {5'h11, 16'hFC00, 6'h00, S8_CLKOUT3[3], S8_CLKOUT3[16], S8_CLKOUT2[11], S8_CLKOUT2[1], S8_CLKOUT1[18], //bits 15 downto 6 + S8_CLKOUT1[0], S8_CLKOUT0[6], S8_CLKOUT0[20], S8_CLKOUT0[8], S8_CLKOUT0[7]}; //bits 5 downto 0 - rom[174] = {5'h12, 16'hF0FF, 4'h0, S8_CLKOUT5[14], S8_CLKFBOUT[14], S8_CLKOUT4[0], S8_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[174] = {5'h12, 16'hF0FF, 4'h0, S8_CLKOUT5[14], S8_CLKFBOUT[14], S8_CLKOUT4[0], S8_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[175] = {5'h13, 16'h5120, S8_DIVCLK[11], 1'b0, S8_DIVCLK[10], 1'b0, S8_DIVCLK[7], S8_DIVCLK[8], //bits 15 downto 10 - S8_DIVCLK[0], 1'b0, S8_DIVCLK[5], S8_DIVCLK[2], 1'b0, S8_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[175] = {5'h13, 16'h5120, S8_DIVCLK[11], 1'b0, S8_DIVCLK[10], 1'b0, S8_DIVCLK[7], S8_DIVCLK[8], //bits 15 downto 10 + S8_DIVCLK[0], 1'b0, S8_DIVCLK[5], S8_DIVCLK[2], 1'b0, S8_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[176] = {5'h14, 16'h2FFF, S8_LOCK[1], S8_LOCK[2], 1'b0, S8_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[176] = {5'h14, 16'h2FFF, S8_LOCK[1], S8_LOCK[2], 1'b0, S8_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[177] = {5'h15, 16'hBFF4, 1'b0, S8_DIVCLK[12], 10'h000, S8_LOCK[38], 1'b0, S8_LOCK[32], S8_LOCK[39]}; //bits 15 downto 0 + rom[177] = {5'h15, 16'hBFF4, 1'b0, S8_DIVCLK[12], 10'h000, S8_LOCK[38], 1'b0, S8_LOCK[32], S8_LOCK[39]}; //bits 15 downto 0 - rom[178] = {5'h16, 16'h0A55, S8_LOCK[15], S8_LOCK[13], S8_LOCK[27], S8_LOCK[16], 1'b0, S8_LOCK[10], //bits 15 downto 10 - 1'b0, S8_DIVCLK[9], S8_DIVCLK[1], 1'b0, S8_DIVCLK[6], 1'b0, S8_DIVCLK[3], //bits 9 downto 3 - 1'b0, S8_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[178] = {5'h16, 16'h0A55, S8_LOCK[15], S8_LOCK[13], S8_LOCK[27], S8_LOCK[16], 1'b0, S8_LOCK[10], //bits 15 downto 10 + 1'b0, S8_DIVCLK[9], S8_DIVCLK[1], 1'b0, S8_DIVCLK[6], 1'b0, S8_DIVCLK[3], //bits 9 downto 3 + 1'b0, S8_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[179] = {5'h17, 16'hFFD0, 10'h000, S8_LOCK[17], 1'b0, S8_LOCK[8], S8_LOCK[9], S8_LOCK[23], S8_LOCK[22]}; //bits 15 downto 0 + rom[179] = {5'h17, 16'hFFD0, 10'h000, S8_LOCK[17], 1'b0, S8_LOCK[8], S8_LOCK[9], S8_LOCK[23], S8_LOCK[22]}; //bits 15 downto 0 - rom[180] = {5'h18, 16'h1039, S8_DIGITAL_FILT[6], S8_DIGITAL_FILT[7], S8_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S8_DIGITAL_FILT[2], S8_DIGITAL_FILT[1], S8_DIGITAL_FILT[3], S8_DIGITAL_FILT[9], //bits 11 downto 8 - S8_DIGITAL_FILT[8], S8_LOCK[26], 3'h0, S8_LOCK[19], S8_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[180] = {5'h18, 16'h1039, S8_DIGITAL_FILT[6], S8_DIGITAL_FILT[7], S8_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S8_DIGITAL_FILT[2], S8_DIGITAL_FILT[1], S8_DIGITAL_FILT[3], S8_DIGITAL_FILT[9], //bits 11 downto 8 + S8_DIGITAL_FILT[8], S8_LOCK[26], 3'h0, S8_LOCK[19], S8_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[181] = {5'h19, 16'h0000, S8_LOCK[24], S8_LOCK[25], S8_LOCK[21], S8_LOCK[14], S8_LOCK[11], //bits 15 downto 11 - S8_LOCK[12], S8_LOCK[20], S8_LOCK[6], S8_LOCK[35], S8_LOCK[36], //bits 10 downto 6 - S8_LOCK[37], S8_LOCK[3], S8_LOCK[33], S8_LOCK[31], S8_LOCK[34], S8_LOCK[30]}; //bits 5 downto 0 + rom[181] = {5'h19, 16'h0000, S8_LOCK[24], S8_LOCK[25], S8_LOCK[21], S8_LOCK[14], S8_LOCK[11], //bits 15 downto 11 + S8_LOCK[12], S8_LOCK[20], S8_LOCK[6], S8_LOCK[35], S8_LOCK[36], //bits 10 downto 6 + S8_LOCK[37], S8_LOCK[3], S8_LOCK[33], S8_LOCK[31], S8_LOCK[34], S8_LOCK[30]}; //bits 5 downto 0 - rom[182] = {5'h1A, 16'hFFFC, 14'h0000, S8_LOCK[28], S8_LOCK[29]}; //bits 15 downto 0 + rom[182] = {5'h1A, 16'hFFFC, 14'h0000, S8_LOCK[28], S8_LOCK[29]}; //bits 15 downto 0 - rom[183] = {5'h1D, 16'h2FFF, S8_LOCK[7], S8_LOCK[4], 1'b0, S8_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[183] = {5'h1D, 16'h2FFF, S8_LOCK[7], S8_LOCK[4], 1'b0, S8_LOCK[5], 12'h000}; //bits 15 downto 0 - // Initialize the rest of the ROM + // Initialize the rest of the ROM // for(ii = 46; ii < 64; ii = ii +1) begin // rom[ii] = 0; // end @@ -1537,7 +1537,7 @@ module pll_drp // State sync reg [3:0] current_state = RESTART; reg [3:0] next_state = RESTART; - + // State Definitions localparam RESTART = 4'h1; localparam WAIT_LOCK = 4'h2; @@ -1548,15 +1548,15 @@ module pll_drp localparam BITSET = 4'h7; localparam WRITE = 4'h8; localparam WAIT_DRDY = 4'h9; - - // These variables are used to keep track of the number of iterations that + + // These variables are used to keep track of the number of iterations that // each state takes to reconfigure // STATE_COUNT_CONST is used to reset the counters and should match the // number of registers necessary to reconfigure each state. localparam STATE_COUNT_CONST = 23; - reg [4:0] state_count = STATE_COUNT_CONST; + reg [4:0] state_count = STATE_COUNT_CONST; reg [4:0] next_state_count = STATE_COUNT_CONST; - + // This block assigns the next register value from the state machine below always @(posedge SCLK) begin DADDR <= #TCQ next_daddr; @@ -1564,13 +1564,13 @@ module pll_drp DEN <= #TCQ next_den; RST_PLL <= #TCQ next_rst_pll; DI <= #TCQ next_di; - + SRDY <= #TCQ next_srdy; - + rom_addr <= #TCQ next_rom_addr; state_count <= #TCQ next_state_count; end - + // This block assigns the next state, reset is syncronous. always @(posedge SCLK) begin if(RST) begin @@ -1579,7 +1579,7 @@ module pll_drp current_state <= #TCQ next_state; end end - + always @* begin // Setup the default values next_srdy = 1'b0; @@ -1590,7 +1590,7 @@ module pll_drp next_di = DI; next_rom_addr = rom_addr; next_state_count = state_count; - + case (current_state) // If RST is asserted reset the machine RESTART: begin @@ -1600,15 +1600,15 @@ module pll_drp next_rst_pll = 1'b1; next_state = WAIT_LOCK; end - + // Waits for the PLL to assert LOCKED - once it does asserts SRDY WAIT_LOCK: begin // Make sure reset is de-asserted next_rst_pll = 1'b0; - // Reset the number of registers left to write for the next + // Reset the number of registers left to write for the next // reconfiguration event. next_state_count = STATE_COUNT_CONST; - + if(LOCKED) begin // PLL is locked, go on to wait for the SEN signal next_state = WAIT_SEN; @@ -1620,8 +1620,8 @@ module pll_drp next_state = WAIT_LOCK; end end - - // Wait for the next SEN pulse and set the ROM addr appropriately + + // Wait for the next SEN pulse and set the ROM addr appropriately // based on SADDR WAIT_SEN: begin if(SEN) begin @@ -1667,7 +1667,7 @@ module pll_drp next_state = WAIT_A_DRDY; end end - + // Zero out the bits that are not set in the mask stored in rom BITMASK: begin // Do the mask @@ -1675,7 +1675,7 @@ module pll_drp // Go on to set the bits next_state = BITSET; end - + // After the input is masked, OR the bits with calculated value in rom BITSET: begin // Set the bits that need to be assigned @@ -1685,20 +1685,20 @@ module pll_drp // Go on to write the data to the PLL next_state = WRITE; end - + // DI is setup so assert DWE, DEN, and RST_PLL. Subtract one from the // state count and go to wait for DRDY. WRITE: begin // Set WE and EN on PLL next_dwe = 1'b1; next_den = 1'b1; - + // Decrement the number of registers left to write next_state_count = state_count - 1'b1; // Wait for the write to complete next_state = WAIT_DRDY; end - + // Wait for DRDY to assert from the PLL. If the state count is not 0 // jump to ADDRESS (continue reconfiguration). If state count is // 0 wait for lock. @@ -1718,12 +1718,12 @@ module pll_drp next_state = WAIT_DRDY; end end - + // If in an unknown state reset the machine default: begin next_state = RESTART; end endcase end - + endmodule diff --git a/cores/Spectrum/ula_radas.v b/cores/Spectrum/ula_radas.v index add2b97..dd4847e 100644 --- a/cores/Spectrum/ula_radas.v +++ b/cores/Spectrum/ula_radas.v @@ -57,6 +57,7 @@ module ula_radas ( input wire [1:0] mode, input wire disable_contention, input wire access_to_contmem, + output wire doc_ext_option, // Video output wire [2:0] r, @@ -174,16 +175,17 @@ module ula_radas ( end // Timex config register - reg [5:0] TimexConfigReg = 6'h00; + reg [7:0] TimexConfigReg = 8'h00; wire PG = TimexConfigReg[0]; wire HCL = TimexConfigReg[1]; wire HR = TimexConfigReg[2]; + assign doc_ext_option = TimexConfigReg[7]; wire [2:0] HRInk = TimexConfigReg[5:3]; always @(posedge clk7) begin if (rst_n == 1'b0) - TimexConfigReg <= 6'h00; + TimexConfigReg <= 8'h00; else if (TimexConfigLoad) - TimexConfigReg <= din[5:0]; + TimexConfigReg <= din; end // Combinational logic between AttrData and AttrOutput @@ -443,7 +445,7 @@ module ula_radas ( // Port 0xFE always @(posedge clk7) begin if (iorq_n==1'b0 && wr_n==1'b0) begin - if (a[0]==1'b0) begin + if (a[0]==1'b0 && a[7:0]!=8'hF4) begin {spk,mic} <= din[4:3]; end end @@ -457,7 +459,7 @@ module ula_radas ( PaletteLoad = 1'b0; WriteToPortFE = 1'b0; if (iorq_n==1'b0 && wr_n==1'b0) begin - if (a[0]==1'b0) + if (a[0]==1'b0 && a[7:0]!=8'hF4) WriteToPortFE = 1'b1; else if (a[7:0]==TIMEXPORT) TimexConfigLoad = 1'b1; @@ -484,7 +486,7 @@ module ula_radas ( always @* begin dout = 8'hFF; if (iorq_n==1'b0 && rd_n==1'b0) begin - if (a[0]==1'b0) + if (a[0]==1'b0 && a[7:0]!=8'hF4) dout = {1'b1,post_processed_ear,1'b1,kbd}; else if (a==ULAPLUSADDR) dout = {1'b0,PaletteReg}; diff --git a/cores/Spectrum/zxuno.v b/cores/Spectrum/zxuno.v index 0d7ccfc..f02a0e1 100644 --- a/cores/Spectrum/zxuno.v +++ b/cores/Spectrum/zxuno.v @@ -65,7 +65,7 @@ module zxuno ( input wire joyleft, input wire joyright, input wire joyfire, - + // MOUSE inout wire mouseclk, inout wire mousedata, @@ -140,6 +140,7 @@ module zxuno ( wire issue2_keyboard; wire disable_contention; wire access_to_screen; + wire doc_ext_option; // bit 7 del puerto $FF del Timex // CoreID wire oe_n_coreid; @@ -218,7 +219,7 @@ module zxuno ( ); ula_radas la_ula ( - // Clocks + // Clocks .clk14(clk14), // 14MHz master clock .clk7(clk7), .wssclk(wssclk), // 5MHz WSS clock @@ -226,15 +227,15 @@ module zxuno ( .CPUContention(CPUContention), .rst_n(mrst_n & rst_n & power_on_reset_n), - // CPU interface - .a(cpuaddr), + // CPU interface + .a(cpuaddr), .access_to_contmem(access_to_screen), - .mreq_n(mreq_n), - .iorq_n(iorq_n), - .rd_n(rd_n), - .wr_n(wr_n), - .int_n(int_n), - .din(cpudout), + .mreq_n(mreq_n), + .iorq_n(iorq_n), + .rd_n(rd_n), + .wr_n(wr_n), + .int_n(int_n), + .din(cpudout), .dout(ula_dout), .rasterint_enable(rasterint_enable), .vretraceint_disable(vretraceint_disable), @@ -242,23 +243,24 @@ module zxuno ( .raster_int_in_progress(raster_int_in_progress), // VRAM interface - .va(vram_addr), // 16KB videoram - .vramdata(vram_dout), - + .va(vram_addr), // 16KB videoram, 2 pages + .vramdata(vram_dout), + // I/O ports - .ear(ear), - .mic(mic), - .spk(spk), - .kbd(kbdcol_to_ula), - .issue2_keyboard(issue2_keyboard), - .mode(timing_mode), - .disable_contention(disable_contention), + .ear(ear), + .mic(mic), + .spk(spk), + .kbd(kbdcol_to_ula), + .issue2_keyboard(issue2_keyboard), + .mode(timing_mode), + .disable_contention(disable_contention), + .doc_ext_option(doc_ext_option), // Video - .r(r), - .g(g), - .b(b), - .hsync(hsync), + .r(r), + .g(g), + .b(b), + .hsync(hsync), .vsync(vsync) ); @@ -303,7 +305,7 @@ module zxuno ( .sd_miso(sd_miso) ); - memory bootrom_rom_y_ram ( + new_memory bootrom_rom_y_ram ( // Relojes y reset .clk(clk), // Reloj del sistema CLK7 .mclk(clk), // Reloj para el modulo de memoria de doble puerto @@ -327,11 +329,16 @@ module zxuno ( // Interface con la ULA .vramaddr(vram_addr), .vramdout(vram_dout), + .doc_ext_option(doc_ext_option), .issue2_keyboard_enabled(issue2_keyboard), .timing_mode(timing_mode), .disable_contention(disable_contention), .access_to_screen(access_to_screen), + // Interface con el bus externo (TO-DO) + .inhibit_rom(1'b0), + .din_external(8'h00), + // Interface para registros ZXUNO .addr(zxuno_addr), .ior(zxuno_regrd), @@ -518,21 +525,21 @@ module zxuno ( .oe_n(oe_n_ay), .audio_out_ay1(ay1_audio), .audio_out_ay2(ay2_audio) - ); + ); /////////////////////////////////// // SOUND MIXER /////////////////////////////////// // 8-bit mixer to generate different audio levels according to input sources - mixer audio_mix( - .clkdac(clk), - .reset(1'b0), - .mic(mic), - .spk(spk), + mixer audio_mix( + .clkdac(clk), + .reset(1'b0), + .mic(mic), + .spk(spk), .ear(ear), .ay1(ay1_audio), - .ay2(ay2_audio), - .audio(audio_out) - ); + .ay2(ay2_audio), + .audio(audio_out) + ); endmodule diff --git a/firmware/firmware.asm b/firmware/firmware.asm index 88913c4..0c0d7b8 100644 --- a/firmware/firmware.asm +++ b/firmware/firmware.asm @@ -22,6 +22,7 @@ define scandbl_ctrl 11 define raster_line 12 define raster_ctrl 13 + define dev_control 14 define core_addr $fc define core_boot $fd define cold_boot $fe @@ -910,7 +911,37 @@ romsb sub $1e-$16 jp z, roms27 sub $6e-$1f ; n= New Entry jp nz, roms144 - call loadta + call qloadt + ld ix, cad54 + call_prnstr + dec c + ld a, %01000111 ; fondo blanco tinta azul + ld h, $12 + ld l, c + ld de, $0201 + call window + ld c, l + ld hl, $0200 + ld b, $18 + call inputv +; push bc +; push hl + ld a, (codcnt) + rrca + ret nc + call atoi + + call isbusy + ld bc, $090a +; pop hl +; pop bc + jr nc, romsb5 + ld ix, cad113 + call_prnstr + call_prnstr + call_prnstr + jp waitky +romsb5 call loadta jp nc, roms12 ld hl, %00001010 romsc ld (offsel), hl @@ -937,21 +968,8 @@ romsd dec iyh jr nz, romsc ei call romcyb - ld ix, cad54 - call_prnstr - dec c - ld a, %01000111 ; fondo blanco tinta azul - ld h, $12 - ld l, c - ld de, $0201 - call window - ld c, l - ld hl, $0200 - ld b, $18 - call inputv - ld a, (codcnt) - rrca - ret nc + + call newent call atoi ld (items), a @@ -1237,6 +1255,18 @@ roms27 ld hl, $0104 ld a, (codcnt) jp main13 +isbusy ld hl, indexe + ld b, a +isbus1 ld a, (hl) ; calculo en L el número de entradas + inc l + inc a + jr nz, isbus1 + ld a, l + ret + + +ret + ;*** Upgrade Menu *** ;********************* upgra ld bc, (menuop) @@ -1627,8 +1657,10 @@ buub ld a, (de) inc de jr nz, beeb djnz buub -beeb jr z, bien - pop hl + pop ix +sali pop bc + jr desc +beeb pop hl pop bc ld de, $0020 add hl, de @@ -1639,9 +1671,6 @@ desc pop hl pop de pop bc ret -bien pop ix -sali pop bc - jr desc trans push bc ld a, (tmpbu2+$d) @@ -2145,6 +2174,23 @@ addbl1 inc iyl sub iyl ret +;first part of loadta +qloadt ld ix, cad49 + call prnhel + call bloq1 + dec c + dec c + ld iyl, 5 +loadt1 ld ix, cad42 + call_prnstr + dec iyl + jr nz, loadt1 + ld ixl, cad43 & $ff + call_prnstr + ld ixl, cad44 & $ff + ld c, b + call_prnstr + ; ------------------------------------- ; Prits a blank line in the actual line ; ------------------------------------- @@ -2199,22 +2245,7 @@ shaon ld a, $0f ; ------------------------------------- ; Shows the window of Load from Tape ; ------------------------------------- -loadta ld ix, cad49 - call prnhel - call bloq1 - dec c - dec c - ld iyl, 5 -loadt1 ld ix, cad42 - call_prnstr - dec iyl - jr nz, loadt1 - ld ixl, cad43 & $ff - call_prnstr - ld ixl, cad44 & $ff - ld c, b - call_prnstr - call romcyb +loadta call qloadt ld ix, cad45 call_prnstr ld ix, tmpbuf @@ -3204,7 +3235,7 @@ conti di call calcu push hl pop ix - ld d, (ix+6) + ld d, (ix+2) ld hl, timing ld a, 3 cp (hl) ; timing @@ -3269,22 +3300,16 @@ conti3 ld de, $c000 | master_mapper inc a cp 24 jr nz, conti3 - defb $c2 -conti35 dec iyl - jr nz, conti5 -conti4 ld a, (ix+1) - ld iyl, a - ld a, (ix) - ld iyh, a -conti5 ld a, iyh - inc iyh +conti4 ld iyl, 8 +conti5 ld a, (ix) + inc (ix) call alto slot2a ld a, master_mapper dec b out (c), a inc b - ld a, (ix+2) - inc (ix+2) + ld a, iyl + inc iyl out (c), a ld de, $c000 ld a, $40 @@ -3321,18 +3346,18 @@ conti6 in a, (c) jr z, conti6 conti7 pop bc pop ix -conti8 dec (ix+3) - jr nz, conti35 +conti8 dec (ix+1) + jr nz, conti5 conti9 ld a, 0 dec b out (c), 0;d inc b out (c), a - ld bc, $1ffd - ld a, (ix+4) + dec b + ld a, dev_control out (c), a - ld b, $7f - ld a, (ix+5) + inc b + ld a, (ix+3) out (c), a rst 0 @@ -4455,6 +4480,9 @@ cad109 defb '63.8', 0 cad110 defb '1X', 0 cad111 defb '2X', 0 cad112 defb 'Break to exit', 0 +cad113 defb 'Slot occupied, select', 0 + defb 'another or delete a', 0 + defb 'ROM to free it', 0 ;cad199 defb 'af0000 bc0000 de0000 hl0000 sp0000 ix0000 iy0000', 0 fincad diff --git a/firmware/generamcs.bat b/firmware/generamcs.bat index e906627..d38cbeb 100644 --- a/firmware/generamcs.bat +++ b/firmware/generamcs.bat @@ -19,27 +19,27 @@ call :CreateMachine CORE8 "Acorn Atom (VGA)" AcornAtom\AcornAtom.%2.bit 0 %3 call :CreateMachine CORE9 "NES (VGA)" NES\xilinx\nes_zxuno.%2.bit 0 %3 copy /y rom_binaries\esxdos.rom sd_binaries\ESXDOS.%3 copy /y firmware.rom sd_binaries\FIRMWARE.%3 -GenRom 0 202 0 0 0 BIOS firmware.rom core_taps\FIRMWARE.TAP -GenRom 0 0 0 0 0 ESXDOS rom_binaries\esxdos.rom core_taps\ESXDOS.TAP -call :CreateRom 0 "ZX Spectrum 48K Cargando Leches" leches dn 8 4 0 0 -call :CreateRom 1 "ZX +3e DivMMC" plus3en40divmmc t 8 4 0 0 -call :CreateRom 5 "SE Basic IV 4.0 Anya" se d 8 4 0 0 -call :CreateRom 7 "ZX Spectrum 48K" 48 dn 8 4 0 32 -call :CreateRom 8 "Jet Pac (1983)" JetPac 0 8 1 0 32 -call :CreateRom 9 "Pssst (1983)" Pssst 0 8 1 0 32 -call :CreateRom 10 "Cookie (1983)" Cookie 0 8 1 0 32 -call :CreateRom 11 "Tranz Am (1983)" TranzAm 0 8 1 0 32 -call :CreateRom 12 "Master Chess (1983)" MasterChess 0 8 1 0 32 -call :CreateRom 13 "Backgammon (1983)" Backgammon 0 8 1 0 32 -call :CreateRom 14 "Hungry Horace (1983)" HungryHorace 0 8 1 0 32 -call :CreateRom 15 "Horace & the Spiders (1983)" HoraceSpiders 0 8 1 0 32 -call :CreateRom 16 "Planetoids (1983)" Planetoids 0 8 1 0 32 -call :CreateRom 17 "Space Raiders (1983)" SpaceRaiders 0 8 1 0 32 -call :CreateRom 18 "Deathchase (1983)" Deathchase 0 8 1 0 32 -call :CreateRom 19 "Manic Miner (1983)" ManicMiner 0 8 1 0 32 -call :CreateRom 20 "Misco Jones (2013)" MiscoJones 0 8 1 0 32 -call :CreateRom 21 "Jet Set Willy (1984)" JetSetWilly 0 8 1 0 32 -call :CreateRom 22 "Lala Prologue (2010)" LalaPrologue 0 8 1 0 32 +GenRom 0 sf1t BIOS firmware.rom core_taps\FIRMWARE.TAP +GenRom 0 0 ESXDOS rom_binaries\esxdos.rom core_taps\ESXDOS.TAP +call :CreateRom 0 "ZX Spectrum 48K Cargando Leches" leches dn 0 +call :CreateRom 1 "ZX +3e DivMMC" plus3en40divmmc t 0 +call :CreateRom 5 "SE Basic IV 4.0 Anya" se d 0 +call :CreateRom 7 "ZX Spectrum 48K" 48 dn 17 +call :CreateRom 8 "Jet Pac (1983)" JetPac 0 17 +call :CreateRom 9 "Pssst (1983)" Pssst 0 17 +call :CreateRom 10 "Cookie (1983)" Cookie 0 17 +call :CreateRom 11 "Tranz Am (1983)" TranzAm 0 17 +call :CreateRom 12 "Master Chess (1983)" MasterChess 0 17 +call :CreateRom 13 "Backgammon (1983)" Backgammon 0 17 +call :CreateRom 14 "Hungry Horace (1983)" HungryHorace 0 17 +call :CreateRom 15 "Horace & the Spiders (1983)" HoraceSpiders 0 17 +call :CreateRom 16 "Planetoids (1983)" Planetoids 0 17 +call :CreateRom 17 "Space Raiders (1983)" SpaceRaiders 0 17 +call :CreateRom 18 "Deathchase (1983)" Deathchase 0 17 +call :CreateRom 19 "Manic Miner (1983)" ManicMiner 0 17 +call :CreateRom 20 "Misco Jones (2013)" MiscoJones 0 17 +call :CreateRom 21 "Jet Set Willy (1984)" JetSetWilly 0 17 +call :CreateRom 22 "Lala Prologue (2010)" LalaPrologue 0 17 srec_cat FLASH.ZX1 -binary ^ -o prom.%2.mcs -Intel ^ -line-length=44 ^ @@ -54,13 +54,13 @@ IF EXIST ..\cores\%3 ( ) ELSE ( Bit2Bin ..\cores\%4 sd_binaries\%1.%5 ) -GenRom 0 0 0 0 0 %2 sd_binaries\%1.%5 core_taps\%1.TAP +GenRom 0 0 %2 sd_binaries\%1.%5 core_taps\%1.TAP AddItem %1 core_taps\%1.tap rem CgLeches core_taps\%1.TAP core_wavs\%1.WAV 4 goto :eof :CreateRom -GenRom %4 %5 %6 %7 %8 %2 rom_binaries\%3.rom rom_taps\%3.tap +GenRom %4 %5 %2 rom_binaries\%3.rom rom_taps\%3.tap AddItem ROM %1 rom_taps\%3.tap rem CgLeches rom_taps\%3.tap rom_wavs\%3.wav 4 :eof