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Añado últimos cambios de McLeod al test21

This commit is contained in:
antoniovillena 2016-06-28 23:46:18 +02:00
parent a922eef849
commit 99cc4a8f67
9 changed files with 145 additions and 48 deletions
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35
cores/Spectrum/control_enable_options.v
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@ -28,7 +28,7 @@ module control_enable_options(
input wire zxuno_regwr,
input wire [7:0] din,
output reg [7:0] dout,
output wire oe_n,
output reg oe_n,
output wire disable_ay,
output wire disable_turboay,
output wire disable_7ffd,
@ -36,13 +36,17 @@ module control_enable_options(
output wire disable_romsel7f,
output wire disable_romsel1f,
output wire enable_timexmmu,
output wire disable_spisd
output wire disable_spisd,
output wire disable_timexscr,
output wire disable_ulaplus,
output wire disable_radas
);
parameter DEVOPTIONS = 8'h0E;
parameter DEVOPTS2 = 8'h0F;
assign oe_n = ~(zxuno_addr == DEVOPTIONS && zxuno_regrd == 1'b1);
reg [7:0] devoptions = 8'h00; // initial value
reg [7:0] devopts2 = 8'h00; // initial value
assign disable_ay = devoptions[0];
assign disable_turboay = devoptions[1];
assign disable_7ffd = devoptions[2];
@ -51,11 +55,32 @@ module control_enable_options(
assign disable_romsel1f = devoptions[5];
assign enable_timexmmu = devoptions[6];
assign disable_spisd = devoptions[7];
assign disable_timexscr = devopts2[0];
assign disable_ulaplus = devopts2[1];
assign disable_radas = devopts2[2];
always @(posedge clk) begin
if (rst_n == 1'b0)
if (rst_n == 1'b0) begin
devoptions <= 8'h00; // or after a hardware reset (not implemented yet)
devopts2 <= 8'h00;
end
else if (zxuno_addr == DEVOPTIONS && zxuno_regwr == 1'b1)
devoptions <= din;
dout <= devoptions;
else if (zxuno_addr == DEVOPTS2 && zxuno_regwr == 1'b1)
devopts2 <= din;
end
always @* begin
oe_n = 1'b1;
dout = 8'hFF;
if (zxuno_regrd == 1'b1)
if (zxuno_addr == DEVOPTIONS) begin
oe_n = 1'b0;
dout = devoptions;
end
else if (zxuno_addr == DEVOPTS2) begin
oe_n = 1'b0;
dout = devopts2;
end
end
endmodule

8
cores/Spectrum/coreid.v
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@ -26,7 +26,7 @@ module coreid (
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire regaddr_changed,
output wire [7:0] dout,
output reg [7:0] dout,
output wire oe_n
);
@ -40,9 +40,9 @@ module coreid (
text[ 2] = "1";
text[ 3] = "-";
text[ 4] = "2";
text[ 5] = "2";
text[ 5] = "3";
text[ 6] = "0";
text[ 7] = "5";
text[ 7] = "6";
text[ 8] = "2";
text[ 9] = "0";
text[10] = "1";
@ -52,7 +52,6 @@ module coreid (
reg [3:0] textindx = 4'h0;
reg reading = 1'b0;
assign oe_n = !(zxuno_addr == 8'hFF && zxuno_regrd==1'b1);
assign dout = (oe_n==1'b0)? text[textindx] : 8'hZZ;
always @(posedge clk) begin
if (rst_n == 1'b0 || (regaddr_changed==1'b1 && zxuno_addr==8'hFF)) begin
@ -66,5 +65,6 @@ module coreid (
reading <= 1'b0;
textindx <= textindx + 1;
end
dout <= text[textindx];
end
endmodule

8
cores/Spectrum/new_memory.v
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@ -23,7 +23,7 @@
module new_memory (
// Relojes y reset
input wire clk, // Reloj del sistema CLK7
input wire clk, // Reloj de la CPU
input wire mclk, // Reloj para la BRAM
input wire mrst_n,
input wire rst_n,
@ -200,12 +200,12 @@ module new_memory (
if (!disable_1ffd && !disable_7ffd) begin
if (!iorq_n && !wr_n && `ADDR_1FFD && !puerto_bloqueado)
bankplus3 <= din;
if (!iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado)
else if (!iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado)
bank128 <= din;
end
if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado)
else if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado)
bank128 <= din;
if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU)
else if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU)
timex_mmu <= din;
end
end

9
cores/Spectrum/pines_zxuno_v4.ucf
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@ -87,5 +87,10 @@ NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "cpuclk" PERIOD=35.555 ns; # 28.125 MHz max
NET "cpuclkplain" PERIOD=35.555 ns; # 28.125 MHz max
NET "cpuclk" PERIOD=71.111 ns;
NET "cpuclkplain" PERIOD=71.111 ns;
NET "clk50mhz" PERIOD=20 ns;
NET "sysclk" PERIOD=35.555 ns;
NET "clk14" PERIOD=71.111 ns;
NET "clk7" PERIOD=142.222 ns;
NET "clk3d5" PERIOD=284.444 ns;

6
cores/Spectrum/rom.v
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@ -24,16 +24,16 @@ module rom (
output reg [7:0] dout
);
reg [7:0] mem[0:255];
reg [7:0] mem[0:8191];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
for (i=0;i<256;i=i+1) begin
for (i=0;i<8192;i=i+1) begin
mem[i] = 8'h00;
end
$readmemh ("bootloader_hex.txt", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a[7:0]];
dout <= mem[a[12:0]];
end
endmodule

2
cores/Spectrum/tld_zxuno.v
View File

@ -119,7 +119,7 @@ module tld_zxuno (
.ear(~ear), // negada porque el hardware tiene un transistor inversor
.audio_out(audio_out),
.sram_addr(sram_addr),
.sram_addr(sram_addr[18:0]),
.sram_data(sram_data),
.sram_we_n(sram_we_n),

53
cores/Spectrum/ula_radas.v
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@ -49,6 +49,11 @@ module ula_radas (
output reg [13:0] va, // 16KB videoram
input wire [7:0] vramdata,
// ZX-UNO register interface
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
// I/O ports
input wire ear,
input wire [4:0] kbd,
@ -60,6 +65,9 @@ module ula_radas (
input wire access_to_contmem,
output wire doc_ext_option,
input wire enable_timexmmu,
input wire disable_timexscr,
input wire disable_ulaplus,
input wire disable_radas,
// Video
output wire [2:0] r,
@ -275,15 +283,25 @@ module ula_radas (
end
// ConfigReg register (ULAplus)
reg [1:0] ConfigReg = 2'b00;
wire ULAplusEnabled = ConfigReg[0];
assign RadasEnabled = ConfigReg[1];
reg ConfigReg = 1'b0;
always @(posedge clkregs) begin
if (rst_n == 1'b0)
ConfigReg <= 2'b00;
ConfigReg <= 1'b0;
else if (ConfigRegLoad)
ConfigReg <= din[1:0];
ConfigReg <= din[0];
end
// RadasCtrl register
reg [1:0] RadasCtrl = 2'b00;
always @(posedge clkregs) begin
if (rst_n == 1'b0)
RadasCtrl <= 2'b00;
else if (zxuno_addr == RADASCTRL && zxuno_regwr == 1'b1 && disable_radas == 1'b0)
RadasCtrl <= din[1:0];
end
assign RadasEnabled = &RadasCtrl[1:0];
wire ULAplusEnabled = ConfigReg | RadasEnabled;
// Palette LUT
wire [7:0] PaletteEntryToCPU;
@ -440,10 +458,11 @@ module ula_radas (
///////////////////////////////////////////////
parameter
TIMEXPORT = 8'hFF,
TIMEXMMU = 8'hF4,
ULAPLUSADDR = 16'hBF3B,
ULAPLUSDATA = 16'hFF3B;
TIMEXPORT = 8'hFF,
TIMEXMMU = 8'hF4,
ULAPLUSADDR = 16'hBF3B,
ULAPLUSDATA = 16'hFF3B,
RADASCTRL = 8'h40;
// Z80 writes values into registers
// Port 0xFE
@ -463,11 +482,11 @@ module ula_radas (
if (iorq_n==1'b0 && wr_n==1'b0) begin
if (a[0]==1'b0 && a[7:0]!=TIMEXMMU)
WriteToPortFE = 1'b1;
else if (a[7:0]==TIMEXPORT)
else if (a[7:0]==TIMEXPORT && !disable_timexscr)
TimexConfigLoad = 1'b1;
else if (a==ULAPLUSADDR)
else if (a==ULAPLUSADDR && !disable_ulaplus)
PaletteRegLoad = 1'b1;
else if (a==ULAPLUSDATA) begin
else if (a==ULAPLUSDATA && !disable_ulaplus) begin
if (PaletteReg[6]==1'b0) // writting a new value into palette LUT
PaletteLoad = 1'b1;
else
@ -490,13 +509,15 @@ module ula_radas (
if (iorq_n==1'b0 && rd_n==1'b0) begin
if (a[0]==1'b0 && a[7:0]!=8'hF4)
dout = {1'b1,post_processed_ear,1'b1,kbd};
else if (a==ULAPLUSADDR)
else if (zxuno_addr == RADASCTRL && zxuno_regrd == 1'b1 && !disable_radas)
dout = {6'b000000,RadasCtrl};
else if (a==ULAPLUSADDR && !disable_ulaplus)
dout = {1'b0,PaletteReg};
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b0)
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b0 && !disable_ulaplus)
dout = PaletteEntryToCPU;
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1)
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1 && !disable_ulaplus)
dout = {7'b0000000,ConfigReg};
else if (a[7:0]==TIMEXPORT && enable_timexmmu)
else if (a[7:0]==TIMEXPORT && enable_timexmmu && !disable_timexscr)
dout = TimexConfigReg;
else begin
if (BitmapAddr || AttrAddr)

54
cores/Spectrum/vga_scandoubler.v
View File

@ -49,13 +49,7 @@ module vga_scandoubler (
reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
reg [9:0] totalhor = 10'd0;
// Para generar scanlines:
wire [2:0] rout, gout, bout;
reg scaneffect = 1'b0;
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : {1'b0, rout[2:1]};
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : {1'b0, gout[2:1]};
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : {1'b0, bout[2:1]};
// Memoria de doble puerto que guarda la información de dos scans
// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
// puntos en negro que se pintan durante el HBlank
@ -67,11 +61,24 @@ module vga_scandoubler (
.din({ri,gi,bi}),
.dout({rout,gout,bout})
);
// Para generar scanlines:
reg scaneffect = 1'b0;
wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
color_dimmed apply_to_red (rout, rout_dimmed);
color_dimmed apply_to_green (gout, gout_dimmed);
color_dimmed apply_to_blue (bout, bout_dimmed);
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
// En "totalhor" mido el número de ciclos de reloj que hay en un scan
always @(posedge clkvideo) begin
// if (vsync_ext_n == 1'b0) begin
// addrvideo <= 11'd0;
// end
if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
totalhor <= addrvideo[9:0];
addrvideo <= {~addrvideo[10],10'b0000000000};
@ -89,12 +96,16 @@ module vga_scandoubler (
// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
// reducido para un efecto chachi de scanlines en la VGA
always @(posedge clkvga) begin
if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
addrvga <= {~addrvga[10],10'b000000000};
// if (vsync_ext_n == 1'b0) begin
// addrvga <= 11'b10000000000;
// scaneffect <= 1'b0;
// end
if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
addrvga <= {addrvga[10], 10'b000000000};
scaneffect <= ~scaneffect;
end
else if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
addrvga <= {addrvga[10], 10'b000000000};
else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
addrvga <= {~addrvga[10],10'b000000000};
scaneffect <= ~scaneffect;
end
else
@ -173,3 +184,24 @@ module vgascanline_dport (
scan[addrwrite] <= din;
end
endmodule
module color_dimmed (
input wire [2:0] in,
output reg [2:0] out // out is scaled to roughly 70% of in
);
always @* begin // a LUT
case (in)
3'd0 : out = 3'd0;
3'd1 : out = 3'd1;
3'd2 : out = 3'd1;
3'd3 : out = 3'd2;
3'd4 : out = 3'd3;
3'd5 : out = 3'd3;
3'd6 : out = 3'd4;
3'd7 : out = 3'd5;
default: out = 3'd0;
endcase
end
endmodule

18
cores/Spectrum/zxuno.v
View File

@ -171,6 +171,9 @@ module zxuno (
wire disable_romsel1f;
wire enable_timexmmu;
wire disable_spisd;
wire disable_timexscr;
wire disable_ulaplus;
wire disable_radas;
wire [7:0] devoptions_dout;
wire oe_n_devoptions;
@ -264,6 +267,11 @@ module zxuno (
.va(vram_addr), // 16KB videoram, 2 pages
.vramdata(vram_dout),
// ZX-UNO register interface
.zxuno_addr(zxuno_addr),
.zxuno_regrd(zxuno_regrd),
.zxuno_regwr(zxuno_regwr),
// I/O ports
.ear(ear),
.mic(mic),
@ -274,6 +282,9 @@ module zxuno (
.disable_contention(disable_contention),
.doc_ext_option(doc_ext_option),
.enable_timexmmu(enable_timexmmu),
.disable_timexscr(disable_timexscr),
.disable_ulaplus(disable_ulaplus),
.disable_radas(disable_radas),
// Video
.r(r),
@ -300,7 +311,7 @@ module zxuno (
);
flash_and_sd cacharros_con_spi (
.clk(clk28),
.clk(clk14),
.a(cpuaddr),
.iorq_n(iorq_n),
.rd_n(rd_n),
@ -461,7 +472,10 @@ module zxuno (
.disable_romsel7f(disable_romsel7f),
.disable_romsel1f(disable_romsel1f),
.enable_timexmmu(enable_timexmmu),
.disable_spisd(disable_spisd)
.disable_spisd(disable_spisd),
.disable_timexscr(disable_timexscr),
.disable_ulaplus(disable_ulaplus),
.disable_radas(disable_radas)
);
scandoubler_ctrl control_scandoubler (